JP2013038224A - Manufacturing method of electronic apparatus and electronic apparatus - Google Patents

Manufacturing method of electronic apparatus and electronic apparatus Download PDF

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JP2013038224A
JP2013038224A JP2011173085A JP2011173085A JP2013038224A JP 2013038224 A JP2013038224 A JP 2013038224A JP 2011173085 A JP2011173085 A JP 2011173085A JP 2011173085 A JP2011173085 A JP 2011173085A JP 2013038224 A JP2013038224 A JP 2013038224A
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solder
spacer
spacers
resin
manufacturing
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JP5763467B2 (en
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Yayoi Matsushita
弥生 松下
Tsugio Masuda
次男 増田
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Honda Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of an electronic apparatus and the electronic apparatus which control the thickness of solder while ensuring the insulation quality.SOLUTION: In a manufacturing method of an electronic apparatus 1, a substrate 7 is disposed on the metal plate 9 through solder 5, 11 and electronic components 3, 7 are disposed on the substrate through the solder 5. Then, the solder 5, 11 is reflow heated and soldering is conducted. Spacers 21, 22, which are made of an insulative resin and melt and closely contact with the solder during reflow heating, are respectively disposed at outer peripheries of the solder 5, 11. After the reflow heating, the electronic component 3 and the substrate 7 are resin sealed by a sealing resin 15.

Description

本発明は、金属板上にはんだを介して電子部品を実装した電子装置及び電子装置の製造方法に関する。   The present invention relates to an electronic device in which an electronic component is mounted on a metal plate via solder and a method for manufacturing the electronic device.

従来、パワー半導体装置等の電子装置の製造工程では、放熱板（金属板）に電子部品としての半導体素子及び絶縁基板をはんだを介して積層し、加熱（リフロー）処理にてはんだ接合を行う。次いで、この放熱板に端子一体形のケースを接着し、端子と半導体素子とをボンディングワイヤで接続して内部配線を施す。この状態でケース内に絶縁封止樹脂（例えば、シリコーン樹脂）を充填して回路を封止し電気絶縁する。   Conventionally, in a manufacturing process of an electronic device such as a power semiconductor device, a semiconductor element as an electronic component and an insulating substrate are laminated on a heat radiating plate (metal plate) via solder, and solder joining is performed by heating (reflow) processing. Next, a terminal-integrated case is bonded to the heat radiating plate, and the terminal and the semiconductor element are connected by a bonding wire to provide internal wiring. In this state, the case is filled with an insulating sealing resin (for example, silicone resin), the circuit is sealed and electrically insulated.

ところで、パワー半導体装置では、通電によって熱が発生するが、パワー半導体装置の各構成部品は線膨張係数が異なることから、はんだに歪みが生じ、はんだの亀裂や剥離の発生・進展による熱的及び電気的性能の低下が発生する可能性がある。
はんだの厚さを厚くするとはんだの歪みが小さくなり耐久信頼性が向上するが、はんだが厚すぎるとはんだでの熱抵抗が増加し放熱性が低下してしまう。したがって、はんだの厚さ（高さ）は、耐久信頼性を得るための下限値から放熱性能を満足する上限値までの範囲で管理する必要がある。
そこで、従来、はんだの高さを制御するため、はんだの周囲にスペーサを配置してパワー半導体装置を製造する製造方法知られている（例えば、特許文献１参照）。 By the way, in a power semiconductor device, heat is generated by energization, but each component of the power semiconductor device has a different coefficient of linear expansion, so that the solder is distorted, and the thermal and A decrease in electrical performance may occur.
If the thickness of the solder is increased, the distortion of the solder is reduced and the durability reliability is improved. However, if the solder is too thick, the thermal resistance of the solder is increased and the heat dissipation is reduced. Therefore, it is necessary to manage the thickness (height) of the solder in a range from a lower limit value for obtaining durability reliability to an upper limit value satisfying the heat radiation performance.
Therefore, conventionally, a manufacturing method for manufacturing a power semiconductor device by arranging a spacer around the solder in order to control the height of the solder is known (see, for example, Patent Document 1).

特開２００６−２４５４３５号公報JP 2006-245435 A

しかしながら、上記従来の製造方法では、スペーサの外周部を絶縁封止する場合、スペーサが封止樹脂の流動を阻害し、封止樹脂と周辺部品との密着性が不足し、絶縁性が低下するおそれがある。
本発明は、上述した事情に鑑みてなされたものであり、絶縁性を確保しつつ、はんだの厚さを制御可能な電子装置の製造方法及び電子装置を提供することを目的とする。 However, in the above-described conventional manufacturing method, when the outer peripheral portion of the spacer is insulated and sealed, the spacer hinders the flow of the sealing resin, the adhesion between the sealing resin and the peripheral parts is insufficient, and the insulating property is lowered. There is a fear.
The present invention has been made in view of the above-described circumstances, and an object thereof is to provide an electronic device manufacturing method and an electronic device capable of controlling the thickness of solder while ensuring insulation.

上記目的を達成するために、本発明は、金属板上にはんだを介して電子部品を配置し、前記はんだをリフロー加熱してはんだ付けする電子装置の製造方法において、前記はんだの外周部に、絶縁性樹脂からなり、前記リフロー加熱時に溶融して前記はんだと密接するスペーサを配置し、前記リフロー加熱後に前記電子部品を樹脂封止することを特徴とする。
上記構成によれば、スペーサによってはんだの厚さを制御できる。また、スペーサがはんだと密接するため、スペーサが封止樹脂の流動を阻害することがなく、封止樹脂と周辺部品との密着性を図ることができる。また、線膨張係数が異なる電子部品と封止樹脂との間に線膨張係数が中間の絶縁性樹脂からなるスペーサが位置することとなるため、各部品界面での応力を緩和し、はんだの亀裂や剥離を抑制できる。 In order to achieve the above object, the present invention provides an electronic device manufacturing method in which an electronic component is disposed on a metal plate via solder, and the solder is soldered by reflow heating. A spacer made of an insulating resin, which is melted during the reflow heating and is in close contact with the solder, is disposed, and the electronic component is resin-sealed after the reflow heating.
According to the above configuration, the thickness of the solder can be controlled by the spacer. Further, since the spacer is in close contact with the solder, the spacer does not hinder the flow of the sealing resin, and the adhesion between the sealing resin and the peripheral component can be achieved. In addition, a spacer made of an insulating resin having an intermediate linear expansion coefficient is located between the electronic component having a different linear expansion coefficient and the sealing resin. And peeling can be suppressed.

上記構成において、前記スペーサに半硬化状態の樹脂シートを使用してもよい。
上記構成によれば、スペーサが半硬化状態であるため、加熱時に流動性が向上してはんだと周辺部品との間の隙間にも入り込み、各部品界面の密着性を向上させることができる。また、スペーサが半硬化状態であるため、加熱時の軟化による粘度低下が比較的少なく、スペーサとしての高さを維持できる。 In the above configuration, a semi-cured resin sheet may be used for the spacer.
According to the said structure, since a spacer is a semi-hardened state, fluidity | liquidity improves at the time of a heating, it also penetrates into the clearance gap between a solder and peripheral components, and can improve the adhesiveness of each component interface. Moreover, since the spacer is in a semi-cured state, the viscosity decrease due to softening during heating is relatively small, and the height as the spacer can be maintained.

上記構成において、前記スペーサを、角形の前記電子部品の少なくとも角部に４カ所以上点接触あるいは線接触するように設置してもよい。
上記構成によれば、はんだの亀裂や剥離が生じやすい電子部品の角部にスペーサを配置したため、はんだの亀裂や剥離を確実に抑制できる。 The said structure WHEREIN: You may install the said spacer so that at least four corners of the said square electronic component may be in point contact or line contact.
According to the said structure, since the spacer was arrange | positioned in the corner | angular part of the electronic component which is easy to produce the crack and peeling of a solder, the crack and peeling of a solder can be suppressed reliably.

また、本発明は、金属板上にはんだを介して電子部品を配置し、前記はんだをリフロー加熱してはんだ付けする電子装置の製造方法において、前記はんだの外周部に、絶縁性樹脂からなり、前記リフロー加熱時に溶融して前記はんだと密接するスペーサを配置し、前記リフロー加熱後に前記電子部品を樹脂封止することを特徴とする。
上記構成によれば、スペーサによってはんだの厚さを制御できる。また、スペーサがはんだと密接するため、スペーサが封止樹脂の流動を阻害することがなく、封止樹脂と周辺部品との密着性を図ることができる。また、線膨張係数が異なる電子部品と封止樹脂との間に線膨張係数が中間の絶縁性樹脂からなるスペーサが位置することとなるため、各部品界面での応力を緩和し、はんだの亀裂や剥離を抑制できる。 Further, the present invention is an electronic device manufacturing method in which an electronic component is disposed on a metal plate via solder, and the solder is soldered by reflow heating, and the outer peripheral portion of the solder is made of an insulating resin, A spacer which is melted during the reflow heating and is in close contact with the solder is disposed, and the electronic component is resin-sealed after the reflow heating.
According to the above configuration, the thickness of the solder can be controlled by the spacer. Further, since the spacer is in close contact with the solder, the spacer does not hinder the flow of the sealing resin, and the adhesion between the sealing resin and the peripheral component can be achieved. In addition, a spacer made of an insulating resin having an intermediate linear expansion coefficient is located between the electronic component having a different linear expansion coefficient and the sealing resin. And peeling can be suppressed.

本発明によれば、スペーサによってはんだの厚さを制御できるとともに、スペーサがはんだと密接するため、スペーサが封止樹脂の流動を阻害することがなく、封止樹脂と周辺部品との密着性を図ることができ、その結果、電子装置の絶縁性を確保できる。また、線膨張係数が異なる電子部品と封止樹脂との間に線膨張係数が中間の絶縁性樹脂からなるスペーサが位置することとなるため、各部品界面での応力を緩和し、はんだの亀裂や剥離を抑制できる。   According to the present invention, the thickness of the solder can be controlled by the spacer, and since the spacer is in close contact with the solder, the spacer does not hinder the flow of the sealing resin, and the adhesion between the sealing resin and the peripheral component is improved. As a result, the insulation of the electronic device can be secured. In addition, a spacer made of an insulating resin having an intermediate linear expansion coefficient is located between the electronic component having a different linear expansion coefficient and the sealing resin. And peeling can be suppressed.

また、スペーサが半硬化状態であるため、加熱時に流動性が向上してはんだと周辺部品との間の隙間にも入り込み、各部品界面の密着性を向上させることができ、電子装置の絶縁性をより確実に確保できる。スペーサが半硬化状態であるため、加熱時の軟化による粘度低下が比較的少なく、スペーサとしての高さを維持できる。   In addition, since the spacer is semi-cured, it improves fluidity when heated and enters the gap between the solder and the peripheral component, improving the adhesion at the interface of each component, and insulating the electronic device. Can be secured more reliably. Since the spacer is in a semi-cured state, the viscosity decrease due to softening during heating is relatively small, and the height as the spacer can be maintained.

また、はんだの亀裂や剥離が生じやすい電子部品の角部にスペーサを配置したため、はんだの亀裂や剥離を確実に抑制できる。   In addition, since the spacers are arranged at the corners of the electronic component where solder cracks and peeling easily occur, the solder cracks and peeling can be reliably suppressed.

本発明の実施の形態に係る電子装置としてのパワー半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the power semiconductor device as an electronic device which concerns on embodiment of this invention. 加熱時間とスペーサの粘度との関係を示すグラフである。It is a graph which shows the relationship between a heating time and the viscosity of a spacer. 加熱温度とスペーサの粘度との関係を示すグラフである。It is a graph which shows the relationship between heating temperature and the viscosity of a spacer. スペーサの配置位置を示す図である。It is a figure which shows the arrangement position of a spacer. スペーサとはんだとの間の隙間とスペーサに対するはんだの厚さ率との関係を示すグラフである。It is a graph which shows the relationship between the clearance gap between a spacer and solder, and the thickness ratio of the solder with respect to a spacer. パワー半導体装置の製造方法における積層工程を示す説明図である。It is explanatory drawing which shows the lamination process in the manufacturing method of a power semiconductor device. パワー半導体装置の製造方法におけるリフロー行程を示す説明図である。It is explanatory drawing which shows the reflow process in the manufacturing method of a power semiconductor device. はんだ及びスペーサの溶融状態を示すグラフである。It is a graph which shows the fusion state of solder and a spacer. はんだ及びスペーサの溶融状態を示す説明図である。It is explanatory drawing which shows the molten state of a solder and a spacer. リフロー加熱後の積層体を示す図である。It is a figure which shows the laminated body after reflow heating. パワー半導体装置の製造方法におけるケース接着行程を示す説明図である。It is explanatory drawing which shows the case adhesion process in the manufacturing method of a power semiconductor device.

以下、図面を参照して本発明の実施の形態について説明する。
図１は、本実施の形態に係る電子装置としてのパワー半導体装置を模式的に示す断面図である。図２は加熱時間とスペーサの粘度との関係を示すグラフであり、図３は加熱温度とスペーサの粘度との関係を示すグラフである。また、図４は、スペーサの配置位置を示す図である。
図１に示すように、パワー半導体装置１は、電気自動車等の電力変換装置に用いられる三相インバータ回路の交流出力１相分の回路をパッケージ化したものである。すなわち、パワー半導体装置１は、１相分の回路を構成する半導体チップ３（電子部品）及びダイオード等の回路素子をはんだ５を介して絶縁回路基板（電子部品）７に実装し、当該絶縁回路基板７を、パッケージ底面を構成するベース板としての放熱板（金属板）９の上にはんだ１１で接合固定し、その周囲を囲む側壁たる樹脂ケース１３を放熱板９に設け、樹脂ケース１３内を絶縁封止樹脂からなる封止剤（例えば、シリコーン樹脂）たる封止樹脂１５で封止して構成されている。 Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view schematically showing a power semiconductor device as an electronic device according to the present embodiment. FIG. 2 is a graph showing the relationship between the heating time and the spacer viscosity, and FIG. 3 is a graph showing the relationship between the heating temperature and the spacer viscosity. FIG. 4 is a diagram showing the arrangement positions of the spacers.
As shown in FIG. 1, the power semiconductor device 1 is a package of a circuit for one phase of an AC output of a three-phase inverter circuit used in a power conversion device such as an electric vehicle. That is, the power semiconductor device 1 mounts a semiconductor chip 3 (electronic component) and a circuit element such as a diode constituting a circuit for one phase on an insulating circuit substrate (electronic component) 7 via a solder 5, and the insulating circuit The substrate 7 is bonded and fixed to a heat radiating plate (metal plate) 9 as a base plate constituting the bottom surface of the package with solder 11, and a resin case 13 as a side wall surrounding the periphery is provided on the heat radiating plate 9. Is sealed with a sealing resin 15 which is a sealing agent (for example, silicone resin) made of an insulating sealing resin.

半導体チップ３は、例えば、ＩＧＢＴ、パワーＭＯＳＦＥＴ、サイリスタ、ダイオード等の大電流に対応した電源供給用のスイッチング素子であり、絶縁回路基板７は、金属板から成る上面基板７Ａ及び下面基板７Ｂの間に絶縁基板７Ｃを挟んでロウ材等により接合してなる３層構造の基板である。本実施の形態では、半導体チップ３及び絶縁回路基板７は角形に形成されている。なお、上面基板７Ａ及び下面基板７Ｂを金属板ではなく導体層で形成しても良い。放熱板９は、例えば銅やアルミニウムなどの高熱伝導性を有する金属で構成された板材である。   The semiconductor chip 3 is a switching element for supplying power corresponding to a large current, such as an IGBT, a power MOSFET, a thyristor, or a diode, and the insulating circuit board 7 is between a top board 7A and a bottom board 7B made of a metal plate. A substrate having a three-layer structure in which an insulating substrate 7C is sandwiched and joined by brazing material or the like. In the present embodiment, the semiconductor chip 3 and the insulated circuit board 7 are formed in a square shape. The upper substrate 7A and the lower substrate 7B may be formed of a conductor layer instead of a metal plate. The heat sink 9 is a plate material made of a metal having high thermal conductivity such as copper or aluminum.

また、パワー半導体装置１には、パッケージ内から外部に樹脂ケース１３を貫通して、半導体チップ３の周辺電極たる外部端子１７が設けられている。外部端子１７は半導体チップ３と導電ワイヤたるアルミニウム製のアルミワイヤ１９により電気的に接続される。すなわち、アルミワイヤ１９は、太さ数十μｍ〜数百μｍの線材であり、その一端が半導体チップ３のチップ表面５Ａに荷重と超音波によって接合され、他端は同様にして外部端子１７に接合されている。パワー半導体装置１の製造時には、かかる接合工程が行われた後、封止樹脂１５で封止される。   Further, the power semiconductor device 1 is provided with an external terminal 17 that is a peripheral electrode of the semiconductor chip 3 through the resin case 13 from the inside of the package to the outside. The external terminal 17 is electrically connected to the semiconductor chip 3 by an aluminum wire 19 made of aluminum as a conductive wire. That is, the aluminum wire 19 is a wire having a thickness of several tens μm to several hundreds μm, one end of which is bonded to the chip surface 5A of the semiconductor chip 3 by a load and ultrasonic waves, and the other end is similarly connected to the external terminal 17. It is joined. At the time of manufacturing the power semiconductor device 1, the joining process is performed, and then the sealing is performed with the sealing resin 15.

はんだ５，１１には、例えばＳｎＡｇやＳｎＡｇＣｕ等の材質からなるシートはんだが用いられ、半導体チップ３、絶縁回路基板７及び放熱板９をはんだ５，１１を介して積層し、半導体チップ３の上におもり３２（図６参照）を載せ、リフロー炉３３（図７参照）で加熱することで、半導体チップ３、絶縁回路基板７及び放熱板９が接合される。
ところで、はんだ５，１１の厚さを厚くするとはんだ５，１１の歪みが小さくなり耐久信頼性が向上するが、はんだ５，１１が厚すぎるとはんだ５，１１での熱抵抗が増加し放熱性が低下してしまう。したがって、はんだ５，１１の厚さ（高さ）は、耐久信頼性を得るための下限値から放熱性能を満足する上限値までの範囲で管理する必要がある。 For the solders 5 and 11, for example, a sheet solder made of a material such as SnAg or SnAgCu is used, and the semiconductor chip 3, the insulating circuit substrate 7 and the heat sink 9 are stacked via the solders 5 and 11. The semiconductor chip 3, the insulating circuit board 7, and the heat sink 9 are joined by placing the weight 32 (see FIG. 6) and heating it in the reflow furnace 33 (see FIG. 7).
By the way, if the thickness of the solders 5 and 11 is increased, the distortion of the solders 5 and 11 is reduced and the durability reliability is improved. However, if the solders 5 and 11 are too thick, the thermal resistance at the solders 5 and 11 is increased and the heat dissipation is increased. Will fall. Therefore, it is necessary to manage the thickness (height) of the solders 5 and 11 within a range from a lower limit value for obtaining durability reliability to an upper limit value satisfying the heat dissipation performance.

そこで、本実施の形態では、半導体チップ３と絶縁回路基板７との間、及び、絶縁回路基板７と放熱板９との間には、それぞれはんだ５，１１の厚さ（高さ）を制御するためのスペーサ２１，２２が設けられている。スペーサ２１，２２には、例えば半硬化状態の樹脂シートが使用される。ここで、半硬化状態とは、熱硬化性樹脂の硬化の中間状態であって、図２に示すように、室温では流動性を持たず固形状で熱可塑樹脂のような挙動を示し、加熱すると軟化しその後硬化する、いわゆるＢステージと称される状態を言う。
スペーサ２１，２２に、例えば液状のエポキシ樹脂を用いた場合には、加熱後の高さのばらつきが大きいが、樹脂シートを用いた場合には、加熱後の高さのばらつきを５％以内に抑えることができる。 Therefore, in the present embodiment, the thicknesses (heights) of the solders 5 and 11 are controlled between the semiconductor chip 3 and the insulating circuit board 7 and between the insulating circuit board 7 and the heat sink 9, respectively. Spacers 21 and 22 are provided. For the spacers 21 and 22, for example, a semi-cured resin sheet is used. Here, the semi-cured state is an intermediate state of the curing of the thermosetting resin, and as shown in FIG. 2, it does not have fluidity at room temperature and exhibits a behavior like a solid thermoplastic resin. Then, a state called a so-called B-stage that softens and then hardens is said.
For example, when a liquid epoxy resin is used for the spacers 21 and 22, the variation in height after heating is large. However, when a resin sheet is used, the variation in height after heating is within 5%. Can be suppressed.

また、樹脂シートは、図３に示すように、加熱温度により溶融して液状化したときの粘性が異なる。図３中、Ｖ１は１２０℃で、Ｖ２は１００℃で、Ｖ３は８０℃で加熱した場合の樹脂シートの粘度である。したがって、加熱温度を制御することにより、樹脂シートの形状制御が可能となる。
スペーサ２１，２２の材質としては、例えば、ポリイミド・ポリアミド・シリコーン系ポリイミド、エポキシ系ポリイミド等の絶縁性樹脂が挙げられる。本実施の形態では、耐熱性及び柔軟性の両方の性質を備えて耐久性を高くするため、耐熱性が高い（２００℃以上である）ポリイミドと柔軟性の高いシリコーンを付加したシリコーン系ポリイミドが用いられている。 Further, as shown in FIG. 3, the resin sheet has different viscosities when melted and liquefied by the heating temperature. In FIG. 3, V1 is 120 ° C., V2 is 100 ° C., and V3 is the viscosity of the resin sheet when heated at 80 ° C. Therefore, the shape of the resin sheet can be controlled by controlling the heating temperature.
Examples of the material of the spacers 21 and 22 include insulating resins such as polyimide, polyamide, silicone-based polyimide, and epoxy-based polyimide. In the present embodiment, in order to increase durability with both heat resistance and flexibility, there is a silicone-based polyimide to which polyimide having high heat resistance (200 ° C. or higher) and silicone having high flexibility are added. It is used.

はんだ５，１１の角部で亀裂や剥離が生じやすいため、スペーサ２１，２２は、当該スペーサ２１，２２の上部部品（例えば、半導体チップ３又は絶縁回路基板７）の四隅の角部に点あるいは線接触する位置に配置される。例えば、スペーサ２２を例に説明すると、図４（Ａ）に示すように、絶縁回路基板７の全周に亘って略長方形のスペーサ２２Ａを設けてもよいし、図４（Ｂ）に示すように、絶縁回路基板７の四隅に略Ｌ字状のスペーサ２２Ｂを設けてもよいし、図４（Ｃ）に示すように、絶縁回路基板７の四隅に略円形のスペーサ２２Ｃを設けてもよいし、図４（Ｄ）に示すように、絶縁回路基板７の四隅に略楕円形のスペーサ２２Ｄを設けてもよい。
例えば、はんだ５，１１の外周部への広がりをより阻止したい場合は、略長方形のスペーサ２２Ａを設けるのがよい。リフロー時に真空効果を大きく得たい場合は、略Ｌ字状のスペーサ２２Ｂを設けるのが望ましい。 Since cracks and peeling easily occur at the corners of the solders 5 and 11, the spacers 21 and 22 have dots or corners at the four corners of the upper part of the spacers 21 and 22 (for example, the semiconductor chip 3 or the insulating circuit board 7). It is arranged at the position where line contact occurs. For example, the spacer 22 will be described as an example. As shown in FIG. 4A, a substantially rectangular spacer 22A may be provided over the entire circumference of the insulating circuit board 7, or as shown in FIG. 4B. In addition, substantially L-shaped spacers 22B may be provided at the four corners of the insulated circuit board 7, or substantially circular spacers 22C may be provided at the four corners of the insulated circuit board 7, as shown in FIG. Then, as shown in FIG. 4D, substantially elliptical spacers 22D may be provided at the four corners of the insulating circuit board 7.
For example, when it is desired to further prevent the solders 5 and 11 from spreading to the outer peripheral portion, it is preferable to provide a substantially rectangular spacer 22A. In order to obtain a large vacuum effect during reflow, it is desirable to provide a substantially L-shaped spacer 22B.

スペーサ２１，２２の高さは、耐久性から求められるはんだ５，１１の最小厚さを下限とし、放熱性から求められるはんだ５，１１の最大厚さを上限とし、はんだ５，１１の厚さ設計値よりも低く設定される。また、スペーサ２１，２２が高すぎると、おもり３２の加重効果が得られず、はんだ５，１１の濡れ広がりが不足し、はんだ５，１１と部品（半導体チップ３、絶縁回路基板７、放熱板９）との接触面積が狭くなり、放熱性が低下するおそれがある。したがって、スペーサ２１，２２の高さは、例えば、はんだ５，１１の厚さ設計値に対して５〜１０％低い高さに設定されるのが望ましく、はんだ５，１１の厚さ設計値に対して５％低い高さに設定されるのが最適である。   The height of the spacers 21 and 22 is set such that the minimum thickness of the solders 5 and 11 required from the durability is the lower limit, and the maximum thickness of the solders 5 and 11 required from the heat dissipation is the upper limit. It is set lower than the design value. On the other hand, if the spacers 21 and 22 are too high, the weighting effect of the weight 32 cannot be obtained, the wetting and spreading of the solders 5 and 11 will be insufficient, and the solders 5 and 11 and the components (semiconductor chip 3, insulating circuit board 7, heat sink) 9) The contact area with 9) becomes narrow, and there is a possibility that the heat dissipation is reduced. Therefore, the height of the spacers 21 and 22 is desirably set to a height that is 5 to 10% lower than the thickness design value of the solders 5 and 11, for example. It is optimal to set the height 5% lower.

スペーサ２１，２２は、積層時に、はんだ５，１１との間に所定の隙間δ１，δ２（図６参照）を有するように配置される。はんだ５，１１とスペーサ２１，２２の隙間δ１，δ２は、１）信頼性が確保できる最適なはんだ５，１１のフィレット形成、２）はんだ５，１１の濡れ広がり性、３）はんだ５，１１やスペーサ２１，２２の位置決め精度、４）各部品の寸法公差等を考慮して最適値に設定される。   The spacers 21 and 22 are arranged so as to have predetermined gaps δ1 and δ2 (see FIG. 6) between the solders 5 and 11 at the time of lamination. The gaps δ1 and δ2 between the solders 5 and 11 and the spacers 21 and 22 are 1) optimal fillet formation of the solder 5 and 11 that can ensure reliability, 2) wettability of the solders 5 and 11, and 3) solders 5 and 11 And positioning accuracy of the spacers 21 and 22, and 4) an optimum value is set in consideration of a dimensional tolerance of each part.

図５は、スペーサとはんだとの間の隙間とスペーサに対するはんだの厚さ率との関係を示すグラフである。ここでは、スペーサ２２とはんだ１１との間の隙間δ２とスペーサ２２に対するはんだ１１の厚さ率を例に説明する。図中、Ａ１〜Ａ４は実測データ、ＢはＡの近似線である。
厚さ率は、凝固後に最適なはんだ厚さを得るために設定される値である。溶融時に周囲に流れるはんだがあるため、溶融・凝固後のはんだの厚さは溶融前と比較して小さくなる。そのため、所望のはんだ厚さに対して、溶融時に周囲に流れ出すはんだ分量を考慮した、凝固後に減少するはんだ厚さをはんだ厚さ率とする。
図５に示すように、厚さ率が高くなるほど、スペーサ２２とはんだ１１との間の隙間δ２は距離が長くなるように設定される。スペーサ２１とはんだ５との間の隙間δ１も同様である。 FIG. 5 is a graph showing the relationship between the gap between the spacer and the solder and the thickness ratio of the solder with respect to the spacer. Here, the gap δ2 between the spacer 22 and the solder 11 and the thickness ratio of the solder 11 with respect to the spacer 22 will be described as an example. In the figure, A1 to A4 are actually measured data, and B is an approximate line of A.
The thickness ratio is a value set to obtain an optimal solder thickness after solidification. Since there is solder flowing around when melting, the thickness of the solder after melting and solidification is smaller than before melting. Therefore, the solder thickness that decreases after solidification in consideration of the amount of solder that flows out to the surroundings during melting with respect to the desired solder thickness is defined as the solder thickness ratio.
As shown in FIG. 5, the gap δ <b> 2 between the spacer 22 and the solder 11 is set to be longer as the thickness ratio is higher. The same applies to the gap δ1 between the spacer 21 and the solder 5.

以下、パワー半導体装置１の製造方法について説明する。
図６は、パワー半導体装置１の製造方法における積層工程を示す説明図である。
まず、下治具３１に放熱板９を配置し、放熱板９の上には、はんだ１１を配置するとともに、はんだ１１の外周部に、スペーサ２２を配置する。次いで、はんだ１１の上に絶縁回路基板７を配置し、この絶縁回路基板７の上には、はんだ５を配置するとともに、はんだ５の外周部に、スペーサ２１を配置する。スペーサ２１ははんだ５との間に所定の隙間δ１を空けて配置され、スペーサ２２ははんだ１１との間に所定の隙間δ２を空けて配置される。 Hereinafter, a method for manufacturing the power semiconductor device 1 will be described.
FIG. 6 is an explanatory diagram showing a stacking process in the method for manufacturing the power semiconductor device 1.
First, the heat radiating plate 9 is disposed on the lower jig 31, the solder 11 is disposed on the heat radiating plate 9, and the spacer 22 is disposed on the outer periphery of the solder 11. Next, the insulating circuit board 7 is disposed on the solder 11, the solder 5 is disposed on the insulating circuit board 7, and the spacer 21 is disposed on the outer periphery of the solder 5. The spacer 21 is arranged with a predetermined gap δ1 between the solder 5 and the spacer 22 is arranged with a predetermined gap δ2 with the solder 11.

これらのスペーサ２１，２２は、例えばカメラによる画像認識や治具等により位置を確認して設置される。スペーサ２１，２２の設置後は、適宜加圧してもよい。
次に、はんだ５の上に半導体チップ３を配置し、半導体チップ３の上におもり３２を配置する。以下、はんだ５，１１を介して積層された半導体５、絶縁回路基板７及び放熱板９を積層体と呼ぶものとする。 These spacers 21 and 22 are installed by confirming their positions by, for example, image recognition by a camera or a jig. You may pressurize suitably after installation of spacers 21 and 22.
Next, the semiconductor chip 3 is disposed on the solder 5, and the weight 32 is disposed on the semiconductor chip 3. Hereinafter, the semiconductor 5, the insulating circuit board 7, and the heat sink 9 that are stacked via the solders 5 and 11 are referred to as a stacked body.

図７はパワー半導体装置１の製造方法におけるリフロー行程を示す説明図である。また、図８ははんだ５，１１及びスペーサ２１，２２の溶融状態を示すグラフであり、図９ははんだ５，１１及びスペーサ２１，２２の溶融状態を示す説明図である。図１０は、リフロー加熱後の積層体を示す図である。
次いで、おもり３２を載せた積層体を、図７に示すように、水素（Ｈ2）及び窒素（Ｎ2）が充満するリフロー炉３３に入れて例えば２６０℃に加熱し、所定時間後に冷却する。このとき、スペーサ２１，２２は、図８に示すように、加熱に伴い粘度が低下し、その後熱硬化し、冷却に伴い凝固する。一方、はんだ５，１１は、加熱後しばらくしてから粘度が低下し、冷却に伴い凝固する。図８に示す点Ｐ１，Ｐ２，Ｐ３におけるはんだ１１及びスペーサ２２の状態をそれぞれ図９（Ａ）、図９（Ｂ）、及び図９（Ｃ）に示す。 FIG. 7 is an explanatory diagram showing a reflow process in the method for manufacturing the power semiconductor device 1. FIG. 8 is a graph showing the melting state of the solders 5 and 11 and the spacers 21 and 22, and FIG. 9 is an explanatory diagram showing the melting state of the solders 5 and 11 and the spacers 21 and 22. FIG. 10 is a diagram showing the laminate after reflow heating.
Next, as shown in FIG. 7, the laminate on which the weight 32 is placed is placed in a reflow furnace 33 filled with hydrogen (H 2 ) and nitrogen (N 2 ), heated to, for example, 260 ° C., and cooled after a predetermined time. . At this time, as shown in FIG. 8, the spacers 21 and 22 have a viscosity that decreases with heating, and then thermoset and solidify with cooling. On the other hand, the solders 5 and 11 are reduced in viscosity after a while after being heated, and solidify with cooling. The states of the solder 11 and the spacer 22 at the points P1, P2, and P3 shown in FIG. 8 are shown in FIGS. 9A, 9B, and 9C, respectively.

まず、加熱前には、図９（Ａ）に示すように、はんだ１１とスペーサ２２は、隙間δ２を空けて配置されている。加熱されると、図９（Ｂ）に示すように、スペーサ２２は、加熱によって軟化（溶融）して流動する一方で、常温で半硬化状態であるため、加熱時の軟化による粘度低下が比較的少なく、適度に形状が維持され、高さが維持される。また、はんだ１１は、加熱されると溶融して山状のフィレットを形成する。   First, before heating, as shown in FIG. 9A, the solder 11 and the spacer 22 are arranged with a gap δ2. When heated, as shown in FIG. 9B, the spacer 22 is softened (melted) by heating and flows while being in a semi-cured state at room temperature. Therefore, the shape is maintained moderately and the height is maintained. Further, when heated, the solder 11 melts to form a mountain-shaped fillet.

ここで、図８の点Ｐ２で示すように、はんだ１１及びスペーサ２２は溶融して流動性が増大した状態で共存するので、スペーサ２２は、図９（Ｂ）に示すように、はんだ１１のフィレットに倣って形状が変化してはんだ１１に密着し、はんだ１１と上下の部品（ここでは、絶縁回路基板７及び放熱板９）との間の隙間にも入り込む。
はんだ１１及びスペーサ２２は、冷却の開始に伴い同時に凝固を開始し、図９（Ｃ）に示すように、はんだ１１によって上下の部品（絶縁回路基板７及び放熱板９）が接合される。 Here, as shown by a point P2 in FIG. 8, since the solder 11 and the spacer 22 coexist in a state of being melted and having increased fluidity, the spacer 22 is formed of the solder 11 as shown in FIG. The shape changes following the fillet and comes into close contact with the solder 11, and also enters the gap between the solder 11 and the upper and lower components (here, the insulating circuit board 7 and the heat sink 9).
The solder 11 and the spacer 22 start to solidify simultaneously with the start of cooling, and the upper and lower parts (the insulating circuit board 7 and the heat sink 9) are joined by the solder 11 as shown in FIG. 9C.

はんだ５及びスペーサ２１についても同様に溶融及び凝固し、図１０に示すように、はんだ５，１１によって、半導体チップ３、絶縁回路基板７及び放熱板９が接合されることとなる。
このように、スペーサ２１，２２は、はんだ５，１１に密着するとともに、上下の部品（半導体チップ３及び絶縁回路基板７、あるいは、絶縁回路基板７及び放熱板９）に密着するので、各部品３，５，７，９，１１間の界面の密着性が向上し、パワー半導体装置１の絶縁性を確実に確保できる。しかも、スペーサ２１，２２は、半硬化状態の樹脂シートを用いて形成したため、加熱時に流動性が向上してはんだ５，１１と周辺部品３，７，９との間の隙間にも入り込み、各部品３，５，７，９，１１間の界面の密着性をより向上させることができ、パワー半導体装置１の絶縁性をより確実に確保できる。その結果、信頼性の高いパワー半導体装置１を提供できる。 The solder 5 and the spacer 21 are similarly melted and solidified, and as shown in FIG. 10, the semiconductor chip 3, the insulating circuit substrate 7, and the heat sink 9 are joined by the solders 5 and 11.
Thus, the spacers 21 and 22 are in close contact with the solders 5 and 11 and are in close contact with the upper and lower components (the semiconductor chip 3 and the insulating circuit substrate 7 or the insulating circuit substrate 7 and the heat sink 9). The adhesion of the interface between 3, 5, 7, 9, and 11 is improved, and the insulation of the power semiconductor device 1 can be ensured reliably. Moreover, since the spacers 21 and 22 are formed using a semi-cured resin sheet, the fluidity is improved during heating, and the spacers 21 and 22 enter the gaps between the solders 5 and 11 and the peripheral components 3, 7, and 9. The adhesion of the interface between the components 3, 5, 7, 9, and 11 can be further improved, and the insulation of the power semiconductor device 1 can be more reliably ensured. As a result, a highly reliable power semiconductor device 1 can be provided.

図１１は、パワー半導体装置１の製造方法におけるケース接着行程を示す説明図である。
次いで、積層体に樹脂ケース１３を接着し、樹脂ケース１３に設けられた外部端子１７と半導体チップ３とをアルミワイヤ１９により接続する。最後に、図１に示すように、樹脂ケース１３内に封止樹脂１５を注入すると、積層体が封止樹脂１５により封止される。このとき、スペーサ２１，２２は、はんだ５，１１と密接しているため、封止樹脂１５の流動を阻害することがなく、封止樹脂１５が周辺部品３，５，７，９，１１に密着する。 FIG. 11 is an explanatory diagram showing a case bonding process in the method for manufacturing the power semiconductor device 1.
Next, the resin case 13 is bonded to the laminate, and the external terminals 17 provided on the resin case 13 and the semiconductor chip 3 are connected by the aluminum wire 19. Finally, as shown in FIG. 1, when the sealing resin 15 is injected into the resin case 13, the laminate is sealed with the sealing resin 15. At this time, since the spacers 21 and 22 are in close contact with the solders 5 and 11, the sealing resin 15 does not hinder the flow of the sealing resin 15, and the sealing resin 15 is attached to the peripheral parts 3, 5, 7, 9, and 11. In close contact.

また、スペーサ２１，２２は、半導体チップ３と封止樹脂１５との間、及び、絶縁回路基板７と封止樹脂１５との間に介在することとなる。ここで、スペーサ２１，２２に含まれるポリイミド系の材料は、熱膨張係数が６×１０-5／℃であり、周囲の封止樹脂１５（シリコーン樹脂：３×１０-4／℃）より熱膨張係数が小さく、半導体チップ３や絶縁回路基板７の熱膨張係数（２×１０-6／℃）より熱膨張係数が大きい。すなわち、半導体チップ３又は絶縁回路基板７と封止樹脂１５との間に、膨張係数が中間であるスペーサ２１，２２が介在することとなり、その結果、半導体チップ３又は絶縁回路基板７と封止樹脂１５との間の応力を緩和し、はんだ５，１１の剥離や亀裂の発生を抑制できる。 The spacers 21 and 22 are interposed between the semiconductor chip 3 and the sealing resin 15 and between the insulating circuit substrate 7 and the sealing resin 15. Here, the polyimide-based material included in the spacers 21 and 22 has a thermal expansion coefficient of 6 × 10 −5 / ° C. and is more heated than the surrounding sealing resin 15 (silicone resin: 3 × 10 −4 / ° C.). The coefficient of expansion is small, and the coefficient of thermal expansion is larger than the coefficient of thermal expansion (2 × 10 −6 / ° C.) of the semiconductor chip 3 and the insulating circuit board 7. That is, the spacers 21 and 22 having an intermediate expansion coefficient are interposed between the semiconductor chip 3 or the insulating circuit substrate 7 and the sealing resin 15, and as a result, the semiconductor chip 3 or the insulating circuit substrate 7 and the sealing resin 15 are sealed. The stress between the resin 15 and the resin 15 can be relieved, and the occurrence of peeling and cracking of the solders 5 and 11 can be suppressed.

また、スペーサ２１，２２の絶縁破壊電圧は８ｋｖ／ｍｍ以上であり、封止樹脂１５と同等の電気絶縁特性を有することから、リフロー後もスペーサ２１，２２を取り外すことなく、スペーサ２１，２２をそのまま封止剤の一部として利用できる。例えばスペーサ２１，２２を設けない場合には、はんだ５，１１の外周にはんだ５，１１の溶融範囲を決める位置決め治具を設け、リフロー後にはこの位置決め治具を取り外す必要があったが、本実施の形態では、スペーサ２１，２２を取り外す工程を省略でき、工数を削減できるので、製造コストを低減できる。   In addition, since the dielectric breakdown voltage of the spacers 21 and 22 is 8 kv / mm or more and has the same electrical insulation characteristics as the sealing resin 15, the spacers 21 and 22 can be removed without removing the spacers 21 and 22 even after reflow. It can be used as it is as a part of the sealant. For example, when the spacers 21 and 22 are not provided, a positioning jig for determining the melting range of the solders 5 and 11 is provided on the outer periphery of the solders 5 and 11, and it is necessary to remove the positioning jigs after reflow. In the embodiment, the process of removing the spacers 21 and 22 can be omitted, and the number of steps can be reduced, so that the manufacturing cost can be reduced.

以上説明したように、本実施の形態によれば、はんだ５，１１の外周部に、絶縁性樹脂からなり、リフロー加熱時に溶融してはんだ５，１１と密接するスペーサ２１，２２を配置し、リフロー加熱後に半導体チップ３及び絶縁回路基板７を樹脂封止する構成とした。この構成により、スペーサ２１，２２によってはんだ５，１１の厚さを制御できる。また、スペーサ２１，２２がはんだ５，１１と密接するため、スペーサ２１，２２が封止樹脂１５の流動を阻害することがなく、封止樹脂１５と周辺部品３，５，７，９，１１との密着性を図ることができ、その結果、パワー半導体装置１の絶縁性を確保できる。また、線膨張係数が異なる半導体チップ３及び絶縁回路基板７と封止樹脂１５との間に線膨張係数が中間の絶縁性樹脂からなるスペーサ２１，２２が位置することとなるため、各部品３，５，７，９，１１間の界面での応力を緩和し、はんだ５，１１の亀裂や剥離を抑制できる。   As described above, according to the present embodiment, the spacers 21 and 22 made of an insulating resin and melted during reflow heating and in close contact with the solders 5 and 11 are arranged on the outer periphery of the solders 5 and 11. The semiconductor chip 3 and the insulating circuit board 7 were sealed with resin after reflow heating. With this configuration, the thickness of the solders 5 and 11 can be controlled by the spacers 21 and 22. Further, since the spacers 21 and 22 are in close contact with the solders 5 and 11, the spacers 21 and 22 do not hinder the flow of the sealing resin 15, and the sealing resin 15 and the peripheral parts 3, 5, 7, 9, 11. As a result, the insulating property of the power semiconductor device 1 can be ensured. In addition, since the spacers 21 and 22 made of an insulating resin having an intermediate linear expansion coefficient are positioned between the semiconductor chip 3 and the insulating circuit substrate 7 having different linear expansion coefficients and the sealing resin 15, each component 3 , 5, 7, 9 and 11 can be relaxed, and cracks and peeling of the solders 5 and 11 can be suppressed.

また、本実施の形態によれば、スペーサ２１，２２に半硬化状態の樹脂シートを使用する構成とした。スペーサ２１，２２が半硬化状態であるため、加熱時に流動性が向上してはんだ５，１１と周辺部品３，７，９との間の隙間にも入り込み、各部品３，５，７，９，１１間の界面の密着性を向上させることができ、パワー半導体装置１の絶縁性をより確実に確保できる。またスペーサ２１，２２が半硬化状態であるため、加熱時の軟化による粘度低下が比較的少なく、スペーサ２１，２２としての高さを維持できる。   Moreover, according to this Embodiment, it was set as the structure which uses the resin sheet of a semi-hardened state for the spacers 21 and 22. FIG. Since the spacers 21 and 22 are in a semi-cured state, the fluidity is improved during heating, and the spacers 21 and 22 enter into the gaps between the solders 5 and 11 and the peripheral parts 3, 7, and 9. , 11 can be improved, and the insulation of the power semiconductor device 1 can be ensured more reliably. In addition, since the spacers 21 and 22 are in a semi-cured state, a decrease in viscosity due to softening during heating is relatively small, and the height of the spacers 21 and 22 can be maintained.

また、本実施の形態によれば、スペーサ２１，２２を、角形の半導体チップ３及び絶縁回路基板７の少なくとも角部に４カ所以上点接触あるいは線接触するように設置する構成とした。はんだ５，１１の亀裂や剥離が生じやすい半導体チップ３及び絶縁回路基板７の角部にスペーサ２１，２２を配置したため、はんだ５，１１の亀裂や剥離を確実に抑制できる。   Further, according to the present embodiment, the spacers 21 and 22 are installed so as to be in point contact or line contact with at least four corners of the rectangular semiconductor chip 3 and the insulating circuit substrate 7. Since the spacers 21 and 22 are arranged at the corners of the semiconductor chip 3 and the insulating circuit board 7 where the solders 5 and 11 are likely to crack and peel, the cracks and peeling of the solders 5 and 11 can be reliably suppressed.

なお、本発明は、上記実施形態に限らず、本発明の要旨を逸脱することなく、種々の構成を採り得ることは勿論である。   Note that the present invention is not limited to the above-described embodiment, and various configurations can be adopted without departing from the gist of the present invention.

１ パワー半導体装置（電子装置）
３ 半導体チップ（電子部品）
５，１１ はんだ
７ 絶縁回路基板（電子部品）
９ 放熱板（金属板）
１５ 封止樹脂
２１，２２ スペーサ 1 Power semiconductor devices (electronic devices)
3 Semiconductor chip (electronic component)
5,11 Solder 7 Insulated circuit board (electronic component)
9 Heat sink (metal plate)
15 Sealing resin 21, 22 Spacer

Claims (4)

金属板上にはんだを介して電子部品を配置し、前記はんだをリフロー加熱してはんだ付けする電子装置の製造方法において、
前記はんだの外周部に、絶縁性樹脂からなり、前記リフロー加熱時に溶融して前記はんだと密接するスペーサを配置し、
前記リフロー加熱後に前記電子部品を樹脂封止することを特徴とする電子装置の製造方法。 In the method of manufacturing an electronic device in which an electronic component is placed on a metal plate via solder and the solder is soldered by reflow heating,
An outer peripheral portion of the solder is made of an insulating resin, and a spacer that is melted during the reflow heating and is in close contact with the solder is disposed,
A method of manufacturing an electronic device, wherein the electronic component is resin-sealed after the reflow heating. 前記スペーサに半硬化状態の樹脂シートを使用したことを特徴とする請求項１に記載の電子装置の製造方法。   The method of manufacturing an electronic device according to claim 1, wherein a semi-cured resin sheet is used for the spacer. 前記スペーサを、角形の前記電子部品の少なくとも角部に４カ所以上点接触あるいは線接触するように設置したことを特徴とする請求項１又は２に記載の電子装置の製造方法。   3. The method of manufacturing an electronic device according to claim 1, wherein the spacer is disposed so as to be in point contact or line contact with at least four places on at least a corner of the rectangular electronic component. 金属板上にはんだを介して電子部品を配置し、前記はんだをリフロー加熱してはんだ付けする電子装置において、
前記はんだの外周部に、絶縁性樹脂からなり、前記リフロー加熱時に溶融して前記はんだと密接するスペーサを配置し、
前記リフロー加熱後に前記電子部品を樹脂封止することを特徴とする電子装置。 In an electronic device in which an electronic component is placed on a metal plate via solder and the solder is soldered by reflow heating,
An outer peripheral portion of the solder is made of an insulating resin, and a spacer that is melted during the reflow heating and is in close contact with the solder is disposed,
An electronic apparatus, wherein the electronic component is resin-sealed after the reflow heating.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015076511A (en) * 2013-10-09 2015-04-20 株式会社日立製作所 Semiconductor device and manufacturing method of the same
JP2017005071A (en) * 2015-06-09 2017-01-05 カルソニックカンセイ株式会社 Joint structure

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JP2006032617A (en) * 2004-07-15 2006-02-02 Hitachi Ltd Semiconductor power module
JP2006278598A (en) * 2005-03-29 2006-10-12 Mitsubishi Electric Corp Semiconductor device

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Publication number Priority date Publication date Assignee Title
JP2006032617A (en) * 2004-07-15 2006-02-02 Hitachi Ltd Semiconductor power module
JP2006278598A (en) * 2005-03-29 2006-10-12 Mitsubishi Electric Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015076511A (en) * 2013-10-09 2015-04-20 株式会社日立製作所 Semiconductor device and manufacturing method of the same
JP2017005071A (en) * 2015-06-09 2017-01-05 カルソニックカンセイ株式会社 Joint structure

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