JP2008027935A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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JP2008027935A
JP2008027935A JP2006195064A JP2006195064A JP2008027935A JP 2008027935 A JP2008027935 A JP 2008027935A JP 2006195064 A JP2006195064 A JP 2006195064A JP 2006195064 A JP2006195064 A JP 2006195064A JP 2008027935 A JP2008027935 A JP 2008027935A
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semiconductor chip
insulating substrate
chip
metal wiring
solder
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JP2008027935A5 (en
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Koji Sasaki
康二 佐々木
Akihiro Tanba
昭浩 丹波
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve a matter that an Si chip must be mounted as close as possible to the heat dissipating portion in order to enhance heat dissipation properties of a semiconductor module and an insulator is required between the Si chip and the heat dissipating portion in order to insure high breakdown voltage, but when solder is employed for bonding them, thermal fatigue of solder due to temperature variation during use must be prevented. <P>SOLUTION: Warpage of a semiconductor module due to contraction of resin or the coefficient of thermal expansion can be lessened by mounting an insulating substrate mounting an electric circuit such as an Si chip on two or more sides of a heat dissipation plate and then molding the entirely of hard resin. Furthermore, heat dissipation properties can be enhanced by providing a channel of cooling liquid in the heat dissipation plate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本特許は、半導体装置、特にモータ等の制御に用いられるパワー半導体装置に関する。   This patent relates to a semiconductor device, in particular, a power semiconductor device used for controlling a motor or the like.

パワー半導体装置は、モータなどの電気機器を制御するために用いられる半導体装置である。ハイブリッド自動車や燃料電池の市場の伸長により、パワー半導体装置の需要も伸長している。また、要求される通電電流や環境温度などのスペックも厳しくなりつつある。このような使用条件下でパワー半導体装置の信頼性が損なわれないことが重要である。特に、Ｓｉ（シリコン）チップの放熱性の確保が重要である。   The power semiconductor device is a semiconductor device used for controlling an electric device such as a motor. The demand for power semiconductor devices is growing due to the growth of the market for hybrid vehicles and fuel cells. In addition, specifications such as required energization current and environmental temperature are becoming stricter. It is important that the reliability of the power semiconductor device is not impaired under such use conditions. In particular, it is important to ensure heat dissipation of the Si (silicon) chip.

このため、例えば特許文献１に示すような、Ｓｉチップを放熱器に直付けし、放熱器の内部に冷却液を充填して、沸騰冷却によりＳｉチップを冷却することにより、Ｓｉチップの放熱性を向上したパワー半導体装置が提案されている。   For this reason, for example, as shown in Patent Document 1, a Si chip is directly attached to a radiator, a cooling liquid is filled in the radiator, and the Si chip is cooled by boiling cooling. There has been proposed a power semiconductor device with improved characteristics.

特開平８−２９４２６６号公報JP-A-8-294266

パワー半導体装置のＳｉチップには高電圧が付与されるため、Ｓｉチップ−放熱器間の絶縁を充分に確保しなければ、使用時に絶縁破壊が起きる恐れがあり大変危険である。このため、パワーモジュールの実装では、Ｓｉチップと放熱器の間に、金属回路層を表裏面に備えたセラミック絶縁基板や、樹脂の絶縁シートを介して表面に金属回路層を備えた金属絶縁基板などを使用することが多い。Ｓｉチップとセラミック絶縁基板間やＳｉチップと金属絶縁基板間の接合は、はんだを使用することが一般的である。しかし、Ｓｉチップには大電流が通電されるため、半導体装置の稼動時にはジュール発熱によりＳｉチップ温度が上昇する。Ｓｉチップの非通電時にはＳｉチップ温度が低下するため、繰返し使用によって半導体装置の温度は上昇と冷却を繰返し、全体が熱膨張と冷却収縮を繰返す。パワー半導体装置の部材のうち、Ｓｉチップの線膨張係数は３×１０-6／℃程度であり、一方、Ｓｉチップと接続される部材の材料として用いられるＣｕ（銅）の線膨張係数は１７×１０-6／℃、Ａｌ（アルミニウム）の線膨張係数は２４×１０-6／℃程度であるから、これらの部材を接合するはんだには、線膨張係数のミスマッチによるせん断変形が生じ、これが繰返されることによって疲労破壊する。パワー半導体装置の信頼性確保のためには、はんだの疲労破壊を防止することが重要である。 Since a high voltage is applied to the Si chip of the power semiconductor device, unless sufficient insulation between the Si chip and the heatsink is secured, dielectric breakdown may occur during use, which is extremely dangerous. For this reason, when mounting a power module, a ceramic insulating substrate having a metal circuit layer on the front and back surfaces between the Si chip and the radiator, or a metal insulating substrate having a metal circuit layer on the surface through a resin insulating sheet Etc. are often used. Generally, solder is used for bonding between the Si chip and the ceramic insulating substrate or between the Si chip and the metal insulating substrate. However, since a large current is passed through the Si chip, the temperature of the Si chip rises due to Joule heat generation during operation of the semiconductor device. Since the temperature of the Si chip decreases when the Si chip is not energized, the temperature of the semiconductor device repeatedly rises and cools by repeated use, and the whole repeats thermal expansion and cooling contraction. Of the members of the power semiconductor device, the linear expansion coefficient of the Si chip is about 3 × 10 −6 / ° C., while the linear expansion coefficient of Cu (copper) used as the material of the member connected to the Si chip is 17 Since the linear expansion coefficient of Al × 10 −6 / ° C. and Al (aluminum) is about 24 × 10 −6 / ° C., the solder joining these members undergoes shear deformation due to mismatch of the linear expansion coefficient. Fatigue failure by repeated. In order to ensure the reliability of the power semiconductor device, it is important to prevent fatigue breakdown of the solder.

はんだの疲労破壊を防止し、熱疲労寿命を延ばすためには、はんだの周辺を硬質レジンで封止することが有効である。しかし、樹脂と基板やベースの線膨張係数差や、樹脂の硬化収縮により、半導体装置にそりが生じ、基板が破損する恐れがある。樹脂の線膨張係数を基板やベースの線膨張係数に近づけておくことでそりの低減は可能であるが、樹脂の硬化収縮のため、そりを完全に除去することはできない。   In order to prevent solder fatigue failure and extend the thermal fatigue life, it is effective to seal the periphery of the solder with a hard resin. However, there is a risk that the semiconductor device is warped due to a difference in linear expansion coefficient between the resin and the substrate or the base, or due to curing shrinkage of the resin, and the substrate is damaged. Although the warpage can be reduced by keeping the linear expansion coefficient of the resin close to the linear expansion coefficient of the substrate or the base, the warpage cannot be completely removed due to curing shrinkage of the resin.

本発明は前記のような問題点を解決するためになされたものであり、その目的は、パワー半導体装置において、使用時の熱サイクルによる疲労断線が起こりにくく、かつ、放熱性が良く、反り変形量が小さく、低コストで信頼性の高い半導体装置を提供することである。   The present invention has been made in order to solve the above-described problems. The purpose of the power semiconductor device is to prevent fatigue disconnection due to a thermal cycle during use and to have good heat dissipation and warp deformation. The object is to provide a semiconductor device with a small amount, low cost and high reliability.

本発明は、前記目的を達成するために、Ｓｉチップを搭載したセラミック基板あるいは金属絶縁基板を放熱部の両面に接合し、放熱部の内部には冷却液の流路を形成し、基板上のはんだ接合部を封止するエポキシ樹脂などのハードレジンによって放熱板の両側が封止されたパワー半導体装置を構成する。   In order to achieve the above-mentioned object, the present invention joins a ceramic substrate or a metal insulating substrate on which a Si chip is mounted on both surfaces of a heat radiating portion, and forms a coolant flow path inside the heat radiating portion. A power semiconductor device in which both sides of the heat sink are sealed by a hard resin such as an epoxy resin for sealing the solder joint portion is configured.

さらに、本発明は、Ｓｉチップ上にリードフレームをはんだによって接合し、はんだ接続部の一部あるいは全部が硬質のポッティングレジンによって封止されていることを特徴とする。   Furthermore, the present invention is characterized in that a lead frame is joined to a Si chip by solder, and a part or all of the solder connection portion is sealed by a hard potting resin.

本発明によれば、セラミック基板あるいは金属絶縁基板を放熱部の２面以上に接合し、放熱部の内部に冷却液を流すことにより、放熱性の良い半導体装置を提供することができる。また、はんだの一部あるいは全部をハードレジンで封止することにより、使用時の温度サイクルによってはんだの疲労破壊を起こしにくく、かつ、リードフレームの疲労破壊を起こしにくい、信頼性の高い半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor device with good heat dissipation by bonding a ceramic substrate or a metal insulating substrate to two or more surfaces of a heat dissipation portion and flowing a cooling liquid inside the heat dissipation portion. In addition, by sealing part or all of the solder with a hard resin, a highly reliable semiconductor device that does not easily cause fatigue failure of the solder due to the temperature cycle during use and that does not easily cause fatigue failure of the lead frame. Can be provided.

以下本発明の実施例を図面を用いて説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１は本発明の実施例による半導体装置の断面を表す。本実施例では、セラミック基板４の表面に直接Ｃｕのリードフレーム７が設けられ、リードフレーム７の上にチップ下はんだ９を介してＳｉチップ１が接合され、Ｓｉチップ１の上にはアルミワイヤボンディング３が接合される。ワイヤボンディング３はＳｉチップ１とリードフレーム７を電気的に接合している。また、セラミック基板４の裏面にもリードフレーム７が設けられ、リードフレーム７と放熱部となる金属ベース板５は基板下はんだ８を介して接合されている。セラミック基板４がリードフレーム７，基板下はんだ８を介して、金属ベース板５の表裏面に接合されており、全体は上下にほぼ対称な構造となっている。金属ベース板５の一部、冷却液吸入口１０，冷却液吐出口及びリードフレーム７の一部を除くモジュール全体は、トランスファーモールドされたハードレジン２により封止されている。基板下はんだ８，チップ下はんだ９の表面をハードレジンでモールドすることにより、温度変化に伴うはんだの変形を抑制し、はんだの熱疲労寿命を長寿命化することが可能となる。Ｓｉチップ１，セラミック基板４等を金属ベース板５の両面に設けてハードレジン２で覆っているので、金属ベース板５の両面にハードレジン２による応力がかかるので、樹脂の硬化収縮や使用時の温度変化に伴う全体構造のそりや樹脂のはがれや割れを防止することができる。ハードレジン２を含む全体構造が上下対称であれば、そりがより小さくなるので望ましい。   FIG. 1 shows a cross section of a semiconductor device according to an embodiment of the present invention. In the present embodiment, a Cu lead frame 7 is directly provided on the surface of the ceramic substrate 4, and the Si chip 1 is joined to the lead frame 7 via the under-chip solder 9. Bonding 3 is joined. The wire bonding 3 electrically joins the Si chip 1 and the lead frame 7. A lead frame 7 is also provided on the back surface of the ceramic substrate 4, and the lead frame 7 and the metal base plate 5 serving as a heat radiating portion are joined via a solder under substrate 8. The ceramic substrate 4 is joined to the front and back surfaces of the metal base plate 5 via the lead frame 7 and the under-substrate solder 8, and the whole has a substantially symmetrical structure in the vertical direction. The entire module excluding a part of the metal base plate 5, the coolant inlet 10, the coolant outlet, and a part of the lead frame 7 is sealed with a transfer molded hard resin 2. By molding the surfaces of the under-substrate solder 8 and under-chip solder 9 with a hard resin, it is possible to suppress the deformation of the solder accompanying a temperature change and to prolong the thermal fatigue life of the solder. Since the Si chip 1, the ceramic substrate 4, etc. are provided on both surfaces of the metal base plate 5 and covered with the hard resin 2, the stress due to the hard resin 2 is applied to both surfaces of the metal base plate 5. It is possible to prevent warping of the entire structure and peeling or cracking of the resin accompanying temperature changes. If the entire structure including the hard resin 2 is vertically symmetric, it is desirable because warpage becomes smaller.

はんだの変形を抑制するためには、ハードレジンのヤング率は５ＧＰａ以上であり、かつ、ハードレジンの線膨張係数がＳｉチップの線膨張係数である３×１０-6／℃以上、かつ、Ｃｕリードフレームの線膨張係数である１７×１０-6／℃以下であることが望ましい。リードフレームの材質がＡｌである場合は、ハードレジンの線膨張係数は、Ａｌの線膨張係数である２４×１０-6／℃以下であることが望ましい。 In order to suppress the deformation of the solder, the Young's modulus of the hard resin is 5 GPa or more, the linear expansion coefficient of the hard resin is 3 × 10 −6 / ° C. or more, which is the linear expansion coefficient of the Si chip, and Cu It is desirable that the linear expansion coefficient of the lead frame is 17 × 10 −6 / ° C. or less. When the material of the lead frame is Al, the linear expansion coefficient of the hard resin is preferably 24 × 10 −6 / ° C. or less, which is the linear expansion coefficient of Al.

実施例１の半導体装置の製造工程を図５に示す。まず、(５ａ)に示すように、セラミック基板４の両面にリードフレーム７を接合する。接合には銀ロウを用いても良いし、直接接合を用いても良い。次に、(５ａ)に示すように、リードフレーム７にＳｉチップ１を、チップ下はんだ９を用いて接合する。ここでは、チップ下はんだ９は高融点の９５Ｐｂ−５Ｓｎはんだとし、（５ｄ）で実施する基板下はんだ付けに用いるはんだと融点に差をつけている。次に、（５ｃ）に示すように、Ｓｉチップ１にＡｌワイヤボンディング３を接合する。次に、（５ｄ）に示すように、セラミック基板４をＣｕ製の金属ベース板５の上下面に重ねてカーボン治具に配置する。セラミック基板４と金属ベース板５の間にははんだシート２２を配置する。ここでははんだシート２２は全て同一組成のＳｎ（すず）−
Ｐｂ（鉛）共晶はんだである。半導体装置の使用温度が高い場合などはＰｂ含有比率が
９０％以上の高融点はんだを使い、（５ｂ）のはんだ付け工程を省略して、（５ｄ）においてチップ下はんだ付けと基板下はんだ付けを一括して行うことも可能である。このときは（５ｃ）のＡｌワイヤボンディングは（５ｄ）の後に行う。また、Ｐｂの使用を避ける場合にはＳｎ−Ａｇ（銀）−Ｃｕ系等の鉛フリーはんだを使うことも可能である。次に
（５ｄ）に示すように全体を通炉し、全体を加熱することによってはんだを溶融させてリードフレーム７とＣｕ金属ベース板５を接合する。炉の温度は約２３０℃とし、基板下の基板下はんだ８のみ溶融し、チップ下はんだ９は溶融しないようにする。次に（５ｅ）に示すように、全体をトランスファーモールド金型１７に入れ、ハードレジン２によって封止する。（５ｅ）に示すように、トランスファーモールド金型を除去すれば半導体装置が完成する。 The manufacturing process of the semiconductor device of Example 1 is shown in FIG. First, as shown in (5a), the lead frame 7 is joined to both surfaces of the ceramic substrate 4. For joining, silver solder may be used, or direct joining may be used. Next, as shown in (5 a), the Si chip 1 is bonded to the lead frame 7 using the under-chip solder 9. Here, the under-chip solder 9 is a high melting point 95Pb-5Sn solder, and the melting point is different from the solder used for under-substrate soldering performed in (5d). Next, as shown in (5c), an Al wire bonding 3 is bonded to the Si chip 1. Next, as shown in (5d), the ceramic substrate 4 is placed on the upper and lower surfaces of the Cu metal base plate 5 and placed on the carbon jig. A solder sheet 22 is disposed between the ceramic substrate 4 and the metal base plate 5. Here, all the solder sheets 22 have the same composition Sn (tin) −
Pb (lead) eutectic solder. When the operating temperature of the semiconductor device is high, use a high melting point solder having a Pb content ratio of 90% or more, omit the soldering process of (5b), and perform soldering under the chip and soldering under the board in (5d). It is also possible to carry out all at once. At this time, the Al wire bonding in (5c) is performed after (5d). In order to avoid the use of Pb, it is possible to use a lead-free solder such as Sn—Ag (silver) —Cu. Next, as shown in (5d), the whole is passed through and the whole is heated to melt the solder and join the lead frame 7 and the Cu metal base plate 5 together. The temperature of the furnace is set to about 230 ° C., only the under-substrate solder 8 below the substrate is melted, and the under-chip solder 9 is not melted. Next, as shown in (5e), the whole is placed in a transfer mold 17 and sealed with the hard resin 2. As shown in (5e), the semiconductor device is completed by removing the transfer mold.

図２は本発明のほかの実施例による半導体装置の断面を示す。本実施例では、Ｓｉチップ上面にワイヤボンディングではなくＣｕリード１３を、リード下はんだ１４を介して接合している。ここではリード下はんだ１４には高融点の９５Ｐｂ−５Ｓｎはんだを用い、チップ下はんだと一括してリフローによって接合している。また、構造全体はハードレジンによりトランスファーモールドされている。ワイヤボンディングを用いないことによりワイヤボンディング工程を省略でき、製造コストや製造時間の低減が可能となる。ここでも、ハードレジンの線膨張係数は、Ｓｉチップの線膨張係数より大きく、リードフレームの線膨張係数より小さいことが望ましい。   FIG. 2 shows a cross section of a semiconductor device according to another embodiment of the present invention. In this embodiment, the Cu lead 13 is bonded to the upper surface of the Si chip via the solder 14 under the lead instead of wire bonding. Here, high melting point 95Pb-5Sn solder is used for the solder 14 under the lead, and it is joined together with the solder under the chip by reflow. The entire structure is transfer molded by a hard resin. By not using wire bonding, the wire bonding process can be omitted, and manufacturing cost and manufacturing time can be reduced. Here again, it is desirable that the linear expansion coefficient of the hard resin is larger than that of the Si chip and smaller than that of the lead frame.

図３は本発明の他の実施例による半導体装置の断面を示す。Ｓｉチップ上にリードを接合しているところは実施例２と同一であるが、ここでは全体をトランスファーモールドするのではなく、チップ下はんだ及びチップ，リード下はんだを覆うようにポッティングレジン１５によって封止している。トランスファーモールドを用いないことにより、モールド金型を用意する必要が無くなり、製造コスト及び製造時間の低減が可能となる。また、樹脂封止の部分が少ないことにより、樹脂収縮や使用時の温度変化による樹脂の影響が小さくなり、パワー半導体装置全体のそりが小さくなる。ここでも、ハードレジンの線膨張係数は、Ｓｉチップの線膨張係数より大きく、リードフレームの線膨張係数より小さいことが望ましい。   FIG. 3 shows a cross section of a semiconductor device according to another embodiment of the present invention. The place where the lead is joined on the Si chip is the same as that of the second embodiment, but here the whole is not transfer-molded but sealed by the potting resin 15 so as to cover the solder under the chip and the solder under the chip and the lead. It has stopped. By not using a transfer mold, it is not necessary to prepare a mold and manufacturing cost and manufacturing time can be reduced. Further, since the resin sealing portion is small, the influence of the resin due to the resin shrinkage and the temperature change at the time of use is reduced, and the warpage of the entire power semiconductor device is reduced. Here again, it is desirable that the linear expansion coefficient of the hard resin is larger than that of the Si chip and smaller than that of the lead frame.

実施例３の半導体装置の製造工程を図６に示す。まず、（６ａ）に示すように、セラミック基板４の上下両面にリードフレーム７を接合する。次に、（６ｂ）に示すように、リードフレーム７にチップ下はんだ９を介してＳｉチップ１を接合し、同時にＳｉチップ１にリード下はんだ１４を介してリード１３を接合する。ここではチップ下はんだ９とリード下はんだ１４は全て同一の組成とし、一括リフローによって接合する。次に（６ｃ）に示すように、チップ下はんだ及びリード下はんだの表面が覆われるように硬質のポッティングレジン１５によって封止する。ここで用いるポッティングレジンは、はんだの熱変形を抑止するためにヤング率が５ＧＰａ以上の硬質のものであることが望ましい。また、線膨張係数はＳｉチップ以上、リードフレーム以下であることが好適である。次に、(６ｄ)に示すように、Ｃｕ金属ベース板５とセラミック基板をはんだ付け治具１６の中に設置する。金属ベース板とセラミック基板の間にははんだシート２２を設置する。ここでははんだシートはＰｂ−Ｓｎ共晶はんだを用いる。次に全体を通炉することで金属ベース板とセラミック基板をはんだ接合する。最後にはんだ付け治具をはずして、半導体装置が完成する。   The manufacturing process of the semiconductor device of Example 3 is shown in FIG. First, as shown in (6a), the lead frames 7 are joined to the upper and lower surfaces of the ceramic substrate 4. Next, as shown in (6 b), the Si chip 1 is joined to the lead frame 7 via the under-chip solder 9, and simultaneously, the lead 13 is joined to the Si chip 1 via the under-lead solder 14. Here, the under-chip solder 9 and the under-lead solder 14 have the same composition, and are joined by batch reflow. Next, as shown in (6c), sealing is performed with a hard potting resin 15 so that the surfaces of the solder under the chip and the solder under the lead are covered. The potting resin used here is desirably a hard one having a Young's modulus of 5 GPa or more in order to suppress thermal deformation of the solder. The linear expansion coefficient is preferably not less than the Si chip and not more than the lead frame. Next, as shown in (6d), the Cu metal base plate 5 and the ceramic substrate are placed in a soldering jig 16. A solder sheet 22 is installed between the metal base plate and the ceramic substrate. Here, a Pb—Sn eutectic solder is used as the solder sheet. Next, the metal base plate and the ceramic substrate are joined by soldering through the furnace. Finally, the soldering jig is removed to complete the semiconductor device.

図４は本発明の他の実施例による半導体装置の断面を示す。ここではセラミック基板の代わりに金属基板１９を用い、この金属基板を、熱伝導シート１８を介してＣｕ金属ベース板に接合している。金属基板１９の表面には、樹脂絶縁層２０を介してリードフレーム７が接合され、リードフレーム７の上にはチップ下はんだ９を介してＳｉチップ１が接合されている。Ｓｉチップ１上面とリードフレーム７上面は、Ａｌワイヤボンディング３によって電気的に結合されている。全体はハードレジン２でモールドされており、ハードレジンの硬化収縮によって発生する残留応力によって金属ベース基板がＣｕ金属ベース板に押し当てられることにより、Ｓｉチップ１で発生させた熱を効率よく金属ベース板に伝えることが可能となる。   FIG. 4 shows a cross section of a semiconductor device according to another embodiment of the present invention. Here, a metal substrate 19 is used instead of the ceramic substrate, and this metal substrate is bonded to a Cu metal base plate via a heat conductive sheet 18. The lead frame 7 is joined to the surface of the metal substrate 19 via a resin insulating layer 20, and the Si chip 1 is joined to the lead frame 7 via a chip solder 9. The upper surface of the Si chip 1 and the upper surface of the lead frame 7 are electrically coupled by Al wire bonding 3. The whole is molded with the hard resin 2, and the metal base substrate is pressed against the Cu metal base plate by the residual stress generated by the hardening shrinkage of the hard resin. It is possible to tell the board.

実施例４の半導体装置の製造工程を図７に示す。まず、（７ａ）に示すように、金属基板１９の上面に樹脂絶縁シート２０を介してリードフレーム７を接合する。ここでは接合には接着剤を用いている。次に、（７ｂ）に示すように、リードフレーム７にＳｉチップ１を、チップ下はんだ９を用いて接合する。ここでは、チップ下はんだ９はＰｂ−Ｓｎ共晶はんだを用いているが、使用温度が高い場合には高融点の９５Ｐｂ−５Ｓｎはんだを用いても良いし、Ｓｎ−Ａｇ−ＣｕなどのＰｂフリーはんだを用いることも可能である。次に、（７ｃ）に示すように、Ｓｉチップ１にＡｌワイヤボンディング３を接合する。次に、（７ｄ）に示すように、金属基板１９をＣｕ製の金属ベース板５の上下面に重ねてモールド金型１７に配置する。金属基板１９と金属ベース板５の間には樹脂製の熱伝導シート１８を配置する。モールド金型の内部にはカーボン製のスペーサ２１を設置し、あらかじめ金属基板１９を金属ベース板５に押し付けておく。この状態でトランスファーモールドにより液状のレジン１２を注入し、加熱硬化させてハードレジン２とする。ここで用いるハードレジン２は、ヤング率が５ＧＰａ以上の硬質樹脂であることが望ましい。ハードレジンの硬化収縮と、硬化後の熱収縮によって金属基板１９が金属ベース板５に押し付けられるため、樹脂製の熱伝導シート１８に対するリードフレーム７，金属ベース板５の密着性が向上し、Ｓｉチップ１で発生した熱を効率的に金属ベース板に逃がすことのできる、放熱性の高い半導体装置を構成することができる。最後に（７ｅ）に示すように、トランスファーモールド金型を除去すれば半導体装置が完成する。   The manufacturing process of the semiconductor device of Example 4 is shown in FIG. First, as shown in (7 a), the lead frame 7 is joined to the upper surface of the metal substrate 19 via the resin insulating sheet 20. Here, an adhesive is used for joining. Next, as shown in (7 b), the Si chip 1 is joined to the lead frame 7 using the under-chip solder 9. Here, Pb—Sn eutectic solder is used for the under-chip solder 9, but when the operating temperature is high, 95 Pb-5 Sn solder having a high melting point may be used, or Pb-free such as Sn—Ag—Cu. It is also possible to use solder. Next, as shown in (7c), an Al wire bonding 3 is bonded to the Si chip 1. Next, as shown in (7d), the metal substrate 19 is placed on the mold die 17 so as to overlap the upper and lower surfaces of the metal base plate 5 made of Cu. A resin heat conduction sheet 18 is disposed between the metal substrate 19 and the metal base plate 5. A carbon spacer 21 is installed inside the mold, and the metal substrate 19 is pressed against the metal base plate 5 in advance. In this state, a liquid resin 12 is injected by a transfer mold and cured by heating to obtain a hard resin 2. The hard resin 2 used here is desirably a hard resin having a Young's modulus of 5 GPa or more. Since the metal substrate 19 is pressed against the metal base plate 5 by the hardening shrinkage of the hard resin and the heat shrinkage after hardening, the adhesion of the lead frame 7 and the metal base plate 5 to the resin thermal conductive sheet 18 is improved. It is possible to configure a semiconductor device with high heat dissipation that can efficiently release the heat generated in the chip 1 to the metal base plate. Finally, as shown in (7e), the semiconductor device is completed by removing the transfer mold.

本発明の一実施形態になる半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which becomes one Embodiment of this invention. 本発明の他の実施形態になる半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which becomes other embodiment of this invention. 本発明の他の実施形態になる半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which becomes other embodiment of this invention. 本発明の他の実施形態になる半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which becomes other embodiment of this invention. 本発明の一実施形態になる半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which becomes one Embodiment of this invention. 本発明の他の実施形態になる半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which becomes other embodiment of this invention. 本発明の他の実施形態になる半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which becomes other embodiment of this invention.

符号の説明Explanation of symbols

１…Ｓｉチップ、２…ハードレジン、３…ワイヤボンディング、４…セラミック基板、５…金属ベース板、６…冷却液、７…リードフレーム、８…基板下はんだ、９…チップ下はんだ、１０…冷却液吸入口、１１…冷却液吐出口、１２…液状レジン、１３…リード、１４…リード下はんだ、１５…ポッティングレジン、１６…はんだ付け治具、１７…トランスファーモールド金型、１８…熱伝導シート、１９…金属基板、２０…樹脂絶縁シート、２１…スペーサ、２２…はんだシート。
DESCRIPTION OF SYMBOLS 1 ... Si chip, 2 ... Hard resin, 3 ... Wire bonding, 4 ... Ceramic substrate, 5 ... Metal base plate, 6 ... Cooling liquid, 7 ... Lead frame, 8 ... Substrate solder, 9 ... Under-chip solder, 10 ... Coolant suction port, 11 ... Coolant discharge port, 12 ... Liquid resin, 13 ... Lead, 14 ... Solder under lead, 15 ... Potting resin, 16 ... Soldering jig, 17 ... Transfer mold die, 18 ... Heat conduction Sheet, 19 ... metal substrate, 20 ... resin insulation sheet, 21 ... spacer, 22 ... solder sheet.

Claims (6)

内部に冷却液を環流させる流路を有する金属製の放熱部と、
前記放熱部上に設けられ、回路層を備える第一の絶縁基板と、
前記第一の絶縁基板上に接合部材により接合された第一の半導体チップと、
前記第一の半導体チップ上に接合された第一の金属配線と、
前記放熱部の、前記第一の絶縁基板を設けた面と反対の面に設けられ、回路層を備える第二の絶縁基板と、
前記第二の絶縁基板上に接合部材により接合された第二の半導体チップと、
前記第二の半導体チップ上に接合された第二の金属配線と、
前記放熱板，前記第一の絶縁基板，第一の半導体チップ，第一の金属配線、第二の絶縁基板，第二の半導体チップ、及び第二の金属配線とを覆う封止樹脂とを備えたことを特徴とするパワー半導体装置。 A metal heat dissipating part having a flow path for circulating the coolant inside;
A first insulating substrate provided on the heat dissipating part and provided with a circuit layer;
A first semiconductor chip bonded to the first insulating substrate by a bonding member;
A first metal wiring bonded on the first semiconductor chip;
A second insulating substrate provided on a surface opposite to the surface on which the first insulating substrate is provided of the heat radiating portion, and provided with a circuit layer;
A second semiconductor chip bonded to the second insulating substrate by a bonding member;
A second metal wiring bonded on the second semiconductor chip;
A sealing resin that covers the heat sink, the first insulating substrate, the first semiconductor chip, the first metal wiring, the second insulating substrate, the second semiconductor chip, and the second metal wiring. A power semiconductor device characterized by the above. 請求項１において、
前記第一の絶縁基板，第一の半導体チップ，第一の金属配線、前記第二の絶縁基板，第二の半導体チップ，第二の金属配線及び前記封止樹脂は、略対称に備えられていることを特徴とするパワー半導体装置。 In claim 1,
The first insulating substrate, the first semiconductor chip, the first metal wiring, the second insulating substrate, the second semiconductor chip, the second metal wiring, and the sealing resin are provided substantially symmetrically. A power semiconductor device. 内部に冷却液を環流させる流路を有する金属製の放熱部と、
前記放熱部上に設けられ、回路層を備える第一の絶縁基板と、
前記第一の絶縁基板上に第一の接合部材により接合された第一の半導体チップと、
前記第一の半導体チップ上に接合された第一の金属配線と、
前記第一の接合部材、前記第一の半導体チップ、及び前記第一の半導体チップと前記第一の金属配線との接合部とを覆う第一のボッティングレジンと、
前記放熱部の、前記第一の絶縁基板を設けた面と反対の面に設けられ、回路層を備える第二の絶縁基板と、
前記第二の絶縁基板上に第二の接合部材により接合された第二の半導体チップと、
前記第二の半導体チップ上に接合された第二の金属配線と、
前記第一の接合部材、前記第一の半導体チップ、及び前記第一の半導体チップと前記第一の金属配線との接合部とを覆う第一のボッティングレジンと、
前記第二の接合部材、前記第二の半導体チップ、及び前記第二の半導体チップと前記第二の金属配線との接合部とを覆う第二のボッティングレジンを備えたことを特徴とするパワー半導体装置。 A metal heat dissipating part having a flow path for circulating the coolant inside;
A first insulating substrate provided on the heat dissipating part and provided with a circuit layer;
A first semiconductor chip bonded to the first insulating substrate by a first bonding member;
A first metal wiring bonded on the first semiconductor chip;
A first botting resin that covers the first bonding member, the first semiconductor chip, and a bonding portion between the first semiconductor chip and the first metal wiring;
A second insulating substrate provided on a surface opposite to the surface on which the first insulating substrate is provided of the heat radiating portion, and provided with a circuit layer;
A second semiconductor chip bonded to the second insulating substrate by a second bonding member;
A second metal wiring bonded on the second semiconductor chip;
A first botting resin that covers the first bonding member, the first semiconductor chip, and a bonding portion between the first semiconductor chip and the first metal wiring;
A power comprising: the second bonding member, the second semiconductor chip, and a second botting resin that covers a bonding portion between the second semiconductor chip and the second metal wiring. Semiconductor device. 請求項３において、
前記第一の絶縁基板，第一の半導体チップ，第一の金属配線、第一のボッティングレジン、前記第二の絶縁基板，第二の半導体チップ，第二の金属配線、及び第二のボッティングレジンは、略対称に備えられていることを特徴とするパワー半導体装置。 In claim 3,
The first insulating substrate, the first semiconductor chip, the first metal wiring, the first botting resin, the second insulating substrate, the second semiconductor chip, the second metal wiring, and the second The power semiconductor device is characterized in that the ting resin is provided substantially symmetrically. 回路を有する絶縁基板上に半導体チップを接合し、前記半導体チップ上に金属配線を接合する工程と、
前記半導体チップ及び前記金属配線を有する前記絶縁基板を、内部に冷却液の還流路を有する放熱板の両面のそれぞれに取り付ける工程と、
前記半導体チップ、前記金属配線、前記絶縁基板、前記放熱板を樹脂封止する工程とを有するパワー半導体装置の製造方法。 Bonding a semiconductor chip on an insulating substrate having a circuit, and bonding metal wiring on the semiconductor chip;
Attaching the insulating substrate having the semiconductor chip and the metal wiring to each of both surfaces of a heat sink having a reflux path for cooling liquid inside;
A method of manufacturing a power semiconductor device, comprising: sealing the semiconductor chip, the metal wiring, the insulating substrate, and the heat sink. 請求項５において、
前記絶縁基板を前記放熱板にスペーサにより押圧した状態で樹脂封止を行うことを特徴とするパワー半導体装置の製造方法。 In claim 5,
A method of manufacturing a power semiconductor device, wherein resin sealing is performed in a state where the insulating substrate is pressed against the heat sink by a spacer.
JP2006195064A 2006-07-18 2006-07-18 Power semiconductor device Pending JP2008027935A (en)

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JP2011050197A (en) * 2009-08-28 2011-03-10 Hitachi Ltd Power converter
WO2024010240A1 (en) * 2022-07-04 2024-01-11 주식회사 아모그린텍 Power module and method for manufacturing same

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