JP6697944B2 - Power semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device that is a key part for efficiently using energy, and more particularly to a printed circuit board on which an insulating substrate on which a power semiconductor element is mounted and a main circuit for the power semiconductor element are formed. The present invention relates to a power semiconductor device including:

  Among the power semiconductor devices that are widely used in a wide range of fields such as industrial equipment, electric railways, home appliances, etc., especially the power semiconductor devices mounted in industrial equipment are required to be compact, have high heat dissipation and have high reliability. .. In such a power semiconductor device, a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or FwDi is mounted on an insulating substrate having high heat dissipation and an aluminum wire or the like is used for the surface electrode of the power semiconductor element. In many cases, wiring is performed to form a circuit.

  In such a structure, the conductor layer pattern formed on the insulating substrate is used for the wiring from the power semiconductor element to the external electrode arranged in the case of the power semiconductor device. Therefore, there is a problem that the area of the expensive insulating substrate increases, the cost increases, and the external shape of the power semiconductor device increases.

  Therefore, in order to reduce the size of the power semiconductor device, in Patent Document 1, an insulating substrate on which a semiconductor element is mounted and a printed circuit board with double-sided wiring are electrically connected with a conductive adhesive such as solder to form a resin casing. A multilayer wiring structure housed in the body has been proposed.

JP2012-74730A

In a normal multilayer wiring structure using a printed circuit board, the main electrodes and signal electrodes of the power semiconductor element are connected only to the copper conductor layer on the back surface (lower surface) of the printed circuit board by soldering.
Since the main electrode is a high-current contact here, it is necessary to secure an insulation distance and reduce thermal strain caused by the difference in expansion coefficient to secure connection reliability. Needs to be as large as possible. On the other hand, in order to increase the transistor density of the signal electrode, it is necessary to reduce the solder height in the signal electrode as much as possible. Therefore, in terms of characteristics, reliability, or productivity, it is necessary to have a configuration capable of forming solder joints having different required heights in the same process. For example, when solder is supplied in advance to form bumps, there is a concern that the solder may overflow and short-circuit, so it is difficult to increase the solder height.

  Patent Document 1 discloses a structure of a power semiconductor device using an insulating substrate and a printed circuit board. However, there is a concern that the solder thickness for the main electrode may change due to the laminated structure, and connection under a temperature cycle may occur. There is some concern about securing reliability.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power semiconductor device capable of improving the connection quality of electrodes in a power semiconductor element as compared with the related art.

In order to achieve the above object, the present invention is configured as follows.
That is, the power semiconductor device according to one aspect of the present invention is a power semiconductor element, an insulating plate member that is positioned to face the power semiconductor element, and has an insulating layer, a proximal conductor layer, and a distal conductor layer, Wherein the insulating layer has a proximal surface proximal to the power semiconductor element and a distal surface distal to the power semiconductor element facing each other in the thickness direction, and the insulating plate member is The proximal conductor layer is provided on the proximal surface, the distal conductor layer is provided on the distal surface, and the main electrode and the distal conductor layer of the power semiconductor element are joined with a first solder, The signal electrode in the power semiconductor element and the proximal conductor layer are joined with a second solder.

  According to the power semiconductor device of one aspect of the present invention, the main electrode in the power semiconductor element is connected to the distal conductor layer located farther from the power semiconductor element in the insulating plate material by soldering, The signal electrode of the semiconductor device for use is connected to the proximal conductor layer of the insulating plate member by soldering. Therefore, according to the power semiconductor device, it is possible to form solder joints having different heights. As a result, in the main electrode, which is a high-current contact, it is possible to secure an insulation distance, and it is possible to relax the thermal stress acting on the solder due to the temperature cycle, and to secure the connection reliability, Further, it is possible to reduce short circuit defects in the signal electrode.

  In addition, since it is possible to perform solder joint with the main electrode without increasing the size of the signal electrode, it is possible to prevent the size of the power semiconductor element from increasing.

  Furthermore, as compared with the case where only the signal electrode is connected by wire bond, the main electrode and the signal electrode are both joined by solder, so that productivity can be improved, and when the main electrode is joined by soldering. It is also possible to suppress the occurrence of wire bond defects in the signal electrodes due to solder scattering.

FIG. 3 is a conceptual diagram of the power semiconductor device according to the first embodiment. It is a conceptual diagram which shows the joining state of the printed circuit board shown in FIG. 1, and a power semiconductor element. FIG. 7 is a conceptual diagram of a power semiconductor device according to a second embodiment. It is a conceptual diagram which shows the joining state of the printed circuit board shown in FIG. 3, and a power semiconductor element. FIG. 9 is a conceptual diagram of a power semiconductor device according to a third embodiment. It is a conceptual diagram which shows the joining state of the printed circuit board shown in FIG. 5, and a power semiconductor element. It is a top view which shows the outline of the junction state of the printed circuit board and the power semiconductor element shown in FIG.

  A power semiconductor device according to an embodiment will be described below with reference to the drawings. In each figure, the same or similar components are designated by the same reference numerals. In addition, in order to avoid unnecessary redundancy in the following description and facilitate understanding by those skilled in the art, detailed description of well-known matters and redundant description of substantially the same configuration may be omitted. .. Further, the contents of the following description and the accompanying drawings are not intended to limit the subject matter described in the claims.

Embodiment 1.
FIG. 1 is a diagram schematically showing the overall structure of a power semiconductor device 101 according to the first embodiment. This power semiconductor device 101 includes, as basic components, an IGBT 20 (Insulated Gate Bipolar Transistor) and a diode 3, which correspond to an example of a power semiconductor element, and a printed circuit board 50 which corresponds to an example of an insulating plate material. The power semiconductor device 101 can further include the insulating substrate 1, the sealing resin 6, the case 7, the electrode terminal 8 and the like, as in the present embodiment. The configuration of such a power semiconductor device 101 will be described below.

  As shown in FIG. 2, the insulating substrate 1 is formed by adhering copper conductor layers 1b and 1c to both surfaces of a resin insulating sheet 1a, and the IGBT 20 and the diode 3 are electrically connected to the copper conductor layer 1c by solder 41. Mechanically connected. Here, as the solder 41, for example, Sn—Ag—Cu based solder is used. Such an insulating substrate 1 also serves as heat dissipation of the IGBT 20 and the diode 3 and wiring on the back side of both semiconductor elements.

  The printed circuit board 50 is arranged in parallel or substantially parallel to the power semiconductor element such as the IGBT 20 mounted on the insulating substrate 1. The printed circuit board 50 has an insulating layer 51 whose material is FR-4 (Flame Retardant Type 4) or the like. As shown in FIG. 2, the insulating layer 51 has a distal surface 51a on the distal side from the power semiconductor element and a proximal surface 51b on the proximal side, which face each other in the thickness direction 51c. The distal conductor layer 52 serving as a circuit pattern is bonded to the distal surface 51a, and the proximal conductor layer 53 serving as a circuit pattern is bonded to the proximal surface 51b, respectively, by an adhesive sheet (not shown). Copper is used as the material of the distal conductor layer 52 and the proximal conductor layer 53, for example. The distal conductor layer 52 and the proximal conductor layer 53 are electrically connected to each other through the through hole 55.

  The distal conductor layer 52 and the proximal conductor layer 53 are joined to the surface electrodes of the IGBT 20 and the diode 3 by solders 42, 43, 44, and are electrically and mechanically connected. As the solder 42, 43, 44, for example, Sn—Ag—Cu based solder is used. Specifically, as shown in FIG. 1, the surface electrode of the diode 3 is bonded to the distal conductor layer 52 of the printed circuit board 50 by solder 44, and the emitter electrode 22 corresponding to the main electrode in the IGBT 20 is bonded by the solder 42. It is joined to the distal conductor layer 52. The gate electrode 21 corresponding to the signal electrode in the IGBT 20 is joined to the proximal conductor layer 53 by the solder 43. In this way, in order to join the surface electrode of the power semiconductor element and the distal conductor layer 52 of the printed board 50 with the solder, the insulating layer 51 and further the proximal conductor layer 53 of the printed board 50 are formed in the thickness direction 51c. Has a through opening 58 that is not in contact with the solders 42 and 44.

  By setting the size of the through opening 58 so as not to contact the solders 42 and 44, the solders 42 and 44 are prevented from being deformed even when the insulating layer 51 having a large linear expansion coefficient in the thickness direction 51c is deformed. can do. Therefore, it is possible to improve the reliability of the solder joint in the presence of the temperature cycle.

Further, the solder 42, 43, 44 for joining the distal conductor layer 52 and the proximal conductor layer 53 in the printed circuit board 50 and the surface electrode of the power semiconductor element such as the IGBT 20 has fillets in order to reduce thermal stress. It is desirable to form.
In the present embodiment, as shown in FIG. 2, the emitter electrode 22 corresponding to the main electrode in the IGBT 20 has a main electrode bonding region 54b bonded to the solder 42. Further, the distal conductor layer 52 of the printed circuit board 50 has a distal conductor layer bonding area 54 a bonded to the solder 42. Here, as shown in FIG. 2, the distal conductor layer bonding region 54a is smaller than the main electrode bonding region 54b. This enables the formation of fillets. The distal conductor layer joint region 54a and the main electrode joint region 54b may be collectively referred to as a joint portion 54.

  In order to form the size of such a joint region, it is sufficient to limit the region where the solder spreads. For example, the area of the through opening 58 in the insulating layer 51 of the printed circuit board 50 is adjusted to form the distal conductor layer bonding region 54a in the distal conductor layer 52, or the distal conductor layer 52 is exposed by solder resist. It can be realized by adjusting the area. Further, in the proximal conductor layer 53, it can be realized by adjusting the pattern area by etching or adjusting the exposed area by the solder resist.

  Further, when the epoxy resin is used for the sealing resin 6, the printed circuit board 50 and the power semiconductor element of the IGBT 20 and the diode 3 facing each other are 0.2 mm or more in order to ensure electrical insulation between them. Gap is required.

Further, as shown in FIG. 1, a case 7 mainly made of PPS (polyphenylene sulfide) is bonded to the outer edge portion of the insulating substrate 1 with a silicone adhesive (not shown). Electrode terminals 8 are inserted in the case 7. The electrode terminal 8 is made of aluminum, for example, and is electrically connected to the distal conductor layer 52 by a bonding wire 9 having a diameter of 0.3 mm, for example.
The sealing resin 6 made of epoxy resin is injected into the case 7 from the gap between the insulating substrate 1 and the printed circuit board 50 until the upper surface of the printed circuit board 50 is covered, and after vacuum degassing, heating and curing.
The power semiconductor device 101 is formed with the configuration described above.

  As shown in FIG. 2, the distal conductor layer bonding region 54 a exists in the plane of the distal conductor layer 52 and is bonded to the emitter electrode 22 of the IGBT 20 with the solder 42. The gate electrode 21 of the IGBT 20 is joined to the proximal conductor layer 53 with the solder 43. The surface electrode of the diode 3 is joined to the distal conductor layer 52 with the solder 44. As a result, in the power semiconductor device 101, in the IGBT 20, the gate electrode 21 having a relatively small area and the emitter electrode 22 having a large area have the proximal conductor layer 53 and the distal conductor layer 52 of the printed circuit board 50. Further, soldering is performed in the same process, respectively, and the formation of solder joints having different heights in the thickness direction 51c is realized. In this way, in the power semiconductor device 101, the solder will not overflow and short-circuit, and the insulating property can be secured.

  Further, the solder 42, 44 for joining the emitter electrode 22 of the IGBT 20 through which a large current flows and the surface electrode of the diode 3 can be formed thick. Therefore, the thermal cycle can relax the thermal stress acting between the IGBT 20 and the solder 42 due to the difference in the thermal expansion coefficient, and the connection reliability can be ensured. Furthermore, short circuit defects in the gate electrode 21 can be reduced.

  Further, as compared with the case where only the gate electrode 21 is connected by wire bonding, the gate electrode 21 as well as the emitter electrode 22 are solder-bonded, so that the productivity can be improved. Further, it is possible to suppress the occurrence of wire bond failure of the gate electrode 21 due to solder scattering at the time of soldering the emitter electrode 22.

  Further, since the gate electrode 21 of the IGBT 20 is designed in accordance with the size of the aluminum wire of φ0.3 mm or φ0.4 mm, for example, the area of the gate electrode 21 can be reduced and the transistor density can be improved. .. As a result, the chip size can be reduced.

If the emitter electrode 22 of the IGBT 20 is connected to the proximal conductor layer 53, a current will flow to the distal conductor layer 52 and further to the electrode terminal 8 via the through hole 55 having a small sectional area and a large resistance. Therefore, there is a concern that the heat generation in the through hole 55 becomes large and the FR-4 printed board 50 having low heat resistance may be broken.
However, in the present embodiment, since the emitter electrode 22 is directly connected to the distal conductor layer 52, the heat generation as described above can be reduced, and the destruction of the printed circuit board 50 can be prevented.

  In addition, the distal conductor layer 52 and the proximal conductor layer 53 in the printed board 50 and the surface electrode in the power semiconductor element such as the IGBT 20 are joined by a plate solder between them for reflow. It is applied and then reflowed, soldered to the surface electrode of the power semiconductor element in advance and then reflowed later, or solder joints are formed in the distal conductor layer 52 and the proximal conductor layer 53 of the printed circuit board 50. It is possible to apply a method of previously bonding a spherical solder to the region to be formed and then performing reflow.

The following configuration example (modification) can be adopted with respect to the configuration of the present embodiment.
That is, in the present embodiment, the IGBT is used as the power semiconductor element, but a similar structure can be formed with the MOSFET.
Also, a similar structure can be formed for an RC-IGBT in which an IGBT and a diode are integrated.
In addition, in the present embodiment, the gate electrode 21 and the emitter electrode 22 of the IGBT 20 are connected to the conductor layer of the printed board 50 by solder, but not limited to the gate electrode 21 and the emitter electrode 22, they are formed on the surface of the power semiconductor element. Similar structures can be formed on the formed main electrode, control electrode, and signal electrode.
Further, in the present embodiment, the diode 3 and the IGBT 20 have a module configuration of one pair of 1in1, but two pairs of 2in1 or six pairs of 6in1, further, a converter and a power semiconductor element serving as a brake are provided. The same effect can be obtained even with the configuration in which one is mounted.

Further, in the present embodiment, the metal substrate using the insulating sheet is used as the material of the insulating substrate 1, but a ceramic substrate formed of a ceramic material such as AlN, alumina and SiN can also obtain the same effect.
Further, in the present embodiment, a printed circuit board 50 having a distal conductor layer 52 and a proximal conductor layer 53 as copper conductor layers formed on both surfaces of an insulating layer 51 is used as a substrate on which a power circuit for a power semiconductor element is formed. Although used, the same effect can be obtained with a ceramic substrate formed of a ceramic material such as AlN, alumina, and SiN.

Although the aluminum bonding wire 9 is used in the present embodiment, the same effect can be obtained by using a copper wire, an aluminum-coated copper wire, or a gold wire.
Further, in the present embodiment, the solder is used for connecting the power semiconductor element and the insulating substrate 1 and for connecting the printed circuit board 50 and the power semiconductor element, but the conductivity obtained by dispersing the Ag filler in the epoxy resin is used. The same effect can be obtained by using an adhesive, Ag nanopowder for firing nanoparticles at a low temperature, Cu nanopowder, or the like.

Although PPS is used as the material of the case 7 in the present embodiment, the same effect can be obtained by using LCP (liquid crystal polymer) having higher heat resistance.
Further, as for the direct potting encapsulating resin, the same effect can be obtained even if it is of a type which is poured and cured at room temperature.
The same effect can be obtained even with a transfer mold package in which the mold is used and the transfer mold sealing resin is used to seal the case.

Embodiment 2.
FIG. 3 is a diagram schematically showing an overall structure of the power semiconductor device 102 according to the second embodiment, and FIG. 4 is a view for explaining joining of the power semiconductor element and the printed board in the power semiconductor device 102. FIG.
The power semiconductor device 102 according to the second embodiment is different from the power semiconductor device 101 according to the above-described first embodiment only in that the distal conductor layer 52 has a solder entry hole 56. Hereinafter, this difference will be mainly described, and description of the same or similar components will be omitted.

  As described in the first embodiment, the distal conductor layer 52 of the printed circuit board 50 has the distal conductor layer bonding region 54a to which the surface electrode of the power semiconductor element, for example, the emitter electrode 22 of the IGBT 20 is soldered. As shown in FIGS. 3 and 4, the solder entry hole 56 is a hole that is located at a location corresponding to the distal conductor layer joining region 54a and penetrates the distal conductor layer 52 in the thickness direction 51c.

  By providing the solder entry hole 56, the solder 42 can enter the solder entry hole 56 when the emitter electrode 22 in the IGBT 20 is solder-joined, for example. The power semiconductor device 102 having the solder entry hole 56 has the effects of the above-described power semiconductor device 101 of the first embodiment, and the solder entry hole 56 provides the following effects.

  That is, as described in the first embodiment, the conductor layers (the distal conductor layer 52 and the proximal conductor layer 53) of the printed circuit board 50 and the surface electrodes of the power semiconductor element are made of plate-shaped solder 42, 43,. They are joined by sandwiching 44 between them and performing reflow, or applying cream solder and performing reflow. Here, if the solder supply amount becomes excessive, there is a possibility that a phenomenon may occur in which the solder drops from the power semiconductor element. Therefore, by providing the solder entry hole 56, it is possible to take in excess solder into the solder entry hole 56 and absorb variations in the solder supply amount. As a result, the manufacturing process can be stabilized.

Further, during soldering, voids that hinder heat dissipation may occur in the solder layer, and these voids need to be degassed by evacuation or the like. At the time of defoaming, the voids are released only from the exposed surface of the solder. Therefore, by providing the solder entry hole 56, the exposed surface of the solder joint portion is increased and the void can be reduced.
Further, since the distal conductor layer 52 has the solder entry hole 56, the distal conductor layer 52 is supplied with the solder 42, 44 that is joined to the surface electrodes of the IGBT 20 and the diode 3, and the presence or absence of the joining is determined by the solder entry hole. It is possible to confirm through 56. Therefore, the inspection process can be simplified and the time can be shortened.

  The structural changes in the power semiconductor device 101 described in the first embodiment can also be applied to the power semiconductor device 102 of the present embodiment.

Embodiment 3.
FIG. 5 is a diagram schematically showing the overall structure of the power semiconductor device 103 according to the third embodiment, and FIG. 6 is a view for explaining the joining of the power semiconductor element and the printed board in the power semiconductor device 103. FIG.
The power semiconductor device 103 according to the third embodiment is different from the power semiconductor device 101 according to the above-described first embodiment only in that the distal conductor layer 52 has a resin entry opening 57. Hereinafter, this difference will be mainly described, and description of the same or similar components will be omitted.

  The resin entry opening 57 is, for example, as shown in FIG. 7, an opening that penetrates the distal conductor layer 52 in the thickness direction 51c in a part of the periphery of the distal conductor layer bonding region 54a, and is the insulating layer 51 of the printed circuit board 50. In communication with the above-described through opening 58.

  The power semiconductor device 103 having the resin entrance opening 57 has the effects of the above-described power semiconductor device 101 of the first embodiment. By providing the resin entrance opening 57, the following effects are further produced.

That is, since the insulating substrate 1 and the printed circuit board 50 arranged to face each other need to be electrically insulated from each other, the sealing resin 6 is provided in the gap between the insulating substrate 1 and the printed circuit board 50. Need to be filled. Further, in the IGBT 20 and the diode 3, in order to secure the creepage insulation distance between the front and back of each element, the sealing resin 6 needs to be filled in the gap.
However, the gap is narrow and it is difficult for the sealing resin 6 to be filled, so that an unfilled region may occur. In particular, the space between the solder joints between the surface electrode of the power semiconductor element and the printed circuit board 60 is narrow and difficult to fill. For this, it is effective to shorten the inflow distance of the sealing resin 6.

  Therefore, by providing the resin entrance opening 57 in the outer peripheral portion of the distal conductor layer joining region 54a in the distal conductor layer 52 of the printed board 50, the sealing resin 6 passes through the resin entrance opening 57 and the insulating substrate 1 and the printed board. It is possible to easily enter the gap with 50. Therefore, it is possible to prevent the unfilled area of the sealing resin 6 from being generated.

  Further, by having the resin entry opening 57, the state of the solder fillet of the solders 42 and 44 bonded to the IGBT 20 and the diode 3 and the distal conductor layer 52, as well as the IGBT 20 and the diode 3 and the insulating substrate 1 are formed. It becomes possible to easily inspect each bonding state by visual inspection or the like. Therefore, it becomes possible to easily perform the inspection process of each bonding state in a short time.

  The structural changes in the power semiconductor device 101 described in the first embodiment can also be applied to the power semiconductor device 103 in the present embodiment.

  Further, it is possible to adopt a configuration in which the above-described respective embodiments are combined, and it is also possible to combine the constituent parts shown in different embodiments.

3 diode, 20 IGBT, 21 gate electrode, 22 emitter electrode,
41-44 solder, 50 printed circuit board, 51 insulating layer,
51a distal surface, 51b proximal surface, 51c thickness direction, 52 distal conductor layer,
53 proximal conductor layer, 54a distal conductor layer joining region, 54b main electrode joining region,
56 solder entry hole, 57 resin entry opening, 58 through opening,
101-103 Power semiconductor devices.

Claims (4)

Power semiconductor device,
An insulating plate member, which is located opposite to the power semiconductor element and has an insulating layer, a proximal conductor layer and a distal conductor layer,
The insulating layer has a proximal surface proximal to the power semiconductor element and a distal surface distal to the power semiconductor element, which face each other in the thickness direction.
The insulating plate material has the proximal conductor layer on the proximal surface and the distal conductor layer on the distal surface,
The main electrode and the distal conductor layer in the power semiconductor element are joined with a first solder,
The signal electrode in the power semiconductor element and the proximal conductor layer are joined with a second solder ,
The distal conductor layer has a distal conductor layer bonding region bonded to the first solder, the main electrode has a main electrode bonding region bonded to the first solder, and The lower conductor layer bonding area is smaller than the main electrode bonding area,
A power semiconductor device characterized by the above.   The power semiconductor device according to claim 1, wherein the insulating layer and the proximal conductor layer have through openings that are not in contact with the first solder in the thickness direction. The power semiconductor according to claim 1 or 2 , wherein the distal conductor layer has a solder entry hole penetrating the distal conductor layer in the thickness direction at a position corresponding to the distal conductor layer joining region. apparatus. Said distal conductor layer, a part of the periphery of the distal conductor layer junction region, the distal conductor layer having a resin entrance aperture through to the thickness direction, the power semiconductor according to claim 1 or 2 apparatus.

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