JP2010287651A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010287651A
JP2010287651A JP2009138990A JP2009138990A JP2010287651A JP 2010287651 A JP2010287651 A JP 2010287651A JP 2009138990 A JP2009138990 A JP 2009138990A JP 2009138990 A JP2009138990 A JP 2009138990A JP 2010287651 A JP2010287651 A JP 2010287651A
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semiconductor element
opening
main surface
insulator
semiconductor device
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JP5201085B2 (en
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Daigo Ueno
大悟 上野
Takashi Hirota
崇 広田
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Nissan Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for improving a heat radiation properties by reducing the thermal resistance. <P>SOLUTION: A semiconductor device includes a semiconductor element 11, arranged between a first bus bar 21 and a second bus bar 22 mutually arranged opposite via an insulating body 42. The opening dimension of a first opening part of the insulating body 42, which is larger than the dimension of a first main surface electrode formed on a first main surface of the semiconductor element 11 and smaller than the outside dimension of the semiconductor element 11 is formed. The first main surface electrode and the first bus bar 21 are electrically connected, in the inside of the first opening part by the first junction body 31, and the depth of the first opening part and the thickness of the first junction body 31 are set substantially the same. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体素子の対向する両主面に通電部材が接合されて封止された半導体装置に関する。   The present invention relates to a semiconductor device in which a current-carrying member is bonded to both opposing main surfaces of a semiconductor element and sealed.

従来、この種の技術としては、例えば以下に示す文献に記載されたものが知られている（特許文献１参照）。互いに対向する第一および第二主表面を有する半導体素子と、第一主表面に接触し、貫通ビアを含む多層配線基板と、第二主表面に接触する導電性接合材とを備え、上記多層配線基板を用いて半導体素子と大電流用リードとの接続がなされた半導体装置における冷却構造の技術が記載されている。   Conventionally, as this type of technology, for example, those described in the following documents are known (see Patent Document 1). A semiconductor device having first and second main surfaces facing each other, a multilayer wiring substrate in contact with the first main surface and including a through via, and a conductive bonding material in contact with the second main surface. A technology of a cooling structure in a semiconductor device in which a semiconductor element and a large current lead are connected using a wiring board is described.

特開２００７−１２６８５号公報JP 2007-12485 A

上記従来の半導体装置においては、半導体素子の第一主表面と大電流用リードとの間に、熱伝導率の悪い絶縁体を含む多層配線基板が配設されていた。このため、半導体素子の第一主表面側は、第二主表面側に比べて配設された絶縁体により熱抵抗が高くなり、放熱性が悪化するおそれがあった。   In the conventional semiconductor device, a multilayer wiring board including an insulator having poor thermal conductivity is disposed between the first main surface of the semiconductor element and the large current lead. For this reason, the first main surface side of the semiconductor element has a higher thermal resistance due to the insulator disposed as compared with the second main surface side, and there is a possibility that the heat dissipation property is deteriorated.

そこで、本発明は、上記に鑑みてなされたものであり、その目的とするところは、熱抵抗を低減して、放熱性を向上した半導体装置を提供することにある。   Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device with improved heat dissipation by reducing thermal resistance.

上記目的を達成するために、本発明は、第一の通電部材と第二の通電部材との間に介在する絶縁体に第一の開口部が形成され、第一の開口部は半導体素子の第一の主面に形成された第一の主面電極よりも大きくかつ半導体素子よりも小さく、この第一の開口部の内側で第一の主面電極と第一の通電部材とが第一の導電性接合体により電気的に接続されていることを特徴とする。   In order to achieve the above object, according to the present invention, a first opening is formed in an insulator interposed between a first energization member and a second energization member, and the first opening is formed of a semiconductor element. It is larger than the first main surface electrode formed on the first main surface and smaller than the semiconductor element, and the first main surface electrode and the first current-carrying member are first inside the first opening. It is electrically connected by the conductive joined body.

本発明によれば、絶縁体に形成された第一の開口部で半導体素子の第一の主面電極と第一の導電部材とが電気的に接続されているので、半導体装置の熱抵抗が低減されて放熱性を向上することができる。   According to the present invention, since the first main surface electrode of the semiconductor element and the first conductive member are electrically connected through the first opening formed in the insulator, the thermal resistance of the semiconductor device is reduced. It is reduced and heat dissipation can be improved.

本発明の実施例１に係る半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 1 of this invention. 半導体素子の第一の主面側から見た半導体素子の正面図である。It is the front view of the semiconductor element seen from the 1st main surface side of the semiconductor element. 半導体素子の第二の主面側から見た半導体素子の正面図である。It is the front view of the semiconductor element seen from the 2nd main surface side of the semiconductor element. 第一のバスバー側から見た本発明の実施例１に係る配線部材の正面図である。It is a front view of the wiring member which concerns on Example 1 of this invention seen from the 1st bus-bar side. 図４のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 第二のバスバー側から見た配線部材の正面図である。It is a front view of the wiring member seen from the 2nd bus-bar side. 本発明の実施例１に係る半導体装置のはんだ付け前の様子を示す断面図である。It is sectional drawing which shows the mode before soldering of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例２に係る半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 2 of this invention. 本発明の実施例２に係る半導体装置における配線部材の断面図である。It is sectional drawing of the wiring member in the semiconductor device which concerns on Example 2 of this invention. 本発明の実施例２に係る半導体装置における配線部材の接合前の断面図である。It is sectional drawing before joining of the wiring member in the semiconductor device which concerns on Example 2 of this invention. 本発明の実施例３に係る半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 3 of this invention. 第一のバスバー側から見た本発明の実施例３に係る配線部材の正面図である。It is a front view of the wiring member which concerns on Example 3 of this invention seen from the 1st bus-bar side. 本発明の実施例４に係る半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 4 of this invention. 第一のバスバー側から見た本発明の実施例４に係る配線部材の正面図である。It is a front view of the wiring member which concerns on Example 4 of this invention seen from the 1st bus-bar side.

以下、図面を用いて本発明を実施するための実施例を説明する。   Embodiments for carrying out the present invention will be described below with reference to the drawings.

図１は本発明の実施例１に係る半導体装置の構成を示す断面図である。図１に示す実施例１の半導体装置は、例えばＩＧＢＴ等のパワー半導体素子で構成された半導体素子１１を備え、この半導体素子１１の一方の主面（第一の主面）がはんだ等からなる第一の接合体（導電性接合体）３１を介して第一のバスバー（通電部材）２１に接合され、かつ第一の主面に配設された第一の主面電極（図示せず）が第一のバスバー２１に配設された対応する電極（図示せず）に接続されている。また、半導体素子１１の他方の主面（第二の主面）がはんだ等からなる第二の接合体３２を介して第二のバスバー２２に接合され、かつ第二の主面に配設された第二の主面電極（図示せず）が第一のバスバー２２に配設された対応する電極（図示せず）に接続されている。第一のバスバー２１ならびに第二のバスバー２２は、大電流を通電するための導電部材として機能し、銅やアルミニウムもしくはこれらの金属を含む合金等で構成される。   FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device of Example 1 shown in FIG. 1 includes a semiconductor element 11 made of a power semiconductor element such as an IGBT, and one main surface (first main surface) of the semiconductor element 11 is made of solder or the like. A first main surface electrode (not shown) that is bonded to the first bus bar (conducting member) 21 via the first bonded body (conductive bonded body) 31 and disposed on the first main surface. Are connected to corresponding electrodes (not shown) arranged on the first bus bar 21. Further, the other main surface (second main surface) of the semiconductor element 11 is bonded to the second bus bar 22 via a second bonded body 32 made of solder or the like, and is disposed on the second main surface. A second main surface electrode (not shown) is connected to a corresponding electrode (not shown) disposed on the first bus bar 22. The first bus bar 21 and the second bus bar 22 function as conductive members for passing a large current, and are made of copper, aluminum, an alloy containing these metals, or the like.

第一のバスバー２１と第二のバスバー２２との間には、両バスバーに接合した配線部材４１が半導体素子１１の周囲に配設されている。配線部材４１は、絶縁体４２の内部に導体パターン２４が形成されて構成されている。絶縁体４２に被覆された導体パターン２４は、その一端がはんだ等の第三の接合体３３を介して半導体素子１１の第一の主面側に配設された信号系電極（図示せず）に電気的に接続される一方、他端がはんだ等の第四の接合体３４を介して信号端子２３に電気的に接続されている。信号端子２３は、半導体素子１１と装置外部とを電気的に接続する機能を有し、銅やアルミニウムもしくはこれらの金属を含む合金等で構成される。絶縁体４２は、樹脂成形により形成された樹脂成型品で構成されている。   Between the first bus bar 21 and the second bus bar 22, a wiring member 41 joined to both bus bars is disposed around the semiconductor element 11. The wiring member 41 is configured by forming a conductor pattern 24 inside an insulator 42. The conductor pattern 24 coated with the insulator 42 has a signal system electrode (not shown) having one end disposed on the first main surface side of the semiconductor element 11 via a third joined body 33 such as solder. The other end is electrically connected to the signal terminal 23 via a fourth joined body 34 such as solder. The signal terminal 23 has a function of electrically connecting the semiconductor element 11 and the outside of the apparatus, and is made of copper, aluminum, or an alloy containing these metals. The insulator 42 is composed of a resin molded product formed by resin molding.

上記構成要素は、樹脂５１により封止されて半導体装置として構成されている。樹脂５１は、トランスファーモールドやポッティングなどによって形成されるエポキシやシリコーンなどで構成される。   The above components are sealed with a resin 51 and configured as a semiconductor device. The resin 51 is made of epoxy, silicone, or the like formed by transfer molding or potting.

図２は第一の主面側から見た半導体素子１１の正面図である。図２において、半導体素子１１の第一の主面には、エミッタ電極等からなる第一の主面電極１２と、ゲート信号や半導体素子１１の温度センサ等の信号系電極１４が形成されている。信号系電極１４は、第三の接合体３３を介して図１に示す導体パターン２４に接続されている。   FIG. 2 is a front view of the semiconductor element 11 as viewed from the first main surface side. In FIG. 2, a first main surface electrode 12 made of an emitter electrode or the like and a signal system electrode 14 such as a gate signal or a temperature sensor of the semiconductor element 11 are formed on the first main surface of the semiconductor element 11. . The signal system electrode 14 is connected to the conductor pattern 24 shown in FIG.

図３は第二の主面側から見た半導体素子１１の正面図である。図３において、半導体素子１１の第二の主面には、例えばコレクタ電極等からなる第二の主面電極１３が形成されている。   FIG. 3 is a front view of the semiconductor element 11 as seen from the second main surface side. In FIG. 3, a second main surface electrode 13 made of, for example, a collector electrode is formed on the second main surface of the semiconductor element 11.

図４は第一のバスバー２１側から見た配線部材４１の正面図である。図４において、配線部材４１は、絶縁体４２の中に導体パターン２４を内包して構成され、半導体素子１１が位置する空間として第一の開口部４３が形成されている。   FIG. 4 is a front view of the wiring member 41 as viewed from the first bus bar 21 side. In FIG. 4, the wiring member 41 is configured by including a conductor pattern 24 in an insulator 42, and a first opening 43 is formed as a space in which the semiconductor element 11 is located.

図５は図４のＡ−Ａ線に沿った断面図である。図５において、配線部材４１に形成された第一の開口部４３の面積は、半導体素子１１の第一の主面電極１２の面積よりも大きく、かつ半導体素子１１の外形面積よりも小さく形成されている。また、第一の開口部４３と、半導体素子１１の第二の主面側に形成された第三の開口部４５との間の配線部材４１には、半導体素子１１が配置収納される第二の開口部４４が形成されている。第一の開口部４３は、第二の開口部４４に半導体素子１１を配置した際に、図２に示すいずれの信号系電極１４も第一の開口部４３から露出しないように形成されている。   FIG. 5 is a cross-sectional view taken along line AA in FIG. In FIG. 5, the area of the first opening 43 formed in the wiring member 41 is larger than the area of the first main surface electrode 12 of the semiconductor element 11 and smaller than the outer area of the semiconductor element 11. ing. Further, in the wiring member 41 between the first opening 43 and the third opening 45 formed on the second main surface side of the semiconductor element 11, the second semiconductor element 11 is disposed and accommodated. The opening 44 is formed. The first opening 43 is formed so that none of the signal system electrodes 14 shown in FIG. 2 is exposed from the first opening 43 when the semiconductor element 11 is disposed in the second opening 44. .

また、第一の開口部４３の深さ方向における絶縁体部４２ａの厚みＢは、第一の接合体３１の厚さと同等に設定され、絶縁体４２の全体の厚みＣは、半導体素子１１を第一のバスバー２１および第二のバスバー２２に接合した後の所望の両バスバー間距離と同等に設定形成されている。   Further, the thickness B of the insulator portion 42a in the depth direction of the first opening 43 is set to be equal to the thickness of the first bonded body 31, and the total thickness C of the insulator 42 is the same as that of the semiconductor element 11. The distance between the first bus bar 21 and the second bus bar 22 is set to be equal to the desired distance between both bus bars after joining.

図６は第二のバスバー２２側から見た配線部材４１の正面図である。図６において、絶縁体４２に一部が被覆される導体パターン２４のうち、露出部２４ａ，２４ｂは絶縁体４２から露出されている。また、第二の開口部４４の面積は、半導体素子１１の外形面積と同等に設定されている。さらに、第三の開口部４５の面積は、第二の開口部４４の面積よりも大きく設定されている。第二の開口部４４の中心位置と第三の開口部４５の中心位置とはほぼ一致している。   FIG. 6 is a front view of the wiring member 41 as viewed from the second bus bar 22 side. In FIG. 6, exposed portions 24 a and 24 b are exposed from the insulator 42 in the conductor pattern 24 partially covered by the insulator 42. The area of the second opening 44 is set to be equal to the outer area of the semiconductor element 11. Further, the area of the third opening 45 is set larger than the area of the second opening 44. The center position of the second opening 44 and the center position of the third opening 45 substantially coincide.

上記したように、この実施例１では、半導体素子１１は、第一の接合体３１を介して第一のバスバー２１に接合しているため、半導体素子１１で発生する熱損失を第一のバスバー２１に放熱することが可能となる。これにより、半導体素子１１の熱抵抗を低減することが可能となり、放熱性を向上させることができる。   As described above, in the first embodiment, since the semiconductor element 11 is bonded to the first bus bar 21 via the first bonded body 31, heat loss generated in the semiconductor element 11 is reduced to the first bus bar. It is possible to radiate heat to 21. Thereby, the thermal resistance of the semiconductor element 11 can be reduced, and the heat dissipation can be improved.

また、以下に説明するように、半導体素子１１や第一の接合体３１、第二の接合体３２の位置決めを行いつつ、１回のはんだ付け工程で実装可能となるため、工程を簡易化することができる。   In addition, as described below, the semiconductor element 11, the first joined body 31, and the second joined body 32 can be mounted while being positioned in a single soldering process, thus simplifying the process. be able to.

図７は半導体素子１１のはんだ付け工程前における図１に示す構成要件の断面図である。なお、図７は図１と天地逆（第一のバスバー２１が図面下方、第二のバスバー２２が図面上方）に記載されている。   7 is a cross-sectional view of the constituent requirements shown in FIG. 1 before the soldering process of the semiconductor element 11. 7 is shown upside down from FIG. 1 (the first bus bar 21 is at the bottom of the drawing and the second bus bar 22 is at the top of the drawing).

第一のバスバー２１上に、配線部材４１を載置して、配線部材４１の第一、第二ならびに第三の各開口部４３，４４，４５のそれぞれに、第一の接合体３１、半導体素子１１、第二の接合体３２を載置する。このときの第一の接合体３１ならびに第二の接合体３２は、それぞれ別体部品であり、本実施例１ではシート状のはんだ材料で構成されている。   The wiring member 41 is placed on the first bus bar 21, and the first joined body 31, the semiconductor is placed in each of the first, second and third openings 43, 44, 45 of the wiring member 41. The element 11 and the second joined body 32 are placed. The first joined body 31 and the second joined body 32 at this time are separate parts, and in the first embodiment, they are made of a sheet-like solder material.

第一の接合体３１は、第一の開口部４３のサイズと同等以下である。第一の開口部４３の面積は半導体素子１１の第一の主面電極１２の面積よりも大きく、半導体素子１１の外形面積よりも小さいため、第一の接合体３１を第一の主面電極１２と接する箇所に位置決めすることができる。   The first joined body 31 is equal to or smaller than the size of the first opening 43. Since the area of the first opening 43 is larger than the area of the first main surface electrode 12 of the semiconductor element 11 and smaller than the outer area of the semiconductor element 11, the first joined body 31 is used as the first main surface electrode. 12 can be positioned at a location in contact with 12.

また、第二の開口部４４の面積は半導体素子１１の外形面積と同等の大きさであり、第三の開口部４５の面積は第二の接合体３２の面積と同等以上である。その上、第二の開口部４４と第三の開口部４５の中心位置とはほぼ一致している。これにより、半導体素子１１の第二の主面電極１３の全体に、第二の接合体３４を接触させた状態で位置決めすることができる。   The area of the second opening 44 is the same size as the outer area of the semiconductor element 11, and the area of the third opening 45 is equal to or larger than the area of the second bonded body 32. In addition, the center positions of the second opening 44 and the third opening 45 substantially coincide with each other. As a result, the second bonded body 34 can be positioned in contact with the entire second main surface electrode 13 of the semiconductor element 11.

以上のように、配線部材４１を用いて、半導体素子１１、第一の接合体３１、第二の接合体３２の位置決めを一括して行うことができる。また、絶縁体４２の絶縁体部４２ａの厚さＢは、第一の接合体３１の仕上り厚さと同等であるため、はんだ付け後の第一の接合体３１の厚さを管理しやすくなる。   As described above, the positioning of the semiconductor element 11, the first joined body 31, and the second joined body 32 can be performed at once using the wiring member 41. Moreover, since the thickness B of the insulator part 42a of the insulator 42 is equal to the finished thickness of the first joined body 31, the thickness of the first joined body 31 after soldering can be easily managed.

さらに、半導体素子１１は絶縁体４２の絶縁体部４２ａに接しているため、はんだ付け工程で接合体が溶融した時に半導体素子１１が傾いて接合体の厚さがばらつくことを低減することができる。   Furthermore, since the semiconductor element 11 is in contact with the insulator portion 42a of the insulator 42, it is possible to reduce the variation in the thickness of the bonded body due to the inclination of the semiconductor element 11 when the bonded body is melted in the soldering process. .

また、絶縁体４２の厚みＣを両バスバー間の間隔と同等としているため、はんだ付け時に絶縁体４２がスペーサとして機能し、第一のバスバー２１と第二のバスバー２２との関係をほぼ水平に保ちつつ、両バスバー間距離を管理することが可能となる。それに伴って、第二の接合体３２の厚さも均一に管理することができる。   In addition, since the thickness C of the insulator 42 is equal to the distance between the two bus bars, the insulator 42 functions as a spacer during soldering, and the relationship between the first bus bar 21 and the second bus bar 22 is substantially horizontal. It is possible to manage the distance between both bus bars while maintaining the same. Accordingly, the thickness of the second bonded body 32 can be managed uniformly.

図８は本発明の実施例２に係る半導体装置の構成を示す断面図である。この実施例２の特徴とするところは、先の実施例１に対して、配線部材４１を多層配線基板で構成したことにあり、他は先の実施例１と同様である。配線部材４１を構成する多層配線基板は、図９の断面図に示すように構成されている。図９において、多層配線基板は、４層の第一の絶縁基材４６１〜第四の絶縁基材４６４が積層されて形成されている。第一の絶縁基材４６１には、先の図５に示す第一の開口部４３と同様の第一の開口部４７１が形成され、第二の絶縁基材４６２ならびに第三の絶縁基材４６３には、先の図５に示す第二の開口部４４と同様の第二の開口部４７２と第三の開口部４７３とが形成され、第四の絶縁基材４６４には、先の図５に示す第三の開口部４５と同様の第四の開口部４７４が形成されている。   FIG. 8 is a sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. The feature of the second embodiment is that the wiring member 41 is formed of a multilayer wiring board with respect to the previous first embodiment, and the others are the same as the first embodiment. The multilayer wiring board constituting the wiring member 41 is configured as shown in the sectional view of FIG. In FIG. 9, the multilayer wiring board is formed by laminating four layers of a first insulating base 461 to a fourth insulating base 464. A first opening 471 similar to the first opening 43 shown in FIG. 5 is formed in the first insulating base 461, and the second insulating base 462 and the third insulating base 463 are formed. A second opening 472 and a third opening 473 similar to the second opening 44 shown in FIG. 5 are formed, and the fourth insulating base 464 has the same structure as that shown in FIG. A fourth opening 474 similar to the third opening 45 shown in FIG.

また、第一の絶縁基材４６１には第一の導体パターン４８１が形成され、第二の絶縁基材４６２には第二の導体パターン４８２が形成され、第三の絶縁基材４６３には第三の導体パターン４８３が形成され、第四の絶縁基材４６４には第四の導体パターン４８４が形成されている。第一の導体パターン４８１は、第二の絶縁基材４６２に形成された貫通ビア２５を介して第二の導体パターン４８２と電気的に接続され、第二の導体パターン４８２は、第三の絶縁基材４６３に形成された貫通ビア２５を介して第三の導体パターン４８３と電気的に接続され、第三の導体パターン４８３は、第三の絶縁基材４６３に形成された貫通ビア２５を介して第四の導体パターン４８４と電気的に接続されている。   In addition, the first conductor pattern 481 is formed on the first insulating substrate 461, the second conductor pattern 482 is formed on the second insulating substrate 462, and the first conductor pattern 482 is formed on the third insulating substrate 463. Three conductor patterns 483 are formed, and a fourth conductor pattern 484 is formed on the fourth insulating substrate 464. The first conductor pattern 481 is electrically connected to the second conductor pattern 482 through the through via 25 formed in the second insulating substrate 462, and the second conductor pattern 482 is connected to the third insulating pattern 482. The third conductor pattern 483 is electrically connected to the third conductor pattern 483 through the through via 25 formed in the base material 463, and the third conductor pattern 483 is connected to the third insulating substrate 463 through the through via 25. The fourth conductor pattern 484 is electrically connected.

また、第一の開口部４７１の深さ方向における絶縁体部４２１ａの厚みＢは、先の図５に示す絶縁体部４２ａの厚みＢと同様であり、多層配線基板の全体の厚みＣは、先の図５に示す絶縁体４２の全体の厚みＣと同様である。   Further, the thickness B of the insulator portion 421a in the depth direction of the first opening 471 is the same as the thickness B of the insulator portion 42a shown in FIG. 5, and the overall thickness C of the multilayer wiring board is: This is the same as the overall thickness C of the insulator 42 shown in FIG.

次に、図１０に示す配線部材４１を構成する多層配線基板の断面図を参照して、多層配線基板の製造方法を説明する。   Next, a method for manufacturing a multilayer wiring board will be described with reference to a cross-sectional view of the multilayer wiring board constituting the wiring member 41 shown in FIG.

先ず、一層あたりの厚さが５０〜１００μｍ程度の各絶縁基材４６１〜４６４に、厚さ１０〜３０μｍ程度の導体パターン４８１〜４８４を対応して形成する。また、第二〜第四の絶縁基材４６２〜４６４に貫通ビア２５を設けて、その貫通ビア２５中に導電性ペーストを充填し、もしくは銅めっきを形成することで、各絶縁基材４６１〜４６４に形成された導体パターン４８１〜４８４間の接続を確保する。   First, conductor patterns 481 to 484 having a thickness of about 10 to 30 μm are formed on the respective insulating base materials 461 to 464 having a thickness of about 50 to 100 μm. Further, by providing through vias 25 in the second to fourth insulating bases 462 to 464 and filling the through vias 25 with conductive paste or forming copper plating, the respective insulating bases 461 to 461 are provided. Connection between conductor patterns 481 to 484 formed on 464 is ensured.

続いて、各絶縁基材４６１〜４６４にそれぞれ第一の開口部４７１〜第四の開口部４７４を形成する。その後、各絶縁基材４６１〜４６４を熱圧着したり、もしくは接着剤で張り合わせることにより、多層配線基板である配線部材４１を形成する。   Subsequently, a first opening 471 to a fourth opening 474 are formed in each of the insulating base materials 461 to 464, respectively. Thereafter, the insulating bases 461 to 464 are thermocompression bonded or bonded together with an adhesive to form the wiring member 41 that is a multilayer wiring board.

このように、本実施例２においては、先の実施例と同様の効果を得ることができることに加えて、精度良く厚みの管理がしやすい絶縁機材４６１〜４６４を用いて配線部材４１を形成することで、各部位の寸法精度を確保しやすくなる。それにより、半導体素子１１や第一の接合体３１、第二の接合体３２の位置決め精度を向上することができる。   As described above, in the second embodiment, in addition to obtaining the same effects as those of the previous embodiment, the wiring member 41 is formed using the insulating equipments 461 to 464 that are easy to manage the thickness with high accuracy. This makes it easy to ensure the dimensional accuracy of each part. Thereby, the positioning accuracy of the semiconductor element 11, the first joined body 31, and the second joined body 32 can be improved.

また、第一の開口部４７１〜第四の開口部４７４は、各絶縁基材４６１〜４６４を張り合わせて一体化した後、プレス加工や切削加工により形成してもよい。その際に、各絶縁基材４６１〜４６４を張り合わせる前に、各絶縁基材４６１〜４６４に対応して各開口部４７１〜４７４を形成する予定領域にレジストを塗布しておくことにより、確実に各開口部４７１〜４７４を形成しやすくなる。   The first opening 471 to the fourth opening 474 may be formed by pressing or cutting after the insulating bases 461 to 464 are bonded and integrated. At that time, before pasting the insulating base materials 461 to 464, it is ensured by applying a resist to the regions where the openings 471 to 474 are formed corresponding to the insulating base materials 461 to 464. It becomes easy to form each opening 471-474.

なお、上記実施例２では、配線部材４１は、４層の多層配線基板で構成しているが、多層配線基板の層数は４層に限ることはない。   In the second embodiment, the wiring member 41 is composed of a four-layer multilayer wiring board, but the number of layers of the multilayer wiring board is not limited to four.

図１１は本発明の実施例３に係る半導体装置の構成を示す断面図であり、図１２は第一のバスバー２１側から見た配線部材４１の正面図である。すなわち、図１１は図１２のＡ−Ａ線に沿った断面図である。   11 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention, and FIG. 12 is a front view of the wiring member 41 as viewed from the first bus bar 21 side. That is, FIG. 11 is a cross-sectional view along the line AA in FIG.

この実施例３の特徴とするところは、先の実施例１に対して、配線部材４１を構成する絶縁体４２内に導体パターン２６を形成したことにあり、他は先の実施例１と同様である。   The feature of the third embodiment is that the conductor pattern 26 is formed in the insulator 42 constituting the wiring member 41 with respect to the first embodiment, and the other is the same as the first embodiment. It is.

導体パターン２６は、先に説明した導体パターン２４と同様に銅やアルミニウム、もしくはこれらの金属を含む合金などから構成され、熱伝導性の良好な金属で構成されている。導体パターン２６は、図１２に示すように半導体素子１１の外周に配置形成されて、第一のバスバー２１に接する面が絶縁体４２から露出され、半導体素子１１の信号系電極１４と接続される導体パターン２４とは、電気的に接続されていない。   The conductor pattern 26 is made of copper, aluminum, an alloy containing these metals, or the like, like the conductor pattern 24 described above, and is made of a metal having good thermal conductivity. As shown in FIG. 12, the conductor pattern 26 is disposed and formed on the outer periphery of the semiconductor element 11, and the surface in contact with the first bus bar 21 is exposed from the insulator 42 and connected to the signal system electrode 14 of the semiconductor element 11. The conductor pattern 24 is not electrically connected.

このような構成において、半導体素子１１の外周に沿って絶縁体４２に配置形成された導体パターン２６は、第一のバスバー２１と第二のバスバー２２との間の熱伝導経路として機能する。したがって、半導体素子１１で発生した熱は導体パターン２６によって第一のバスバー２１側に放熱しやすくなり、半導体素子１１の熱抵抗を低減するが可能となる。   In such a configuration, the conductor pattern 26 arranged and formed on the insulator 42 along the outer periphery of the semiconductor element 11 functions as a heat conduction path between the first bus bar 21 and the second bus bar 22. Therefore, the heat generated in the semiconductor element 11 is easily radiated to the first bus bar 21 side by the conductor pattern 26, and the thermal resistance of the semiconductor element 11 can be reduced.

また、本実施例３の半導体素子１１をはんだ付けする際に、第一のバスバー２１と第二のバスバー２２との温度差を小さくすることができる。このため、第一の接合体３１と第二の接合体３２をほぼ同時に溶融及び凝固させることが可能となり、各接合体の厚さを管理制御しやすくなる。さらに、半導体素子１１の外周に沿って導体パターン２６を設けているため、配線部材４１の反りを低減することが可能である。   Moreover, when soldering the semiconductor element 11 of the third embodiment, the temperature difference between the first bus bar 21 and the second bus bar 22 can be reduced. For this reason, the first joined body 31 and the second joined body 32 can be melted and solidified almost simultaneously, and the thickness of each joined body can be easily managed and controlled. Furthermore, since the conductor pattern 26 is provided along the outer periphery of the semiconductor element 11, it is possible to reduce the warp of the wiring member 41.

なお、本実施例３においては、導体パターン２６は第一のバスバー２１に接する面が絶縁体４２から露出しているが、第一のバスバー２１と第二のバスバー２２との間の所望の絶縁性が確保できれば、この限りではない。すなわち、導体パターン２６の第二のバスバー２２に接する面が絶縁体４２から露出してもよく、もしくはいずれのバスバー側にも絶縁体４２から導体パターン２６が露出していなくともよい。   In Example 3, the surface of the conductor pattern 26 that is in contact with the first bus bar 21 is exposed from the insulator 42, but desired insulation between the first bus bar 21 and the second bus bar 22. If sex can be secured, this does not apply. That is, the surface of the conductor pattern 26 in contact with the second bus bar 22 may be exposed from the insulator 42, or the conductor pattern 26 may not be exposed from the insulator 42 on either bus bar side.

図１３は本発明の実施例４に係る半導体装置の構成を示す断面図であり、図１４は第一のバスバー２１側から見た配線部材４１の正面図である。   FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to Example 4 of the present invention, and FIG. 14 is a front view of the wiring member 41 viewed from the first bus bar 21 side.

この実施例４の特徴とするところは、先の実施例１に対して、配線部材４１を構成する絶縁体４２に高熱伝導性樹脂４７を形成したことにあり、他は先の実施例１と同様である。   The feature of the fourth embodiment is that a high thermal conductive resin 47 is formed on the insulator 42 constituting the wiring member 41 with respect to the first embodiment. It is the same.

高熱伝導性樹脂４７は、アルミナやシリカ等の無機材料フィラーを含有した樹脂で構成され、半導体素子１１の外周に沿って半導体素子１１の第一の主面に接して配置形成されている。高熱伝導性樹脂４７は、信号系電極１４と接続される導体パターン２４とは電気的に接続されていない。   The high thermal conductive resin 47 is made of a resin containing an inorganic material filler such as alumina or silica, and is disposed along the outer periphery of the semiconductor element 11 in contact with the first main surface of the semiconductor element 11. The high thermal conductive resin 47 is not electrically connected to the conductor pattern 24 connected to the signal system electrode 14.

このような構成においては、半導体素子１１と第一のバスバー２１との間に高熱伝導性樹脂４７が配置形成されているので、半導体素子１１で発生する熱損失を高熱伝導性樹脂４７を介して第一のバスバー２２へ放熱しやすくすることが可能となる。これにより、半導体素子１１の熱抵抗を低減することができる。   In such a configuration, since the high thermal conductive resin 47 is disposed between the semiconductor element 11 and the first bus bar 21, the heat loss generated in the semiconductor element 11 is caused to pass through the high thermal conductive resin 47. It becomes possible to make it easy to radiate heat to the first bus bar 22. Thereby, the thermal resistance of the semiconductor element 11 can be reduced.

なお、高熱伝導性樹脂４７に代えて、アルミナ、窒化アルミニウム等の絶縁性のセラミックスで構成しても、同様の効果を得ることが可能である。   It should be noted that the same effect can be obtained by using insulating ceramics such as alumina and aluminum nitride instead of the high thermal conductive resin 47.

以上の各実施例１〜４において、第一〜第四の各接合体３１〜３４は、はんだに代えて、エポキシやウレタン等の樹脂に銀やカーボン等の導電性フィラーを含んだ導電性接着剤であってもかなわない。   In each of the above Examples 1 to 4, each of the first to fourth joined bodies 31 to 34 is a conductive adhesive containing a conductive filler such as silver or carbon in a resin such as epoxy or urethane instead of solder. It can be an agent.

なお、上記実施例１〜４は、適宜組み合わせて実施してもかまわない。   In addition, you may implement the said Examples 1-4 suitably combining.

１１…半導体素子
１２，１３…主面電極
１４…信号系電極
２１，２２…バスバー
２３…信号端子
２４，２６，４８１〜４８４…導体パターン
２４ａ，２４ｂ…露出部
２５…貫通ビア
３１〜３４…接合体
４１…配線部材
４２…絶縁体
４２ａ，４２１ａ…絶縁体部
４３〜４５，４３２，４７１〜４７４…開口部
４７…高熱伝導性樹脂
５１…樹脂
４６１〜４６４…絶縁機材 DESCRIPTION OF SYMBOLS 11 ... Semiconductor element 12, 13 ... Main surface electrode 14 ... Signal system electrode 21, 22 ... Bus bar 23 ... Signal terminal 24, 26, 481-484 ... Conductor pattern 24a, 24b ... Exposed part 25 ... Through-via 31-34 ... Junction Body 41 ... Wiring member 42 ... Insulator 42a, 421a ... Insulator part 43-45, 432, 471-474 ... Opening 47 ... High thermal conductive resin 51 ... Resin 461-464 ... Insulation equipment

Claims (7)

絶縁体を介して対向配置された第一の通電部材と第二の通電部材との間に半導体素子が配置された半導体装置において、
前記絶縁体は、前記半導体素子の第一の主面に形成された第一の主面電極よりも大きく、かつ前記半導体素子よりも小さい第一の開口部が形成され、前記第一の開口部の内側で前記第一の主面電極と前記第一の通電部材とが第一の導電性接合体により電気的に接続され、前記第一の開口部の深さと前記第一の導電性接合体の厚さとは同一である
ことを特徴とする半導体装置。 In a semiconductor device in which a semiconductor element is disposed between a first energization member and a second energization member that are disposed to face each other via an insulator,
The insulator has a first opening that is larger than the first main surface electrode formed on the first main surface of the semiconductor element and smaller than the semiconductor element, and the first opening The first main surface electrode and the first current-carrying member are electrically connected to each other by a first conductive joint, and the depth of the first opening and the first conductive joint The thickness of the semiconductor device is the same. 前記第一の通電部材と前記第二の通電部材との間の間隔と前記絶縁体の厚さとは同一であり、
前記絶縁体は、開口寸法が前記半導体素子の外形寸法と同一の第二の開口部と、開口寸法が第二の導電性接合体の外形寸法と同一な第三の開口部とが形成され、前記第二の開口部の内側に前記半導体素子が配置され、前記第三の開口部の内側で前記半導体素子の第二の主面に形成された第二の主面電極と前記第二の通電部材とが前記第二の導電性接合体により電気的に接続されている
ことを特徴とする請求項１に記載の半導体装置。 The distance between the first energization member and the second energization member and the thickness of the insulator are the same,
The insulator is formed with a second opening whose opening dimension is the same as the outer dimension of the semiconductor element, and a third opening whose opening dimension is the same as the outer dimension of the second conductive joint, The semiconductor element is disposed inside the second opening, and the second main surface electrode formed on the second main surface of the semiconductor element inside the third opening and the second energization 2. The semiconductor device according to claim 1, wherein a member is electrically connected by the second conductive joined body. 前記第二の導電性接合体の外形寸法は前記半導体素子の外形寸法よりも大きく、前記第二の開口部と前記第三の開口部との中心は一致している
ことを特徴とする請求項２に記載の半導体装置。 The outer dimension of the second conductive joined body is larger than the outer dimension of the semiconductor element, and the centers of the second opening and the third opening coincide with each other. 2. The semiconductor device according to 2. 前記半導体素子の外周の前記絶縁体の内部に熱伝導体を設けた
ことを特徴とする請求項１〜３のいずれか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein a heat conductor is provided inside the insulator on an outer periphery of the semiconductor element. 前記半導体素子の第一の主面と接する高熱伝導性樹脂を前記絶縁体の内部に設けた
ことを特徴とする請求項１〜４のいずれか１項に記載の半導体装置。 5. The semiconductor device according to claim 1, wherein a high thermal conductive resin in contact with a first main surface of the semiconductor element is provided inside the insulator. 前記絶縁体は、前記半導体素子と前記半導体装置の外部とを電気的に接続する配線を含む多層配線基板で構成されている
ことを特徴とする請求項１〜５のいずれか１項に記載の半導体装置。 The said insulator is comprised with the multilayer wiring board containing the wiring which electrically connects the said semiconductor element and the exterior of the said semiconductor device, The any one of Claims 1-5 characterized by the above-mentioned. Semiconductor device. 前記絶縁体は、樹脂成型品で構成されている
ことを特徴とする請求項１〜６のいずれか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the insulator is formed of a resin molded product.
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