KR20210127229A - Semiconductor module and semiconductor device used therefor - Google Patents

Abstract

A semiconductor module comprising a first heat dissipation member (1, 7), a semiconductor element (20), a sealing material (21) covering the periphery, and a first wiring (26) and a second wiring (26) electrically connected to the semiconductor element ( 27), comprising a semiconductor element and a redistribution layer 24 formed on the sealing material, the semiconductor device 2 mounted on the first heat dissipating member, and the second heat dissipating member 3 disposed on the semiconductor device , 7), a lead frame 4 electrically connected to the semiconductor device via a bonding material 5, and a sealing material 6 covering a part of the first heat dissipation member, the semiconductor device, and a part of the second heat dissipation member. do. A part of the semiconductor device protrudes from the periphery of the other surface 3b of the second heat dissipation member facing the semiconductor device, and the second wiring has one end protruding from the periphery of the other surface of the semiconductor device. It extends to the junction, and one end is electrically connected to the lead frame via a bonding material.

Description

Semiconductor module and semiconductor device used therefor

This application is based on Japanese Patent Application No. 2019-51516 for which it applied on March 19, 2019 and Japanese Patent Application No. 2020-27188 for which it applied on February 20, 2020, here The disclosure is incorporated by reference.

The present disclosure relates to a semiconductor module having a double-sided heat dissipation structure with two heat dissipating members facing each other with a power semiconductor element interposed therebetween, and a semiconductor device used therein.

Conventionally, as a semiconductor module of a double-sided heat dissipation structure provided with power semiconductor elements, such as an IGBT, and two heat dissipation members opposingly interposed therebetween, the thing described in patent document 1 is mentioned, for example. In the semiconductor module described in Patent Document 1, a lower heat sink, a power semiconductor element, a heat dissipation block, and an upper heat sink are laminated in this order via solder. In addition, this semiconductor module has a lead frame, a wire electrically connecting the lead frame and the gate of the power semiconductor element, and a sealing material covering them. In this semiconductor module, a surface of the lower heat sink and the upper heat sink that is opposite to the power semiconductor element is exposed from the sealing material. That is, this semiconductor module is configured to emit heat generated by energizing the power semiconductor element to the outside via these two heat sinks, that is, a heat dissipation member.

Japanese Patent Laid-Open No. 2001-156225

In the above-mentioned semiconductor module, the heat dissipation block is arranged so that the gap between the two heat dissipation members is greater than or equal to a predetermined value, and the heat dissipation member and the wire are contacted to prevent a short circuit. However, this heat dissipation block is a factor that inhibits the thickness reduction of the semiconductor module and increases the thermal resistance from the power semiconductor element to the heat dissipation member.

An object of the present disclosure is to provide a semiconductor module having a double-sided heat dissipation structure comprising a power semiconductor element and two heat dissipating members disposed oppositely therebetween, and having a thinner and lower heat resistance than in the prior art, and a semiconductor device used therefor. do.

According to one aspect of the present disclosure, a semiconductor module includes a first heat dissipation member, a semiconductor element, a sealing material covering the periphery, and first and second wirings electrically connected to the semiconductor element, and the semiconductor element and a lead frame having a redistribution layer formed on the sealing material, the semiconductor device mounted on the first heat dissipating member, the second heat dissipating member disposed on the semiconductor device, and electrically connected to the semiconductor device via a bonding material; , a portion of the first heat dissipation member, a semiconductor device, and a sealing material covering a portion of the second heat dissipation member, wherein the semiconductor device is partially protruded from the periphery of the other surface of the second heat dissipation member facing the semiconductor device, The second wiring has one end extending to a portion protruding from the periphery of the other surface of the semiconductor device, and one end thereof is electrically connected to the lead frame through solder.

Thereby, the semiconductor device and the second heat dissipation member, and the semiconductor device and the lead frame are respectively connected to each other via a bonding material to form a semiconductor module having a heat dissipation structure on both sides. Therefore, in this semiconductor module, the heat dissipation block and wire, which were required in the conventional structure, are unnecessary, and the thickness and heat resistance are reduced accordingly, so that the thickness and the heat resistance are reduced compared to the conventional one.

According to another aspect of the present disclosure, a semiconductor device is a semiconductor device used in a semiconductor module having a double-sided heat dissipation structure including a first heat dissipation member and a second heat dissipation member, and is disposed between the first heat dissipation member and the second heat dissipation member, A semiconductor element, a sealing material surrounding the semiconductor element, and a redistribution layer formed on the semiconductor element and the sealing material; It has a first wiring and a second wiring, wherein the first wiring is arranged inside the outer periphery of the semiconductor element when viewed from the top, and the second wiring extends to a region where the other end is outside the outer periphery of the semiconductor element as seen from the top. extension is installed.

According to this, the semiconductor device described above can be soldered to the second heat dissipation member and lead frame without using a heat dissipation block or wire, and is a configuration suitable for manufacturing a semiconductor module that is thinner and has lower heat resistance than before. .

In addition, reference numerals given in parentheses attached to each component or the like indicate an example of a corresponding relationship between the component and the specific component described in the embodiment described later.

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows the structure of the semiconductor module of 1st Embodiment.
FIG. 2 is a cross-sectional view showing the configuration of the semiconductor device in FIG. 1 .
3 is a perspective view illustrating the semiconductor device of FIG. 2 .
4 is a cross-sectional view showing the configuration of a conventional semiconductor module.
FIG. 5A is a semiconductor device manufacturing process among the semiconductor module manufacturing process of FIG. 1 , and is a cross-sectional view illustrating a semiconductor substrate preparation process.
FIG. 5B is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5A.
FIG. 5C is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5B.
FIG. 5D is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5C.
FIG. 5E is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5D.
5F is a cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to FIG. 5E.
FIG. 5G is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5F.
5H is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5G.
FIG. 5I is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5H.
FIG. 5J is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5I.
FIG. 5K is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5J.
FIG. 5L is a cross-sectional view illustrating a manufacturing process of a semiconductor device subsequent to FIG. 5K.
FIG. 5M is a cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to FIG. 5L.
FIG. 6A is a manufacturing process of the semiconductor module of FIG. 1, and is a cross-sectional view showing a mounting process of a semiconductor device.
6B is a cross-sectional view illustrating a manufacturing process of a semiconductor module subsequent to FIG. 6A.
Fig. 6C is a plan view showing the manufacturing process of Fig. 6B;
FIG. 6D is a cross-sectional view illustrating a manufacturing process of a semiconductor module subsequent to FIG. 6B.
7 is a cross-sectional view showing the configuration of a semiconductor module according to the second embodiment.
8 is a cross-sectional view showing the configuration of a semiconductor module according to a third embodiment.
9 is a perspective view illustrating a semiconductor device in the semiconductor module of FIG. 8 .
Fig. 10 is a plan view showing an example of arrangement of each component in the semiconductor module of Fig. 8;
11 is a cross-sectional view showing a configuration of a modified example of the semiconductor module of the third embodiment.
12 is a cross-sectional view showing a configuration example of a lead frame in a semiconductor module according to a fourth embodiment.
Fig. 13 is an arrow view seen from the direction XIII shown in Fig. 12 .
14 is a view for explaining stress generated in a lead frame not provided with a stress relief unit.
FIG. 15 is a diagram showing a first modified example of the stress relaxation unit, and is an arrow diagram corresponding to FIG. 13 .
FIG. 16 is a view showing a second modified example of the stress relaxation unit, and is a cross-sectional view corresponding to FIG. 12 .
Fig. 17 is an arrow view viewed from the direction of XVII shown in Fig. 16 .
18 is a cross-sectional view showing the configuration of a semiconductor module according to the fifth embodiment.
19 is a view for explaining a surface of a heat sink that faces a semiconductor device;
20 is a view for explaining a gap between the other surface of the heat sink and one surface of the semiconductor device.
21 is a cross-sectional view showing a configuration of a modified example of the semiconductor module of the fifth embodiment.
22 is a cross-sectional view showing a configuration example of a semiconductor device in a semiconductor module according to the sixth embodiment.
23 is a cross-sectional view showing a configuration example of a lead frame in a semiconductor module according to the seventh embodiment.
24 is a cross-sectional view showing a configuration of a modified example of the lead frame according to the seventh embodiment.
25 is a cross-sectional view showing a configuration example of a semiconductor device in a semiconductor module according to an eighth embodiment.
26 is a plan view showing an arrangement example of a projection in the semiconductor device according to the eighth embodiment.
27 is a plan view showing another example of arrangement of the projections in the semiconductor device according to the eighth embodiment.
28 is a cross-sectional view showing the configuration of another modified example of the third embodiment.
29 is a cross-sectional view showing a configuration of a modified example of a semiconductor device according to another embodiment.
30 is a cross-sectional view showing a configuration of a modified example of the second embodiment.
31 is a cross-sectional view showing the configuration of another modification of the third embodiment.
32 is a cross-sectional view showing a configuration of a modification of the first embodiment.
FIG. 33 is a diagram showing a molding process of a sealing material in the manufacturing process of the semiconductor module shown in FIG. 32; FIG.
34 is a cross-sectional view showing the configuration of another modification of the fifth embodiment.
Fig. 35 is a cross-sectional view showing a configuration example of a semiconductor module using a heat transfer insulating substrate having a step portion.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this indication is described based on drawing. In addition, in each of the following embodiments, the same code|symbol is attached|subjected to mutually the same or equal parts, and description is carried out.

(First embodiment)

The semiconductor module S1 of the first embodiment will be described with reference to FIGS. 1 to 3 . The semiconductor module S1 is preferably used, for example, in a power converter that converts direct current into alternating current in order to supply electric power to a driving motor of a vehicle, and may be referred to as a "power card".

In FIG. 1, the wiring part connected to the outside in the other cross section of the 2nd heat sink 3 mentioned later is shown with the broken line. In FIG. 2, the boundary of the area|region which partitioned the insulating layer 25 mentioned later is shown with the broken line for convenience. In addition, FIG. 2 corresponds to the cross-sectional view taken along II-II shown by the dashed-dotted line in FIG.

(Configuration)

As shown in FIG. 1 , the semiconductor module S1 of the present embodiment includes a first heat sink 1 , a semiconductor device 2 , a second heat sink 3 , a lead frame 4 , and a bonding material. (5) and a sealing material (6). In the semiconductor module S1, two heat sinks 1 and 3 are disposed to face each other with the semiconductor device 2 interposed therebetween, and heat generated from the semiconductor device 2 is interposed between the heat sinks 1 and 3 It is a double-sided heat dissipation structure that is emitted from both sides to the outside.

As shown in FIG. 1, the 1st heat sink 1 becomes a plate shape provided with the upper surface 1a and the lower surface 1b which exist in front-back relationship, For example, Cu (copper) or Fe (iron). ) is made of a metal material such as In the first heat sink 1 , the semiconductor device 2 is mounted on the upper surface 1a via a bonding material 5 made of solder, and the lower surface 1b is exposed from the sealing material 6 . In the present embodiment, the first heat sink 1 serves as a current path for energization of the semiconductor device 2 , and as shown in FIG. 1 , for example, a portion of the upper surface 1a side is formed of a sealing material. (6) is extended to the outside. That is, in this embodiment, the 1st heat sink 1 plays two roles of a heat radiation member and wiring. Also, the first heat sink 1 may be referred to as a “first heat dissipation member”.

As shown in FIG. 2 , the semiconductor device 2 has a plate shape having a front surface 2a and a rear surface 2b , and includes a semiconductor element 20 , a sealing material 21 , a first electrode 22 , and , a second electrode 23 and a redistribution layer 24 . The semiconductor device 2 has the second wiring 27 connected to the second electrode 23 as a part of the redistribution layer 24 , and one end of the second wiring 27 is outside the semiconductor element 20 . It is a fan-out type package structure (hereinafter referred to as "FO package structure") extended to the outside. In addition, the semiconductor device 2 may have an FO package structure, a wafer level package structure may be sufficient, and a panel level package structure may be sufficient as it.

As shown in FIG. 1 , the semiconductor device 2 is disposed inside the outer periphery of the upper surface 1a of the first heat sink 1 . In the semiconductor device 2, a part of the second heat sink 3 protrudes outward from the outer edge of the opposite surface 3b, and one end of the second wiring 27 extends to the protruding portion. It is an extended structure. This is because the wire connection with the lead frame 4 and the heat dissipation block between the semiconductor device 2 and the second heat sink 3 are unnecessary, so that it is possible to reduce the thickness and reduce the heat resistance compared to the prior art. This detail will be described later.

The semiconductor element 20 is mainly composed of a semiconductor material such as silicon and silicon carbide, and is, for example, a power semiconductor element such as a MOS transistor and an IGBT (Insulated Gate Bipolar Transistor), and is manufactured by a normal semiconductor process. In the semiconductor element 20 , a third electrode (not shown) is formed on a surface opposite to the surface on which the first electrode 22 and the second electrode 23 are formed, and the third electrode is formed with a bonding material 5 interposed therebetween. It is electrically connected to the upper surface 1a of the heat sink 1 .

The sealing material 21 is a member which covers the periphery of the semiconductor element 20, as shown in FIG. 2, For example, it is comprised with arbitrary resin materials, such as an epoxy resin. The sealing material 21 covers the end surface of the semiconductor element 20 and the back surface 2b of the semiconductor device 2 together with the surface on the opposite side to the surface on which the 1st electrode 22 is formed among the semiconductor elements 20. constitutes

The first electrode 22 , the second electrode 23 , and the third electrode (not shown) are made of, for example, a metal material such as Cu, and are formed on one surface of the semiconductor element 20 by electrolytic plating or the like. . The first electrode 22 and the third electrode become a pair, and serve as a main current path of the semiconductor element 20 . The first electrode 22 is, for example, an emitter electrode. A plurality of second electrodes 23 are formed, and at least one of them becomes, for example, a gate electrode, and is used to control current on/off between the first electrode 22 and the third electrode. In addition, a thing different from a gate electrode among the some 2nd electrode 23 is used as a sensor terminal etc. on an element other than this, for example.

In addition, the first electrode 22 and the second electrode 23 are formed of a metal material such as Cu by electrolytic plating in the same manner as the first wiring 26 and the second wiring 27 in a manufacturing method to be described later. Compared with the case of being composed of a material such as , Al (aluminum), the heat dissipation property is improved.

As shown in FIG. 2 , the redistribution layer 24 includes an insulating layer 25 , a first wiring 26 connected to the first electrode 22 , and a second wiring connected to the second electrode 23 . It has a wiring 27 and is formed on the semiconductor element 20 and the sealing material 21 by a normal redistribution technique.

The insulating layer 25 is made of, for example, an insulating material such as polyimide, and is formed by an arbitrary application process or the like.

The first wiring 26 and the second wiring 27 are made of, for example, a Cu metal material or the like, and are formed by electrolytic plating or the like. The first wiring 26 is formed inside the outer periphery of the semiconductor element 20 when viewed from the top, and one end thereof is electrically and thermally connected to the second heat sink 3 via a bonding material 5 . The second wiring 27 is electrically connected to the lead frame 4 via a bonding material 5 while having one end extending outward from the outer periphery of the semiconductor element 20 when viewed from the top. For example, as shown in FIG. 3 , a plurality of second wirings 27 are formed, and one end of each of the second wirings 27 is extended to the outside of the semiconductor element 20 . 3 shows an example in which five second wirings 27 are formed and each is connected to different second electrodes 23, the number of second electrodes 23 and second wirings 27 is shown. is arbitrary for

As shown in FIG. 1, the 2nd heat sink 3 becomes a plate shape provided with the one surface 3a and the other surface 3b which are in a front-back relationship, and is made of the same material as the 1st heat sink 1. composed by The second heat sink 3 is disposed to face a part of the surface 2a of the semiconductor device 2 in the present embodiment. In the present embodiment, the second heat sink 3 is electrically connected to the first wiring 26 via the bonding material 5 , so that similarly to the first heat sink 1 , the current path of the semiconductor element 20 . In the other cross section of FIG. 1 , a part of the other surface 3b side is extended to the outside of the sealing material 6 . That is, in the present embodiment, the second heat sink 3 plays two roles: a heat dissipation member and wiring. Also, the second heat sink 3 may be referred to as a “second heat dissipation member”.

The lead frame 4 is made of, for example, a metal material such as Cu or Fe, and as shown in FIG. 1 , the second wiring 27 and the bonding material 5 in the semiconductor device 2 are interposed therebetween. to be electrically connected. The lead frame 4 includes, for example, a plurality of leads of the same number as that of the second electrode 23 . In addition, these leads are connected by a tie bar (not shown) until the sealing material 6 is formed. However, after the sealing material 6 is formed, the leads are separated by removing the tie bars by press punching or the like. do. In addition, the lead frame 4 may be comprised by the same member as the 2nd heat sink 3, and may be connected by the tie bar which is not shown until formation of the sealing material 6. Even in this case, the lead frame 4 is in a state separated from the second heat sink 3 by removing the tie bar by press punching or the like after the formation of the sealing material 6 .

The bonding material 5 is a bonding material for bonding the components of the semiconductor module S1 to each other, and in order to electrically connect them, a material having conductivity, for example, solder or the like is used. In addition, although the bonding material 5 is not limited to solder, at least a thing different from a wire is used.

The sealing material 6 is made of, for example, a thermosetting resin such as an epoxy resin, and as shown in FIG. 1 , a part of the heat sinks 1 and 3 , the semiconductor device 2 , and the lead frame 4 . Part and the bonding material 5 are covered.

The above is the basic structure of the semiconductor module S1 of this embodiment.

(effect)

Next, the effect of the semiconductor module S1 of this embodiment is demonstrated in comparison with the semiconductor module S100 of the conventional structure shown in FIG.

First, the semiconductor module S100 of the conventional structure will be briefly described. In addition, since the structure of the semiconductor module S100 is well-known, here, the difference with the semiconductor device 2 is mainly demonstrated.

As shown in FIG. 4 , the semiconductor module S100 having a conventional structure includes a semiconductor device 101 , heat sinks 1 and 3 opposed therebetween, a heat dissipation block 102 , and a wire 103 . and a lead frame 4 , a bonding material 5 , and a sealing material 6 .

As shown in FIG. 4 , the semiconductor device 101 includes a semiconductor element 20 including a first electrode 22 , a second electrode 23 , and a third electrode (not shown). Unlike (2), the sealing material 21 and the redistribution layer 24 are not provided. The semiconductor device 101 is mounted on the first heat sink 1 with the bonding material 5 interposed therebetween, and the outer inner side of the upper surface 1a of the first heat sink 1 and the second heat sink 3 . It is arranged inside the outer periphery of the other surface 3b.

The heat dissipation block 102 is made of a metal material such as Cu, and as shown in FIG. 4 , one side thereof is connected to the first electrode 22 of the semiconductor element 20 via a bonding material 5 , , the other surface is connected to the second heat sink 3 via the bonding material 5 . The heat dissipation block 102 serves to form a current path of the semiconductor device 20 and to transmit heat generated by the semiconductor device 20 to the second heat sink 3 . Further, in the heat dissipation block 102 , the gap between the semiconductor element 20 and the second heat sink 3 is greater than or equal to a predetermined value, and the wire 103 connected to the second electrode 23 is connected to the second heat sink 3 . ) to prevent short-circuiting.

The wire 103 is made of a metal material such as Al (aluminum) and Au (gold), is joined to the second electrode 23 and the lead frame 4 by wire bonding, and electrically connects them.

The above-described conventional semiconductor module S100 has a structure in which it is difficult to further reduce thickness since it is necessary to secure a gap by arranging the heat dissipation block 102 between the semiconductor device 101 and the second heat sink 3 . In the semiconductor module S100 , two layers of bonding materials and one heat dissipation block 102 are interposed between the semiconductor device 101 and the second heat sink 3 , and the thermal resistance increases accordingly.

On the other hand, in the semiconductor module S1 of the present embodiment, the semiconductor device 2 has a configuration including the redistribution layer 24 , and a part of the semiconductor module S1 of the second heat sink 3 is outside the outer edge of the other surface 3b of the second heat sink 3 . It is arranged so as to be hollowed out. In the semiconductor module S1, a bonding material 5 made of solder is interposed between the second wirings 27 provided to extend outward from the outer periphery of the other surface 3b of the second heat sink 3 of the semiconductor device 2 . Thus, the structure is joined to the lead frame (4). Therefore, in the semiconductor module S1, it becomes possible to directly solder the semiconductor device 2 and the 2nd heat sink 3, and the heat dissipation block 102 and the wire 103 become unnecessary.

As a result, only one layer of bonding material 5 is used to connect the semiconductor device 2 and the second heat sink 3 , and the thickness of the heat dissipation block 102 and the first layer of bonding material 5 becomes smaller. , furthermore, it becomes a semiconductor module having a structure with a small thermal resistance. From another point of view, it can be said that the semiconductor device 2 has an FO package structure, so that solder bonding with the lead frame 4 is possible, and it can be said that a structure suitable for thinning and low heat resistance of a semiconductor module having a double-sided heat dissipation structure. have. In addition, since the semiconductor device 2 has a configuration including the redistribution layer 24 , the planar size of the first electrode 22 or the second electrode 23 , and furthermore, the planar size of the semiconductor element 20 can be reduced. Therefore, the effect of improving the cost aspect is also expected.

In addition, the area of the second heat sink 3 is simply reduced, and the second electrode 23 of the semiconductor element 20 on which the redistribution layer 24 is not formed is placed outside the outer portion of the second heat sink 3 . It is also conceivable to arrange to connect the second electrode 23 and the lead frame 4 with the wire 103.

However, in the case of this method, the heat dissipation block 102 becomes unnecessary, and although the thermal resistance becomes small by that much, it also becomes small also with respect to the planar size of the 2nd heat sink 3, and a thermal resistance will become large by that much. As a result, in the semiconductor module having such a structure, there is a fear that the heat dissipation performance does not change or rather deteriorates compared to the prior art. Moreover, in order to connect the wire 103, the planar size of the 2nd electrode 23 must be enlarged, and since the planar size of the semiconductor element 20 becomes large with this, we are anxious about a deterioration in cost. In addition, when the wire 103 is used, the wiring length is required to prevent a short circuit, and the inductance becomes large.

Accordingly, the semiconductor module S1 using the semiconductor device 2 having the FO package structure has a thinner and low thermal resistance structure than in the prior art, as well as noise reduction of high frequency signals and miniaturization of the semiconductor element 20 . The effect of cost reduction is also expected.

(Manufacturing method)

Next, an example of the manufacturing method of the semiconductor module S1 of this embodiment is demonstrated with reference to FIGS. 5A-6C.

First, as shown in FIG. 5A , a semiconductor element 20 manufactured by a conventional semiconductor process is prepared, and a surface on which the first electrode 22 and the second electrode 23 are formed later among the semiconductor elements 20 . is attached to and held on the support substrate 110 . In addition, as this support substrate 110, any thing provided with the adhesive sheet (not shown) with high adhesiveness with silicone on the surface, for example is used.

Next, a mold not shown is prepared, the semiconductor element 20 held by the support substrate 110 is covered with a resin material such as an epoxy resin by compression molding or the like, and cured by heating or the like, as shown in Fig. 5B. As described above, the sealing material 21 is molded. Thereafter, the semiconductor element 20 covered with the sealing material 21 is peeled off from the support substrate 110 .

Next, on the exposed surface of the semiconductor element 20, a solution containing a photosensitive resin material such as polyimide is applied by a spin coating method or the like and dried, and as shown in FIG. 5C, the insulating layer 25 A first layer 251 constituting the

Then, as shown in Fig. 5D, after the first layer 251 is patterned by a photolithography etching method, a first seed layer 281 made of Cu or the like is formed by a vacuum deposition method such as sputtering. do.

Thereafter, as shown in FIG. 5E , a resist layer 253 covering the first layer 251 and the first seed layer 281 is formed. The resist layer 253 uses a photosensitive resin material, and similarly to the first layer 251, it can be formed by a spin coating method or the like.

Subsequently, the resist layer 253 is patterned by the same process as for the patterning of the first layer 251 , and as shown in FIG. 5F , an opening including a region from which the first layer 251 has been removed. to form

Next, a plating layer of Cu or the like is formed by electrolytic plating or the like, and as shown in FIG. 5G , the first electrode 22 and the second electrode 23 are formed, and then, a part of the first wiring 26 is formed. and a part of the second wiring 27 .

Then, as shown in FIG. 5H , after the resist layer 253 is removed with a stripper or the like, a portion of the first seed layer 281 exposed by the removal of the resist layer 253 is removed with an etching solution.

Thereafter, as shown in FIG. 5I , a second layer 252 constituting the insulating layer 25 is formed by spin coating using a photosensitive resin material so as to be the same as that of the first layer 251 . After that, patterning is performed by a photolithography etching method.

Subsequently, as shown in Fig. 5J, a second seed layer 282 made of Cu or the like is formed by a vacuum film forming method such as sputtering. After forming the second seed layer 282 , a resist layer 253 is formed on the second layer 252 by the same process as above and patterned, as shown in FIG. 5K , A resist layer 253 covering the second layer 252 , a part of the first wiring 26 , and a part of the second wiring 27 is formed.

Next, after forming the remainder of the first wiring 26 and the second wiring 27 made of Cu or the like by electrolytic plating or the like, the resist layer 253 is removed with a stripper to remove the resist layer 253 . The second seed layer 282 exposed by the removal is removed with an etchant or the like. Thereby, as shown in FIG. 5L, the redistribution layer 24 provided with the 1st wiring 26 and the 2nd wiring 27 is formed on the semiconductor element 20 and the sealing material 21. As shown in FIG.

Then, as shown in FIG. 5M , the surface of the sealing material 21 on the opposite side to the redistribution layer 24 is thinned by polishing or the like to expose the semiconductor element 20 . Thereafter, a third electrode (not shown) is formed on the exposed surface of the semiconductor element 20 by a vacuum film forming method such as sputtering. In addition, the third electrode (not shown) may be formed only on the exposed surface of the semiconductor element 20 , and in addition to the exposed surface, the entire surface of the polished surface including the surface opposite to the redistribution layer 24 among the sealing material 21 . may be formed in In the former case, the third electrode can be formed only on the exposed surface of the semiconductor device 20 by using a metal mask (not shown).

Although the semiconductor device 2 can be manufactured by the above process, any semiconductor process other than the above may be employ|adopted. For example, in the process of preparing the semiconductor element 20 shown in FIG. 5A, you may prepare the semiconductor element 20 in which the 3rd electrode was formed. In this case, after covering the third electrode with the sealing material 21 , the third electrode is exposed by reducing the thickness of the sealing material 21 , but there is no problem in particular. In this way, about the manufacturing process of the semiconductor device 2, you may change suitably.

Then, as shown in FIG. 6A, the 1st heat sink 1 which consists of metal materials, such as Cu, is prepared, and the semiconductor device 2 is solder-bonded thereon. The first heat sink 1 may be subjected to press punching on a metal plate made of Cu, for example, and then subjected to dry etching to form a wiring portion connected to an external power supply or the like. obtained by

Next, as shown in FIG. 6B , after applying solder on the first wiring 26 and the second wiring 27 of the semiconductor device 2 , a second heat separately prepared on the first wiring 26 . The sink 3 is mounted, the lead frame 4 is mounted on the second wiring 27, and solder bonding is performed. As a result, as shown in FIG. 6C , the semiconductor device 2 is arranged inside the outer periphery of the first heat sink 1 in plan view, and a part of the semiconductor device 2 is emptied from the outer periphery of the second heat sink 3 . While coming out, it will be in the state connected with the lead frame 4 in the said protruding part. Moreover, as shown in FIG. 6C, it is preferable that the semiconductor device 2 becomes a larger planar dimension than the part connected to the semiconductor device 2 among at least one heat sink. This is because it becomes easy to fill a resin material in shaping|molding of the sealing material 6 demonstrated next, and generation|occurrence|production of a void is suppressed. In addition, the 2nd heat sink 3 is obtained by the process similar to the 1st heat sink 1 . In addition, the lead frame 4 is obtained by arbitrary processes, such as press-punching to the metal plate which consists of Cu, for example. In addition, after soldering the semiconductor device 2, the 2nd heat sink 3, and the lead frame 4, you may solder the semiconductor device 2 and the 1st heat sink 1 together.

Then, as shown in FIG. 6D , a mold 300 comprising an upper mold 301 and a lower mold 302 and having a cavity 303 corresponding to the outer shape of the sealing material 6 is prepared. Thereafter, the semiconductor device 2 to which the heat sinks 1 and 3 and the lead frame 4 are soldered into the cavity 303 is put. After this work is charged, a resin material such as an epoxy resin is injected into the cavity 303 from an injection port (not shown), cured by heating or the like, and the sealing material 6 is molded. After the sealing material 6 is molded, the work is released from the mold 300 and the tie bar of the lead frame 4 is removed by press punching or the like, whereby the semiconductor module S1 of the present embodiment can be manufactured.

According to this embodiment, the semiconductor device 2 having the FO package structure, the second heat sink 3 and the lead frame 4 are directly soldered to each other, so that the heat dissipation block 102 and the wire 103 are required. It becomes the semiconductor module S1 of the double-sided heat dissipation structure which does not do this. Therefore, compared with the conventional semiconductor module S100 provided with the heat dissipation block 102 and the wire 103, it becomes the semiconductor module S1 which became thin and low heat resistance.

(Second embodiment)

The semiconductor module S2 of the second embodiment will be described with reference to FIG. 7 . In FIG. 7, in another cross section, the wiring extended to the outside from the heat-transfer insulation board 7 mentioned later is shown with the broken line.

As shown in FIG. 7 , the semiconductor module S2 of the present embodiment is disposed between the first heat sink 1 and the semiconductor device 2 and between the semiconductor device 2 and the second heat sink 3 , respectively. It differs from the said 1st Embodiment in that a total of two heat-transfer insulation board|substrates 7 are arrange|positioned. In this embodiment, this difference is mainly demonstrated.

As shown in FIG. 7 , the heat transfer insulating substrate 7 has a structure in which an electrically conductive portion 71 , an insulating portion 72 , and a heat conductive portion 73 are laminated in this order. On one side of the heat transfer insulating substrate 7, an electrically conductive portion 71 is connected to the semiconductor device 2 and a bonding material 5 through a bonding material 5, and the heat conductive portion 73 is connected to a first heat sink via solder or the like not shown. 1) is connected. On the other side of the heat transfer insulating substrate 7, the electrically conductive portion 71 is connected to the semiconductor device 2 and the bonding material 5 through the bonding material 5, and the heat conductive portion 73 is connected to a second heat sink via solder or the like (not shown). (3) is connected.

In the electrothermal insulating substrate 7, the electrically conductive portion 71, the insulating portion 72, and the thermally conductive portion 73 are all made of a material with high thermal conductivity, and the thermal conductivity as a whole increases, while the electrically conductive portion 71 and The heat conduction unit 73 is electrically independent by the insulating unit 72 . By interposing the heat transfer insulating substrate 7, the semiconductor module S2 has a configuration in which the semiconductor device 2 is electrically independent from the first heat sink 1 and the second heat sink 3 and is thermally connected. has been In other words, in the semiconductor module S2 of the present embodiment, the first heat dissipating member is the first heat sink 1 and the heat transfer insulating substrate 7 , and the second heat dissipation member is the second heat sink 3 and the heat transfer insulating substrate. It can be said that it is comprised by (7), and the heat transfer insulation board 7 side is connected to the semiconductor device 2 also.

In the heat transfer insulating substrate 7 , for example, the electrically conductive portion 71 is mainly made of a metal material such as Cu, and the insulating portion 72 is mainly _{made of an insulating material such as Al 2} O ₃ (alumina) or AlN (aluminum nitride). In this case, the heat conduction portion 73 is mainly composed of a metal material such as Cu. As the thermal insulation substrate 7, a DBC (abbreviation of Direct Bonded Copper) substrate is used, for example.

Part of the electrically conductive portion 71 of the thermal insulation substrate 7 is a wiring connected to an external power supply or the like, or other wiring such as the lead frame 4 is connected, so that electrical exchange with the semiconductor element 20 is not possible. it is made possible

Also according to this embodiment, since the heat dissipation block 102 and the wire 103 are unnecessary, the same effect as that of the first embodiment is obtained.

In the semiconductor module S2, the semiconductor device 2 and the heat sinks 1 and 3 are insulated by the heat transfer insulating substrate 7, and when connected to an external cooler, etc., an insulating layer is provided between the cooler and the semiconductor module S2. It is a structure that does not need to be interposed separately. Therefore, the effect of increasing the reliability of this semiconductor module S2 when connected to an external cooler or the like is expected.

(Third embodiment)

The semiconductor module S3 of the third embodiment will be described with reference to FIGS. 8 to 10 .

In the semiconductor module S3 of the present embodiment, as shown in FIG. 8 , the semiconductor device 2 includes two semiconductor elements 20 and a relay member 29 , and in addition to the heat sinks 1 and 3 , , different from the first embodiment in that the structure further includes the heat sinks 8 and 9 . In this embodiment, this difference is mainly demonstrated.

In the present embodiment, the semiconductor device 2 includes a semiconductor element 20 having various electrodes, and a portion having a first wiring 26 and a second wiring 27 formed thereon (hereinafter referred to as "element for convenience"). Wealth”), it is made with two Moreover, the semiconductor device 2 has a structure with the relay member 29 penetrating in the thickness direction between these two element parts.

In the following description, in order to distinguish and understand the two semiconductor elements 20, as shown in FIG. 8, for convenience, the semiconductor elements 20 connected to the heat sinks 1 and 3 are " The first semiconductor element 201” is called, and the other is called “the second semiconductor element 202”. In addition, in this embodiment, the example in which these semiconductor elements 201 and 202 became the same structure is demonstrated.

A first wiring 26 and a plurality of second wirings 27 are formed in the first semiconductor element 201 and the second semiconductor element 202, for example, as shown in FIG. 9, 2 The element portions are arranged in alignment with their orientation. In addition, about the cross-sectional structure and connection with the heat sinks 1 and 3 in II-II shown by the dashed-dotted line in FIG. 9, it is the same as that of the semiconductor device 2 in said 1st Embodiment.

The relay member 29 has, for example, a first member 29a and a second member 29b as shown in FIG. 8 , and in the thickness direction of the semiconductor device 2 , includes a heat sink and The said heat sink is a member which electrically connects other members. The relay member 29 is made of, for example, a metal material such as Cu, and is formed by electrolytic plating or the like. Specifically, for example, a Cu pillar is disposed as the second member 29b between the two semiconductor elements 201 and 202 spaced apart, and these are covered with the sealing material 21 . In the example shown in FIG. 8 , this second member 29b has the same dimension in the thickness direction as the semiconductor elements 201 and 202 in which the first electrode 22 is formed, and after covering with the sealing material 21 , In this case, it is exposed together with the surface on the side where the 1st electrode 22 is formed among the semiconductor elements 201 and 202. Thereafter, when the redistribution layer 24 is formed, the relay member 29 can be formed by extending and installing the remaining first member 29a on the Cu pillar in the same manner as the redistribution layer 24 . have. In addition, the filler covered with the sealing material 21 should just be comprised with the material which has electroconductivity, and may be other than Cu. The relay member 29 is used in order to connect the 1st heat sink 1 and the 4th heat sink 9, for example, as shown in FIG. 8, The electric current between the 2 semiconductor elements 20 becomes a path In the example shown in FIG. 8 , the relay member 29 is disposed in a portion of the semiconductor device 2 exposed from the second heat sink 3 and located inside the outer periphery of the first heat sink 1 . do. An example of the planar layout of the relay member 29 will be described later.

As shown in FIG. 8, the 3rd heat sink 8 becomes a plate shape which has the upper surface 8a and the lower surface 8b which are in a front-back relationship similarly to the 1st heat sink 1, and metals, such as Cu. made up of materials. In the third heat sink 8, an element portion including the second semiconductor element 202 of the semiconductor device 2 is mounted on the upper surface 8a via a bonding material 5, and the lower surface 8b is formed by a sealing material ( 6) is exposed. The third heat sink 8 is disposed at a predetermined distance from the first heat sink 1 so as not to be directly connected to the first heat sink 1 , that is, not to be short-circuited. That is, the third heat sink 8 faces the back surface 2b facing the first heat sink 1 of the semiconductor device 2 , and the first heat sink 1 and the sealing material 6 are interposed therebetween. left and placed Also, the third heat sink 8 may be referred to as a “third heat dissipation member”.

As shown in Fig. 8, the fourth heat sink 9 is formed into a plate shape having one surface 9a and the other surface 9b in a front and rear relation, similar to the second heat sink 3, and is made of Cu or the like. It is made of metal material. The fourth heat sink 9 is arranged so that the other surface 9b faces the element portion including the second semiconductor element 202 in the semiconductor device 2 , and the bonding material 5 is interposed between the second semiconductor device 2 and the semiconductor device 2 . It is electrically connected to the element 202 . The fourth heat sink 9 has one surface 9a exposed from the sealing material 6 . The fourth heat sink 9 is directly connected to the second heat sink 3 so as not to be short-circuited, and is disposed with a predetermined or more spaced apart from the second heat sink 3 . That is, the fourth heat sink 9 faces the surface 2a facing the second heat sink 3 of the semiconductor device 2 , while the second heat sink 3 and the sealing material 6 are interposed therebetween. left and placed Also, the fourth heat sink 9 may be referred to as a “fourth heat dissipation member”.

Moreover, the element part provided with the 2nd semiconductor element 202 of the semiconductor device 2 is arrange|positioned inside the outer periphery of the upper surface 8a of the 3rd heat sink 8 . In addition, one end of the second wiring 27 of the element portion is disposed outside the outer edge of the other surface 9b of the fourth heat sink 9 , and similarly to the first embodiment, another cross section in FIG. 8 . in the lead frame 4 and soldered.

That is, the semiconductor module S3 of the present embodiment has a configuration in which two element portions having a double-sided heat dissipation structure are provided in the sealing material 6 , and these are electrically connected in series via a relay member 29 . Such a semiconductor module S3 may be referred to as a “2in1 structure”.

Next, an example of the planar layout of the four heat sinks 1, 3, 8, and 9 and the relay member 29 is demonstrated with reference to FIG.

For example, the semiconductor module S3 includes, as shown in FIG. 10 , heat sinks 1 and 3 in which a semiconductor device 2 including two semiconductor elements 20 is disposed oppositely and a heat sink ( 8, 9) is a configuration arranged between each. In addition, the semiconductor module S3 is further disposed between the first heat sink 1 and the third heat sink 8 , and is electrically connected to the second heat sink 3 via the relay member 29 . A heat sink 10 is provided.

In such a configuration, the semiconductor device 2 includes two relay members 291 and 292 . For example, in the first relay member 291 , as shown in FIG. 10 , the first heat sink 1 and the fourth heat sink 9 overlap when viewed from a direction normal to the one surface 3a. It is arrange|positioned at the part where there is, and each heat sink and the bonding material 5 are connected through it. The second relay member 292 is disposed at a portion where the second heat sink 3 and the fifth heat sink 10 overlap when viewed from the normal to the one surface 3a, and each heat sink and the bonding material ( 5) is connected. The semiconductor module S3 having such a layout is configured to appropriately change the current value by on/off control of each of the two semiconductor elements 20 .

Further, as shown in FIG. 10 , the plurality of lead frames 4 include a second wiring 27 (not shown) formed in two element portions, a second heat sink 3 and a fourth heat sink 9 . It is connected outside the outer perimeter of Therefore, even if it is a 2in1 structure like this embodiment, the heat dissipation block 102 and the wire 103 are unnecessary, and the thickness and low heat resistance are reduced compared with the prior art.

According to this embodiment, the effect similar to the said 1st Embodiment is acquired.

(Modified example of 3rd embodiment)

A semiconductor module S4 as a modification of the third embodiment will be described with reference to FIG. 11 . The semiconductor module S4 differs from the third embodiment in that the cross-sectional shape of the relay member 29 is changed as shown in FIG. 11 .

In the present modification, the relay member 29 has a shape having at least one step portion in cross-sectional view. In addition, as shown in FIG. 11 , the relay member 29 has a shape in which the second member 29b has a step portion, and the first member 29a is extended and installed to shift the position of the semiconductor device 2 . ), the portion exposed from the front surface 2a and the portion exposed from the back surface 2b of the semiconductor device 2 are offset. The relay member 29 is basically formed by the method described above in the third embodiment. For example, first, as the second member 29b , a part of the Cu pillar having a step portion is covered with the sealing material 21 . At this time, as in the third embodiment, the second member 29b has a surface on the side on which the first electrode 22 is formed among the semiconductor elements 201 and 202 and a surface on the same side as the sealing material 21 . is exposed from Then, in planar view, in the position offset from the part exposed from the back surface 2b among the said Cu pillars, the 1st member 29a is extended in the thickness direction by the method similar to the redistribution layer 24. As shown in FIG. Thereby, while the relay member 29 has a shape having a step portion, the portion exposed from the front surface 2a and the portion exposed from the rear surface 2b are offset. In addition, in this modification, the filler covered with the sealing material 21 may be columnar, and the shape (for example, L-shape in cross-section, etc.) may be sufficient as it has a stepped part, and it is arbitrary. In the case where the filler is the former, the relay member 29 is formed by forming a portion protruding from the periphery of the filler in plan view, and then extending the remainder in the thickness direction on the protruding portion. When the filler is the latter, the relay member 29 is a surface on the side on which the redistribution layer 24 of the filler is formed, and extends the remainder in the thickness direction at a position offset from the portion exposed on the back surface side of the sealing material 21 . is formed by By the above method, the relay member 29 formed so that the portion exposed from the front surface 2a of the semiconductor device 2 and the portion exposed from the rear surface 2b side are offset is a cross-sectional shape having at least one stepped portion. do. Thereby, the effect of not only thinning but reduction of the planar size is acquired.

Specifically, as in the third embodiment, when the cross-sectional shape of the relay member 29 is rectangular, in order to prevent short circuit between the relay member 29 and the second heat sink 3 , the first It is necessary to make the width dimension of the heat sink 1 larger than the 2nd heat sink 3 . In addition, as shown in FIG. 11, the space|interval between the 1st heat sink 1 and the 3rd heat sink 8 and the space|interval between the 2nd heat sink 3 and the 4th heat sink 9 are these From the viewpoint of preventing a short circuit between them, they all need to be a predetermined or greater X. Taking these into consideration, in the third embodiment, the width dimension of the first heat sink 1 is the second heat sink 3 and at least the distance X between the fourth heat sink 9 and the relay member 29 . The space for connecting to is added.

On the other hand, in the present modification, the relay member 29 is bent in the semiconductor device 2 , and the portion connected to the fourth heat sink 9 is connected to the first heat sink 1 . is offset from the part. As a result, as shown in Fig. 11, even if the relay member 29 has its one end connected to the portion protruding from the second heat sink 3 from the second heat sink 3 by the width of X, The other end side offset from the one end side may be connected to the fourth heat sink 9 .

Therefore, in this modified example, the width dimension of the 1st heat sink 1 can be made smaller than the said 3rd Embodiment. In addition, the fourth heat sink 9 to which the other end side of the relay member 29 is connected does not need to be excessively enlarged in width compared with the third heat sink 8 for the same reason, The width dimension can be made smaller than that of the third embodiment. Thereby, in the semiconductor module S4, the width dimension of the 1st heat sink 1 and the 4th heat sink 9 becomes small, so that the plane size becomes smaller than the said 3rd Embodiment.

According to this modified example, in addition to the effect similar to the said 3rd embodiment, it becomes the semiconductor module S4 from which the effect of being able to miniaturize also about a planar size is acquired.

(Fourth embodiment)

A semiconductor module according to a fourth embodiment will be described with reference to FIGS. 12 and 13 .

In FIG. 12 , a part of the semiconductor device 2 and the second heat sink 3 among the components of the semiconductor module according to the present embodiment in order to make it easier to see the stress relief portion 42 of the lead frame 4, which will be described later. A part of and the lead frame 4 are omitted. In Fig. 12, for convenience of explanation, the direction along the left and right directions of the paper is referred to as the X direction, the direction perpendicular to the paper plane is referred to as the Y direction, and the direction perpendicular to the X direction in the paper plane is referred to as the Z direction. , and their directions are indicated by arrows or the like. This also applies to FIG. 16, which will be described later.

In FIG. 13 , for the same reason as in FIG. 12 , members other than a part of the semiconductor device 2 , the lead frame 4 and the bonding material 5 are omitted, and X, Y, Each direction of Z is indicated by an arrow or the like. This also applies to FIGS. 14, 15, and 17, which will be described later.

In the semiconductor module according to the present embodiment, for example, as shown in FIG. 12 , a lead frame 4 connected to the second wiring 27 of the semiconductor device 2 via a bonding material 5 is stress relieved. It differs from the said 1st Embodiment in the point of the structure provided with the part 42. As shown in FIG. In this embodiment, this difference is mainly demonstrated.

Hereinafter, for convenience of explanation, as shown in FIG. 12 , an end of the lead frame 4 on the side connected to the second wiring 27 is referred to as a “first end 4a”, and an end on the opposite side thereof. is referred to as a “second end 4b”. In addition, along the lead frame 4, the direction which goes from the 1st edge part 4a to the 2nd edge part 4b is called "extension installation direction."

In the present embodiment, the lead frame 4 relieves stress generated on the first end 4a side of the lead frame 4 in the manufacturing process, and connects the second wiring 27 and the lead frame 4 to each other. A stress relief portion 42 for reducing the load applied to the bonding material 5 to be connected is provided. Specifically, in the cooling process after connecting the lead frame 4 to the second wiring 27 via the bonding material 5 during the process of manufacturing the semiconductor module, due to thermal contraction of the lead frame 4, A stress is generated at one end 4a, and a load is applied to the bonding material 5 by the stress. Since cracks may occur in the bonding material 5 by this load, it is preferable to reduce the stress generated on the side of the first end 4a from the viewpoint of securing bonding reliability. That is, by concentrating the stress on the stress relief portion 42 and elastically or plastically deforming the portion, the stress and thus the load on the bonding material 5 are reduced, and cracks are prevented from occurring in the bonding material 5 . .

The lead frame 4 is, for example, as shown in Fig. 12, has a shape having a boundary portion 41 between the first end 4a and the second end 4b, which is a boundary portion in which the direction of extension and installation is changed. . Specifically, as for the lead frame 4, for example, the part including the 1st end part 4a and the part containing the 2nd end part 4b follow the X direction, and a part in between is Z direction. It can be shaped according to In this case, the extension direction of the lead frame 4 is changed from the X direction to the Z direction, and this boundary is the boundary portion 41 .

Further, in the lead frame 4, a portion between the first end portion 4a and the boundary portion 41 is a stress relief portion 42 different from the portion in which the extension direction is different. Specifically, for example, as shown in FIG. 13 , in the lead frame 4 , the extension direction of the predetermined portion including the first end 4a is along the X direction, but the lead frame 4 reaches the boundary portion 41 . On the way, it is the stress relief part 42 whose extension installation direction changed to the Y-direction side. In other words, in the present embodiment, the lead frame 4 is provided with the stress relief portion 42, so that the portion from the first end portion 4a to the boundary portion 41 is substantially L-shaped. Further, the lead frame 4 has a flat shape in which the portion from the first end 4a to the boundary portion 41 and the portion from the second end 4b to the boundary portion 41 are not arranged in a straight line in plan view. is made of That is, the lead frame 4 has a configuration in which the portion from the first end 4a to the boundary portion 41 has a shape different from that of a straight line.

When the portion from the first end portion 4a to the boundary portion 41 is straight, the lead frame 4 is connected to the semiconductor device 2 with the bonding material 5 in the cooling step. It heat-shrinks along the extension installation direction, and the stress shown by the outline arrow of FIG. 14 generate|occur|produces. When this thermal stress is large, a crack may generate|occur|produce in the bonding material 5, and there exists a possibility that the reliability of a semiconductor module may fall. The stress relieving part 42 serves to relieve the thermal stress applied to the bonding material 5 by changing the direction of its extension in the portion from the first end portion 4a to the boundary portion 41 . In addition, the stress relaxation part 42 is formed by giving press punching to the board|plate material which consists of a metal material, for example.

According to the present embodiment, in addition to the effects of the first embodiment, the occurrence of cracks in the bonding material 5 connecting the second wiring 27 of the semiconductor device 2 and the lead frame 4 is suppressed, and further It becomes a semiconductor module in which the effect of improving reliability is also obtained.

(Modified example of 4th embodiment)

The stress relief portion 42 may have any structure capable of relieving the stress generated on the side of the first end 4a, and is not limited to the above example. As shown in FIG. 15, for example, the stress relaxation part 42 may be made into a substantially U-shape on the XY plane when viewed from the top.

In addition, as shown, for example in FIG. 16, the stress relaxation part 42 may be made into the substantially U-shaped shape deformed in the Z direction in cross-sectional view. In this case, as shown in FIG. 17, for example, the lead frame 4 is the part from the 1st edge part 4a to the boundary part 41, and the boundary part 41 from the 2nd edge part 4b, as shown in FIG. ) to be configured to be located on the same straight line. However, since the extension direction of the lead frame 4 changes on the way from the boundary portion 41 to the first end 4a by the stress relaxation portion 42 , in the cooling step after connection to the semiconductor device 2 , Thermal stress generated in the first end 4a is reduced.

In addition, from the viewpoint of processing precision, the stress relief portion 42 is preferably formed so as to be positioned on the same plane as the portion from the first end portion 4a to the boundary portion 41 . In addition, if it is the purpose of concentrating the stress on the stress relieving part 42 and elastically or plastically deforming it at that location, as described above, the stress relieving part 42 is not only the orientation of the extension installation direction of the lead frame 4 but also the , the width or thickness may be partially different from that of a different portion. In other words, the stress relief portion 42 is in a state from the first end 4a to the boundary portion 41 in which at least one of the thickness, width, and extension direction of the lead frame 4 is different from that of the other portions. is the area to be In addition, the width of the lead frame 4 here means the dimension in the direction orthogonal to the extension installation direction.

Also in this modified example, the effect similar to the said 4th embodiment is acquired.

(5th embodiment)

A semiconductor module according to a fifth embodiment will be described with reference to FIGS. 18 to 20 .

In FIG. 18, in order to make it easy to see the recessed part 31 formed in the 2nd heat sink 3 mentioned later, while the sealing material 6 is abbreviate|omitted, the outline is shown by the double-dotted line.

In the semiconductor module of this embodiment, for example, as shown in FIG. 18 , a recess is formed on the other surface 3b of the second heat sink 3 connected to the first wiring 26 of the semiconductor device 2 . It differs from the said 1st Embodiment in that (31) is formed. In this embodiment, this difference is mainly demonstrated.

In the present embodiment, the second heat sink 3 is recessed toward one surface 3a in a region different from the region joined to the first wiring 26 of the semiconductor device 2 among the other surfaces 3b. The part 31 is formed, and it has a shape which can ensure the clearance gap between the semiconductor device 2 and the 2nd heat sink 3 . Specifically, as shown in FIG. 19 , the second heat sink 3 has a junction region 3ba on which the other surface 3b is bonded to the semiconductor device 2, and a surface different from the junction region 3ba. 3b) is formed by a non-bonding region 3bb, which is a region on the outer side, and at least a part of the non-bonding region 3bb becomes a recessed portion 31 .

The recessed portion 31 is formed from, for example, from the end of the junction vicinity region 3bc, if a part of the non-bonding region 3bb located in the vicinity of the junction region 3ba is referred to as the junction vicinity region 3bc. It becomes a tapered shape inclined toward the outer side of the other surface 3b. The concave portion 31 may be formed by any processing method such as pressing, cutting, casting, or etching, for example. For example, as shown in FIG. 20 , the concave portion 31 has a surface formed by the concave portion 31 as an inclined surface, and the acute angle of the angle formed between the surface formed by the bonding region 3ba and the inclined surface is a taper angle. When θ is, the taper angle θ is preferably 45° or less. This is to secure the region of the second heat sink 3 for diffusing heat from the semiconductor device 2 to the outside, and to prevent the heat dissipation of the semiconductor device 2 from being deteriorated.

The concave portion 31 is formed between the semiconductor device 2 on the outer side of the other surface 3b of the non-junction region 3bb and the semiconductor device 2 in the region 3bc near the junction where the gap D2 is formed. It has a shape larger than the gap D1. This is to make it easier for the sealing material to flow into the gap between the semiconductor device 2 and the second heat sink 3 when the sealing material 6 is formed, so as to ensure the filling properties of the sealing material.

For example, when the entire other surface 3b is a flat surface, the thickness of the bonding material 5 is 100 µm or less, and when a sealing material containing a filler is introduced, the filler is formed between the semiconductor device 2 and the second surface. It becomes difficult to enter the clearance gap between the heat sinks 3, and there exists a possibility that a void may generate|occur|produce. When such voids are generated in the sealing material 6, when the cycle of heat generation/cooling in the semiconductor module is repeated, the action of relieving the thermal stress in the bonding material 5 is weakened, and cracks may occur. It is not preferable from the viewpoint of securing reliability.

In contrast, in the present embodiment, the second heat sink 3 has a recess 31 on the other surface 3b, and the gap between the semiconductor device 2 and the second heat sink 3 is adjacent to the junction. It has a structure in which it becomes wider as it goes outward from the area|region 3bc. Therefore, even when the thickness of the bonding material 5 is thin and a sealing material containing a filler is used, the sealing material easily flows into the gap between the semiconductor device 2 and the second heat sink 3, so that the filling is not possible. It improves, and generation|occurrence|production of the void in the sealing material 6 is suppressed.

According to this embodiment, in addition to the effects of the first embodiment, the filling properties of the sealing material 6 in the gap between the semiconductor device 2 and the second heat sink 3 are further improved, and the sealing material 6 is further improved. It becomes a semiconductor module from which the effect which the void generation|occurrence|production is suppressed and the reliability further improves is obtained.

(Modified example of 5th embodiment)

When the concave portion 31 in the second heat sink 3 forms the sealing material 6 , the resin material constituting the sealing material 6 is disposed between the semiconductor device 2 and the second heat sink 3 . What is necessary is just a shape filled in a clearance gap, and it is not limited to said tapered shape. The concave portion 31 may have a stepped shape, for example, as shown in FIG. 21 . Also in this case, the gap with the semiconductor device 2 in the non-junction region 3bb of the other surface 3b of the second heat sink 3 is the junction vicinity region of the outer edge portion of the other surface 3b. (3bc) is greater. Therefore, the filling property of the sealing material in the clearance gap between the semiconductor device 2 and the 2nd heat sink 3 can be ensured.

Also with this modified example, the same effect as that of the said 5th embodiment is acquired.

(Sixth embodiment)

A semiconductor module according to a sixth embodiment will be described with reference to FIG. 22 .

In the semiconductor module of this embodiment, for example, as shown in FIG. 22 , roughening parts 261 and 271 in which a part of the first wiring 26 and the second wiring 27 in the semiconductor device 2 are harmonized. It is different from the first embodiment in that it is In this embodiment, this difference is mainly demonstrated.

In this embodiment, as shown in FIG. 22, the 1st wiring 26 becomes the roughening part 261 in which the part exposed from the insulating layer 25 which comprises the redistribution layer 24 was roughened. In this embodiment, the 2nd wiring 27 becomes the roughening part 271 in which the part covered with the insulating layer 25, and the part exposed from the insulating layer 25 were roughened. The roughening parts 261 and 271 are roughened by a post-processing process such as laser beam irradiation after forming wiring by the roughening plating method described in Japanese Patent Application Laid-Open No. 2019-181710, for example, or a normal plating forming process. The method and the like may be formed by any method.

Compared with the case where the roughening parts 261 and 271 are not roughened, the specific surface area in the interface with the bonding material 5 or the insulating layer 25 is enlarged, and adhesiveness with the material in contact is improved, A semiconductor module serves to improve the reliability of

In addition, the "roughening part" here means that calculated average surface roughness Ra (unit: micrometer) set by Japanese Industrial Standards (JIS) becomes 0.3 or more, for example.

According to the present embodiment, in addition to the effects of the first embodiment, the adhesiveness of the second wiring 27 in the redistribution layer 24 of the semiconductor device 2 and the bonding between the wirings 26 and 27 and the bonding material 5 . It becomes a semiconductor module from which adhesiveness is improved and the effect of further improving bonding reliability is acquired.

(Seventh embodiment)

A semiconductor module according to a seventh embodiment will be described with reference to FIG. 23 .

In FIG. 23 , in order to make it easier to see the cover layer 43 of the lead frame 4 , which will be described later, a part of the semiconductor device 2 and the second heat sink 3 among the components of the semiconductor module according to the present embodiment are shown. A part and the thing other than the lead frame 4 are abbreviate|omitted.

The semiconductor module of the present embodiment differs from the first embodiment in that the lead frame 4 is provided with a cover layer 43 . In this embodiment, this difference is mainly demonstrated.

In this embodiment, the lead frame 4 is provided with a cover layer 43 covering a partial area on the side of the first end 4a, that is, a predetermined area including a portion connected to the second wiring 27 . is made up of When the cover layer 43 connects the lead frame 4 to the second wiring 27 by means of the bonding material 5, the molten bonding material 5 is not intended for, for example, the second heat sink 3 side. It protrudes into an unintended area, and is formed to prevent short circuit between the lead frame 4 and an unintended area from occurring. For example, when the bonding material 5 is applied to the semiconductor device 2 and the molten bonding material 5 protrudes toward the second heat sink 3 side, the protruding bonding material 5 becomes the second heat. A direct connection between the sink 3 and the lead frame 4 may cause a short circuit. The cover layer 43 is configured to suppress the wet diffusion of the bonding material 5 to such an unintended area.

Specifically, the cover layer 43 is made of any material whose wettability of the bonding material 5 is higher than that of the lead frame 4, and thus serves to control the direction in which the molten bonding material 5 is wet and diffused. For example, when the lead frame 4 is made of Cu and the bonding material 5 is solder, the cover layer 43 is, for example, Au (gold), Ag (silver), Sn (tin) or It is constituted by these alloys or the like. The cover layer 43 is formed by any method, such as vapor deposition or sputtering, for example.

A portion of the second wiring 27 exposed from the insulating layer is referred to as an exposed portion, a portion of the lead frame 4 facing the exposed portion of the second wiring 27 is referred to as an opposing portion, and the cover layer 43 is referred to as an opposing portion. The predetermined area on the side of the second end 4b is continuously covered from the . Thereby, when the molten bonding material 5 comes into contact with the cover layer 43 , the bonding material 5 wet and diffuses along the cover layer 43 toward the second end 4b side, so that the second heat sink 3 . Protrusion to the side is suppressed.

According to this embodiment, in addition to the effects of the first embodiment, the semiconductor module has a structure in which the bonding material 5 is prevented from flowing in an unintended direction in the manufacturing process and the effect of suppressing insulation failure is obtained.

In addition, in the above, after apply|coating the bonding material 5 to the semiconductor device 2, the manufacturing process of connecting the lead frame 4 provided with the cover layer 43 was mentioned as an example and demonstrated. However, the manufacturing process is not limited to this, and a bonding material 5 is applied to the back surface 2b of the semiconductor device 2 and the first wiring 26 and the second wiring 27 in advance, and the cover layer 43 is formed. ) may be connected to the semiconductor device 2 . In this case, the semiconductor device 2, the 1st heat sink 1, the 2nd heat sink 3, and the lead frame 4 can be joined collectively, and the simplification of a manufacturing process becomes possible.

In addition, the lead frame 4 should just be a structure which can suppress the wet-diffusion of the bonding material 5, and the structure which does not have the cover layer 43 may be sufficient. For example, in the lead frame 4, the cover layer 43 is not formed, and the wettability of the area other than the area corresponding to the cover layer 43 is made to a state in which the wettability is worse than that of other areas, so that the wetting and diffusion of the bonding material 5 is reduced. The structure may be suppressed. As a means for partially worsening the wettability of the bonding material 5 in the lead frame 4, laser irradiation etc. are mentioned, for example. That is, the lead frame 4 has a region where the wettability of the bonding material 5 is relatively high and a region where the wettability of the bonding material 5 is relatively high. ) may be configured to extend to the side. This is also the same in the modified example described below.

(Modified example of 7th embodiment)

For example, as shown in FIG. 24 , the lead frame 4 is on the second end 4b side of the opposing portion facing the second wiring 27 , and a groove portion is formed at a predetermined distance from the opposing portion. (44) may be formed. In this case, the cover layer 43 is formed so as to cover the region from at least the opposite portion of the lead frame 4 to the groove portion 44 .

For example, as shown in Fig. 24, the groove portion 44 absorbs the surplus amount of the bonding material 5 applied to the second wiring 27 when the bonding material 5 is applied to an unintended area. ) to prevent flow. The groove portion 44 is made into a substantially V-shaped groove by any processing method such as V-grooving or half-etching, for example, but the shape of the bonding material 5 in which excess material flows in is sufficient. Depth and the like are arbitrary. If the groove portion 44 is too far away from the opposing portion, it will be difficult to absorb the excess of the bonding material 5. For example, the groove portion 44 is on the first end 4a side rather than the boundary portion 41, and is formed within a predetermined range from the opposite portion. .

According to this modification, even when the surplus bonding material 5 is applied to the semiconductor device 2, the surplus is absorbed in the groove portion 44, and the protrusion of the bonding material 5 into an unintended area is suppressed. This provides a semiconductor module having a structure that can further enhance the effects of the seventh embodiment.

(Eighth embodiment)

A semiconductor module according to an eighth embodiment will be described with reference to FIGS. 25 to 27 .

In FIG. 25, in order to make the protrusion part 2c mentioned later easy to see, a part of 1st heat sink 1 and the sealing material 6 are abbreviate|omitted.

In the semiconductor module of this embodiment, for example, as shown in FIG. 25 , the protrusion 2c is formed in the semiconductor device 2 , and the semiconductor device 2 and the second heat sink 3 are not intended. It differs from the said 1st Embodiment in that it is a structure which does not come into contact with a non-contact site|part. In this embodiment, this difference is mainly demonstrated.

In the semiconductor device 2 in this embodiment, for example, as shown in FIG. 26 , a plurality of projections 2c are formed in a region near the outer edge of the surface 2a on the side of the first wiring 26 . . This is when the end of the semiconductor device 2 is bent toward the second heat sink 3 side in the manufacturing process, the front surface 2a of the semiconductor device 2 and the other surface of the second heat sink 3 ( This is to prevent the filling failure of the sealing material 6 due to the end portions of 3b) being in extensive contact and blocking the gaps therebetween.

That is, the protrusion 2c is formed in the vicinity of an outer portion of the semiconductor device 2 that has a large fluctuation due to warping, and when the semiconductor device 2 is bent, the second heat sink is earlier than the surface 2a of the semiconductor device 2 . It is a part in contact with the other surface (3b) of (3). Thereby, the protrusion 2c secures a gap between the semiconductor device 2 and the second heat sink 3 , helps the sealing material to flow into the gap, and prevents voids from occurring in the sealing material 6 . plays a role

The projection 2c is made of any material such as a resin material or a metal material. When the projection 2c is made of a resin material, it can be formed by any wet film forming method such as potting, for example. When the projection 2c is made of a metal material, it can be formed by any method such as electrolytic plating, for example. In the latter case, the projection 2c has a configuration that is electrically independent from a circuit portion of the semiconductor device 2 that transmits an electrical signal such as a high-frequency signal.

In addition, the protrusion part 2c may only contact the 2nd heat sink 3, and may be joined to the 2nd heat sink 3 . For example, the protrusion 2c may have a structure containing solder and may be joined to the second heat sink 3 , and in this case, a structure in which solder is joined to the semiconductor device 2 side may be provided. Thereby, the effect which further improves the heat dissipation property of the semiconductor device 2 is also anticipated.

The protrusions 2c are, for example, in a columnar shape, and as shown in FIG. 26 , a plurality of regions in the semiconductor device 2 with a large curvature are arranged in a region capable of contacting the second heat sink 3 . do. Specifically, it is a predetermined region near the outer periphery of the surface 2a of the semiconductor device 2 , and a region facing the other surface 3b of the second heat sink 3 is referred to as an outer edge region 2aa, (2c) is formed in the outer edge region 2aa. The protrusions 2c are interspersed, for example, in the outer edge region 2aa outside the first wiring 26 , and are arranged so as to surround the first wiring 26 .

In addition, the protrusion 2c suppresses contact between the surface 2a of the semiconductor device 2 and the other surface 3b of the second heat sink 3 due to the bending of the semiconductor device 2, thereby preventing the inflow of the sealing material. As long as it does not interfere, it is not limited to the example of said arrangement|positioning and shape. For example, as shown in FIG. 27, the protrusion part 2c may be made into a wall shape, it may be made into any other arbitrary shape, and arrangement|positioning may be changed suitably in the outer edge area|region 2aa.

According to this embodiment, in addition to the effects of the first embodiment, even if warpage of the semiconductor device 2 occurs in the manufacturing process, the gap between the semiconductor device 2 and the second heat sink 3 is secured, and the sealing material is It becomes a semiconductor module from which the effect of suppressing generation|occurrence|production of the void in (6) and improving reliability more is acquired.

(Other embodiment)

Although this indication was described based on an Example, it is understood that this indication is not limited to the said Example or structure. The present disclosure includes various modifications and variations within an equivalent range. In addition, various combinations and forms, and further, other combinations and forms including only one element, more, or less thereof are also included in the scope and spirit of the present disclosure.

(1) For example, in the third embodiment and its modifications, as shown in FIG. 28 , a heat transfer insulating substrate is disposed between the semiconductor device 2 and each heat sink 1 , 3 , 8 , 9 . (7) may be arranged. In this case, the relay member 29 is electrically connected to the electrically conductive portion 71 of the heat transfer insulating substrate 7 , and is electrically independent from the respective heat sinks 1 , 3 , 8 and 9 , but thermally. is connected

(2) In the third embodiment and its modifications, a 2in1 structure in which two element portions are covered with one sealing material 6 has been described. However, the number of element portions may be 3 or more. Even in this case, it becomes a semiconductor module from which the effect of thickness reduction and low heat resistance is acquired compared with the prior art.

(3) In each of the above embodiments, an example has been described in which the first wiring 26 and the second wiring 27 of the semiconductor device 2 are shaped to protrude outward from the outer surface of the insulating layer 25 . , as shown in FIG. 29 , the insulating layer 25 may have a shape concave inward than the outer surface thereof.

(4) In the second embodiment, the first heat dissipation member comprises the first heat sink 1 and the heat transfer insulating substrate 7 , and the second heat dissipation member comprises the second heat sink 3 and the heat transfer insulating substrate 7 ), the examples each constituted were described. However, as shown in FIG. 30 , the first heat dissipating member and the second heat dissipating member may be constituted by only the heat transfer insulating substrate 7 .

In addition, similarly to the other modified example of the said 3rd Embodiment demonstrated in said (1), as shown in FIG. 31, the 1st - 4th heat dissipation member may be comprised only with the heat transfer insulating substrate 7 . In this case, the semiconductor module has a structure in which the first and third heat dissipating members are constituted only by one heat transfer insulating substrate 7 and the second and fourth heat dissipation members are constituted by only one heat transfer insulating substrate 7 . This heat-conducting insulating substrate 7 has a configuration in which the portion connected to the semiconductor element 201 and the portion connected to the semiconductor element 202 of the electrically conductive portion 71 are electrically independent, but the heat-conducting portion 73 is patterned. don't have to be

(5) Although the first and second embodiments described above have been described on the assumption that the semiconductor element 20 in the semiconductor device 2 has a so-called vertical configuration in which a current in the thickness direction is generated, the semiconductor element 20 ) is not limited thereto. For example, the semiconductor element 20 may have a configuration in which the first electrode 22 , the second electrode 23 , and the third electrode are formed in the same plane.

(6) In the first embodiment, the second heat sink 3 has one surface 3a and one surface 3a at a position outside the region to be joined to the semiconductor device 2, for example, as shown in FIG. 32 . The through-hole 32 which connects the other surface 3b may be formed. The through hole 32 is filled with a resin material constituting the sealing material 6 (hereinafter referred to as "sealing material") between the semiconductor device 2 and the second heat sink 3 when the sealing material 6 is molded. It serves as a charging path for

Specifically, the through hole 32 is, for example, as shown in FIG. 33 , the first heat sink 1 , the semiconductor device 2 , the second heat sink 3 , and the lead frame 4 . It becomes a path|route through which the said sealing material flows in when the sealing material is injected|thrown-in after setting the workpiece|work formed by joining in the metal mold|die 310. In addition, the work is arranged so that one surface 3a of the second heat sink 3 does not come into contact with the inner wall of the mold 310 . Then, the sealing material flows from one surface 3a to the other surface 3b to fill the gap between the semiconductor device 2 and the second heat sink 3 , as indicated by an arrow in FIG. 33 . Moreover, the semiconductor module shown in FIG. 32 can be manufactured by exposing the one surface 3a of the 2nd heat sink 3 by grinding, for example after hardening of a sealing material. Thereby, similarly to the said 5th Embodiment, it becomes a semiconductor module of the structure which the filling property of the sealing material 6 was improved.

In addition, the through hole 32 may be formed in the 2nd heat sink 3 in the said 5th Embodiment and its modification, for example, as shown in FIG. 34. As shown in FIG. In this case, the through hole 32 is formed in the concave portion 31 of the second heat sink 3 , and together with the concave portion 31 , a gap between the semiconductor device 2 and the second heat sink 3 . It plays a role of improving the filling property of the sealing material 6 in.

In addition, the through hole 32 may be formed in the 2nd heat sink 3 in the said 3rd Embodiment and its modification. In this case, when the through hole corresponding to the through hole 32 is formed in the 4th heat sink 9, since the filling property of the sealing material 6 will improve more, it is preferable.

(7) When a part or all of the second heat dissipation member and the fourth heat dissipation member are constituted by the heat transfer insulating substrate 7, the heat transfer insulating substrate 7 is, for example, as shown in Fig. 35, an electrically conductive part ( A step portion 74 may be formed in the outer peripheral portion of the 71 . Thereby, the sealing material 6 becomes easy to enter into the clearance gap between the heat transfer insulating substrate 7 and the surface 2a of the semiconductor device 2, and it becomes a semiconductor module of the structure in which the filling property of the sealing material 6 was improved.

Claims (22)

It is a semiconductor module,
a first heat dissipation member (1, 7);
A semiconductor element (20), a sealing material (21) covering the periphery thereof, and first and second wirings (26) and second wirings (27) electrically connected to the semiconductor element are provided; a semiconductor device 2 having a redistribution layer 24 formed thereon and mounted on the first heat dissipation member;
a second heat dissipation member (3, 7) disposed on the semiconductor device;
a lead frame (4) electrically connected to the semiconductor device via a bonding material (5);
a sealing material (6) covering a part of the first heat dissipation member, a part of the semiconductor device, and a part of the second heat dissipation member;
a part of the semiconductor device protrudes from the periphery of the other surface 3b of the second heat dissipation member facing the semiconductor device,
the second wiring has one end extending to a portion protruding from the periphery of the other surface of the semiconductor device, and one end of the second wiring is electrically connected to the lead frame via the bonding material. . According to claim 1,
The semiconductor device is disposed inside an outer periphery of an upper surface (1a) facing the semiconductor device of the first heat dissipation member. 3. The method of claim 1 or 2,
The first heat dissipating member and the second heat dissipating member are heat sinks (1, 3), respectively, and at least one of which constitutes a conductive path. 3. The method of claim 1 or 2,
The first heat dissipating member and the second heat dissipating member are each a heat transfer insulating substrate (7), a semiconductor module. 3. The method of claim 1 or 2,
The first heat dissipating member and the second heat dissipating member are each laminated with heat sinks 1 and 3 and a heat transfer insulating substrate 7, and the heat transfer insulating substrate is connected to the semiconductor device via the bonding material. , semiconductor modules. 6. The method according to any one of claims 1 to 5,
Assuming that the semiconductor element is a first semiconductor element 201, the semiconductor device has a relay member 29 and a second semiconductor element 202 in a portion protruding from the outer edge of the other surface,
It further includes a third heat dissipation member (7, 8) and a fourth heat dissipation member (7, 9) disposed to face each other with the second semiconductor element interposed therebetween,
If a surface of the semiconductor device facing the second heat dissipation member is referred to as a front surface 2a and the opposite surface is referred to as a back surface 2b,
The third heat dissipation member is disposed to face the back surface and to have the first heat dissipation member and the sealing material interposed therebetween,
The fourth heat dissipation member faces the surface and is disposed with the second heat dissipation member and the sealing material interposed therebetween,
At least one of the relay members extends in a direction connecting the front surface and the back surface, and one end thereof is electrically connected to the first heat dissipation member through a bonding material, and the other end thereof is connected to the fourth heat dissipation member through a bonding material. A semiconductor module electrically connected to the member. 7. The method of claim 6,
In the relay member, when viewed in a direction normal to the surface, a portion exposed from the redistribution layer on the front surface and a portion exposed from the sealing material on the back surface are offset from each other. 8. The method of claim 7,
The relay member has a cross-sectional shape having at least one step portion in a direction connecting the front surface and the rear surface. 9. The method according to any one of claims 6 to 8,
The third heat dissipating member and the fourth heat dissipating member are heat sinks (8, 9), respectively. 9. The method according to any one of claims 6 to 8,
The third heat dissipating member and the fourth heat dissipating member are each a heat transfer insulating substrate (7), a semiconductor module. 11. The method according to any one of claims 1 to 10,
Assuming that, among both ends of the lead frame, an end connected to the second wiring via the bonding material is referred to as a first end 4a, and an end opposite to the first end is referred to as a second end 4b, A direction from the first end to the second end is referred to as an extension installation direction,
The lead frame has a boundary portion 41 between the first end and the second end, which is a boundary portion in which the orientation of the extension direction is changed, and a portion between the first end and the boundary portion is , wherein at least one of a thickness, a width, and an orientation of the extension installation direction of the lead frame is a stress relief portion (42) different from that of other portions of the lead frame. 12. The method of claim 11,
A portion of the lead frame between the first end and the boundary portion has a flat shape positioned on the same plane,
and wherein the stress relief portion has an orientation in the extension installation direction different from that of the other portions. 3. The method of claim 1 or 2,
A surface of the second heat dissipating member opposite to the other surface is referred to as a surface 3a, and a region of the other surface of the second heat dissipating member bonded to the semiconductor device and the bonding material through the bonding material is referred to as a bonding area 3ba. and the remainder is referred to as a non-bonding region 3bb, and a part of the non-bonding region located in the vicinity of the junction region is referred to as a junction vicinity region 3bc,
The second heat dissipation member is a heat sink, and at least a part of the non-bonding region is a concave portion 31 concave from the other surface toward the one surface,
and a gap (D2) with the semiconductor device on the outer side of the other surface of the non-junction region is larger than a gap (D1) with the semiconductor device on the region near the junction. 14. The method of claim 13,
The concave portion has a tapered shape inclined from a region near the junction toward an outer side of the other surface. 15. The method of claim 14,
If the surface of the concave portion is referred to as an inclined surface, and an acute angle among angles between the inclined surface and a surface formed by the junction region is referred to as a taper angle (θ), the taper angle is 45° or less. 14. The method of claim 13,
The concave portion includes an outer periphery of the other surface and has a stepped shape from an outer side of the other surface toward the region near the junction. 17. The method according to any one of claims 1 to 16,
A portion of the first wiring exposed from the insulating layer 25 constituting the redistribution layer is a roughened portion 261,
A portion covered by the insulating layer and a portion exposed from the insulating layer among the second wirings are a roughened portion (271). 18. The method according to any one of claims 1 to 17,
Assuming that, among both ends of the lead frame, an end connected to the second wiring via the bonding material is referred to as a first end 4a, and an end opposite to the first end is referred to as a second end 4b,
A part of the lead frame on the side of the first end is a region in which the wettability of the bonding material is higher than that of other regions,
The lead frame is connected to the semiconductor device through the high wettability region. 19. The method of claim 18,
A portion of the second wiring exposed from the insulating layer 25 constituting the redistribution layer is referred to as an exposed portion,
A groove portion 44 concave to the opposite side to the semiconductor device is formed in a portion of the lead frame on the second end side of the opposite portion, which is a portion facing the exposed portion,
and the region from the groove portion and the opposing portion to the groove portion is a region having a higher wettability than other regions of the lead frame. 20. The method according to any one of claims 1 to 12, 16 to 19,
A surface of the outer surface of the semiconductor device facing the second heat dissipating member is referred to as a surface 2a, and a portion near the outer surface of the surface and facing the other surface of the second heat dissipating member is referred to as an outer edge region ( 2aa),
The semiconductor module includes, in the outer edge region, a protrusion (2c) for suppressing contact between the other surface of the second heat dissipation member and the semiconductor device. 21. The method of claim 20,
The said protrusion part becomes a structure containing solder, and is joined to the said other surface of the said 2nd heat dissipation member. A semiconductor device used for a semiconductor module having a double-sided heat dissipation structure having a first heat dissipation member (1, 7) and a second heat dissipation member (3, 7), and disposed between the first heat dissipation member and the second heat dissipation member,
a semiconductor device 20;
a sealing material 21 surrounding the semiconductor element;
a redistribution layer (24) formed on the semiconductor element and the sealing material;
The redistribution layer has an insulating layer 25 and a first wiring 26 and a second wiring 27 formed in the insulating layer and having one end connected to the semiconductor element,
The first wiring is disposed inside the outer periphery of the semiconductor device when viewed from the top,
and wherein the second wiring is provided so that the other end thereof extends to a region outside the outer periphery of the semiconductor element when viewed from the top.

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