JP2011165793A - Semiconductor device and method of manufacturing the same, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device that has a semiconductor chip mounted on a wiring board and sealed with resin. <P>SOLUTION: The semiconductor chip 2 mounted on the wiring board 20 via a heat dissipating member 10 and a plurality of wires (conductive members) 3 electrically connecting the semiconductor chip 2 and wiring board 20 to each other are sealed with the sealing resin (sealing body) 4. Further, the heat dissipating member 10 includes a chip mounting portion 10a where the semiconductor chip 2 is mounted and a heat dissipating lead 10b led out of the chip mounting portion 10a toward respective corner portions of the wiring board 20 and further led out to a reverse surface side located on the opposite side from a chip mounting surface of the wiring board 20. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device in which a semiconductor chip is mounted on a wiring board and the semiconductor chip is resin-sealed.

  Japanese Patent Laying-Open No. 2006-190771 (Patent Document 1) discloses a plating film (thermal via) formed on an inner wall of a through hole in a region where a semiconductor chip is mounted on a wiring board, and an improvement in heat conduction connected thereto. A semiconductor device in which thermal bumps are disposed is disclosed.

  Japanese Patent Application Laid-Open No. 8-78806 (Patent Document 2) discloses a semiconductor device in which a semiconductor chip is mounted on a wiring board (multilayer ceramic substrate) via a metal plate.

JP 2006-190771 A JP-A-8-78806

  As a package structure of a semiconductor device, there is a semiconductor device in which a semiconductor chip is mounted on a wiring board. This type of semiconductor device has an advantage that the planar dimensions of the semiconductor device can be reduced by arranging a plurality of external terminals on the back side of the wiring board.

  As a method of electrically connecting a wiring board and a semiconductor chip mounted on the wiring board, a plurality of electrodes of the semiconductor chip and a plurality of terminals of the wiring board are electrically connected via a plurality of metal wires (wires). There is a wire bonding method to connect to. As another electrical connection method, the main surface side on which the plurality of electrodes of the semiconductor chip are formed is mounted facing the chip mounting surface of the wiring board, and formed on the surface of the wiring board facing the semiconductor chip. There is a flip-chip connection method in which a plurality of terminals and a plurality of electrodes of a semiconductor chip are electrically connected via a plurality of conductive members called bump electrodes. The wire bonding method has an advantage that the manufacturing process can be simplified as compared with the flip chip connection method.

  In the case of a semiconductor device to which this wire bonding method is applied, it is necessary to protect the plurality of wires in order to prevent contact between the plurality of wires or disconnection of the wires. For this reason, a plurality of wires are sealed with a sealing resin. The plurality of electrodes of the semiconductor chip are formed on the main surface side of the semiconductor chip. And since a semiconductor chip is mounted in the state in which the back surface was made to oppose the upper surface of a wiring board, a semiconductor chip is also sealed with sealing resin.

  However, when the semiconductor chip is sealed with a resin, it becomes difficult to cool the semiconductor chip directly from the outside of the semiconductor device, compared to the case where the semiconductor chip is exposed. In general, in a semiconductor device of a type in which a semiconductor chip is mounted on a wiring board containing (main component) containing an organic material, the chip mounting surface of the wiring board is covered with an insulating layer having a lower thermal conductivity than metal. Yes. For this reason, the heat dissipation characteristics of the semiconductor device having the wiring board are insufficient.

  If the heat dissipation characteristic of the semiconductor device cannot be obtained sufficiently, the temperature of the semiconductor chip or the like rises, causing malfunction or noise, and reducing the reliability of the semiconductor device. In particular, in recent years, power consumption tends to increase due to higher functionality of semiconductor devices, and improvement of heat dissipation characteristics has become an important issue from the viewpoint of improving the reliability of semiconductor devices.

  Therefore, the inventor of the present application has made the following investigations regarding the improvement of heat dissipation of a semiconductor device in which a semiconductor chip is mounted on a wiring board and the semiconductor chip is resin-sealed.

  First, the structure which attaches heat dissipation members (heat sink), such as a fin, to the sealing resin which seals a semiconductor chip was examined. However, since the sealing resin is interposed between the semiconductor chip and the heat dissipation member, the heat transfer efficiency is low. For this reason, compared with the case where it attaches to a semiconductor chip without going through sealing resin, heat dissipation efficiency is low.

  Next, for example, as in Patent Document 1, a configuration in which thermal vias are arranged in a region of a wiring board on which a semiconductor chip is mounted was examined. However, in this case, the wiring (wiring pattern) formed on the wiring board and the wiring (in-via wiring) formed inside the through hole (via) of the wiring board are used as a heat dissipation path. The heat transfer area (cross-sectional area) is narrow and the resulting heat dissipation effect is low.

  In addition, as described in Patent Document 2, a configuration in which a semiconductor chip is mounted via a metal plate and the semiconductor chip or the metal plate is not resin-sealed is effective from the viewpoint of improving heat dissipation characteristics. . However, in this case, since the wires that electrically connect the semiconductor chip and the wiring board are not protected, contact between a plurality of wires or disconnection of the wires is likely to occur, and the reliability of the semiconductor device is reduced. .

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in the semiconductor device which is one embodiment of the present invention, the semiconductor chip mounted on the wiring board via the heat dissipation member and the plurality of conductive members that electrically connect the semiconductor chip and the wiring board are sealed. A semiconductor device sealed with a body. The heat dissipating member includes a chip mounting portion on which the semiconductor chip is mounted, and a back surface that is led out from the chip mounting portion toward the outside of the sealing body and is located on the opposite side of the chip mounting surface of the wiring board. It is equipped with a heat dissipation lead that is pulled out to the side.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to one embodiment of the present invention, the reliability of the semiconductor device can be improved.

1 is a perspective view showing an overall structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view showing an internal structure on the upper surface side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line of FIG. It is sectional drawing along the BB line of FIG. FIG. 5 is a cross-sectional view showing an electronic device in which the semiconductor device shown in FIG. 4 is mounted on a mounting substrate. It is an expanded sectional view which expands and shows a part of heat dissipation lead shown in FIG. FIG. 3 is an enlarged plan view showing a positional relationship of a wiring layout connected to an external device when the semiconductor device shown in FIG. 2 is mounted on a mounting board. FIG. 3 is an enlarged plan view showing a main surface side of the semiconductor chip shown in FIG. 2. FIG. 4 is an enlarged cross-sectional view schematically showing a connection portion between the semiconductor chip and the heat dissipation member shown in FIG. 3. FIG. 5 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIGS. It is a top view which shows the whole base material structure prepared by the base material preparation process shown in FIG. It is a top view which shows the wiring board which comprises the base material shown in FIG. It is a top view which shows the lead frame which comprises the base material shown in FIG. FIG. 13 is an enlarged plan view of a portion C shown in FIG. 12, showing a state where an adhesive is applied to the upper surface side of the wiring board shown in FIG. FIG. 15 is an enlarged plan view showing a state in which a lead frame is bonded to the wiring board shown in FIG. 14. FIG. 16 is an enlarged plan view showing a state in which an adhesive is disposed on the lead frame shown in FIG. 15. FIG. 17 is an enlarged plan view showing a state where the semiconductor chip shown in FIG. 8 is mounted on the lead frame shown in FIG. 16. It is an expanded sectional view along the DD line of FIG. It is an expanded sectional view along the EE line of FIG. FIG. 18 is an enlarged plan view showing a state where the semiconductor chip and the wiring board shown in FIG. 17 are wire-bonded. It is the enlarged plan view which expanded further the F section of FIG. It is an expanded sectional view along the DD line of FIG. FIG. 21 is an enlarged plan view showing a state where the semiconductor chip and the wire shown in FIG. 20 are sealed with resin. It is an expanded sectional view along the GG line of FIG. 23 which shows the state which clamped the base material shown in FIG. 20 with the shaping die. It is an expanded sectional view along the HH line of FIG. 23 which shows the state which clamped the base material shown in FIG. 20 with the shaping die. It is an expanded sectional view along the JJ line of FIG. 23 which shows the state which clamped the base material shown in FIG. 20 with a shaping die. FIG. 25 is an enlarged cross-sectional view illustrating a state where sealing resin is supplied into the cavity illustrated in FIG. 24. FIG. 26 is an enlarged cross-sectional view illustrating a state where sealing resin is supplied into the cavity illustrated in FIG. 25. FIG. 24 is an enlarged plan view showing a state in which a plurality of solder balls are joined to the lower surface of the wiring board shown in FIG. 23. FIG. 30 is an enlarged cross-sectional view along the line HH in FIG. 29. It is an enlarged plan view which shows the upper surface side of the base material shown in FIG. FIG. 32 is an enlarged sectional view taken along line KK in FIG. 31. It is an expanded sectional view which shows the state which has arrange | positioned the base material shown in FIG. 32 to a lead bending apparatus. FIG. 34 is an enlarged cross-sectional view showing a state where the lead shown in FIG. 33 is bent. It is an expanded sectional view which shows the state which has arrange | positioned the base material shown in FIG. 34 to a lead front-end | tip cutting device. FIG. 36 is an enlarged cross-sectional view showing a state where the tip of the lead shown in FIG. 35 is cut. FIG. 31 is an enlarged plan view showing a state after the lead shown in FIG. 31 is subjected to the lead processing step shown in FIG. FIG. 38 is an enlarged plan view showing a state in which the base material shown in FIG. 37 is separated into pieces for each device region. FIG. 39 is an enlarged cross-sectional view showing a singulation process, and is a cross-sectional view taken along line LL in FIG. 38. FIG. 6 is a plan view showing a modification of the semiconductor device shown in FIG. 2. FIG. 6 is a plan view showing a modification of the semiconductor device shown in FIG. 2. FIG. 6 is an enlarged cross-sectional view illustrating a modification of the electronic device illustrated in FIG. 5. FIG. 8 is an enlarged plan view showing a positional relationship of a wiring layout connected to an external device when a semiconductor device as a comparative example with respect to FIG. 7 is mounted on a mounting board. FIG. 3 is a plan view showing an internal structure of a main surface side of a semiconductor device which is a comparative example of FIG. 2.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

(Embodiment 1)
<Semiconductor device>
First, the outline of the structure of the semiconductor device according to the present embodiment will be described. FIG. 1 is a perspective view showing the overall structure of the semiconductor device of the present embodiment. FIG. 2 is a plan view showing the internal structure on the upper surface side of the semiconductor device shown in FIG. 3 is a cross-sectional view taken along line AA in FIG. 2, and FIG. 4 is a cross-sectional view taken along line BB in FIG. FIG. 5 is a cross-sectional view showing an electronic device in which the semiconductor device shown in FIG. 4 is mounted on a mounting substrate. In FIG. 2, the position of the sealing resin 4 shown in FIG. 1 is indicated by a two-dot chain line. FIG. 3 is a cross-sectional view taken along the line AA in FIG. 2, but the pads 2c, the wires 3, and the terminals 22 are partly arranged at two points behind the AA cross section. Shown with a chain line.

  A semiconductor device 1 according to the present embodiment includes a semiconductor chip 2 (see FIGS. 2, 3, and 4) mounted on a wiring board 20 via a heat dissipation member 10 (see FIGS. 2, 3, and 4). A plurality of wires (conductive members) 3 (see FIGS. 2 and 3) that electrically connect the semiconductor chip 2 and the wiring board 20 are sealed with a sealing resin (sealing body) 4. Specifically, a plurality of pads (electrodes, chip electrodes) 2c (see FIGS. 2 and 3) formed on the main surface 2a of the semiconductor chip 2 and an upper surface (main surface, surface) 21a of the wiring substrate 20 (FIG. 3). Reference) A plurality of terminals (bonding leads, electrodes) 22 formed thereon are electrically connected to each other via a plurality of wires 3. The plurality of pads 2c, terminals 22 and wires 3 are sealed with a sealing resin 4. That is, the semiconductor device 1 of the present embodiment is a semiconductor device in which the semiconductor chip 2 is mounted on the wiring board 20. Further, by sealing the plurality of wires 3 that electrically connect the semiconductor chip 2 and the wiring substrate 20 with the sealing resin 4, contact between the plurality of wires 3 or disconnection of the wires 3 is prevented. .

  Further, the semiconductor device 1 has the semiconductor chip 2 mounted on the wiring substrate 20 via the heat dissipation member 10, and a part of the heat dissipation member 10 (specifically, part of the heat dissipation lead 10 b) is outside the sealing resin 4. And is formed so that a part is exposed from the sealing resin 4. That is, the semiconductor device 1 is generated inside the sealing resin 4 by disposing the heat radiating member 10 between the semiconductor chip 2 and the wiring substrate 20 and exposing a part of the heat radiating member 10 from the sealing resin 4. A path (heat dissipation path) for transmitting heat (heat generated from the semiconductor chip 2) to the outside of the sealing resin 4 is secured. For this reason, for example, compared with the semiconductor device (illustration omitted) which does not arrange | position the thermal radiation member 10, a thermal radiation characteristic can be improved. Further, by improving the heat dissipation characteristics, malfunction or noise can be prevented or suppressed even when the power consumption of the semiconductor device is increased. The semiconductor device 1 specifically examined by the inventor of the present application is a semiconductor device to be incorporated into a high-functional electronic device used in a high temperature environment, and its power consumption is, for example, 2 W or more.

  As shown in FIG. 5, when the semiconductor device 1 of the present embodiment is mounted on the mounting board (motherboard) 30, a part of the heat radiating member 10 (a part of the heat radiating lead 10 b) is attached to the mounting board 30. These lands (terminals) 31 are joined via a joining member 32 made of, for example, solder. Thereby, the heat transmitted to the heat dissipation lead 10b can be efficiently radiated to the mounting substrate 30 side.

<Wiring board>
Next, details of the wiring board 20 shown in FIGS. 1 to 4 will be described. As shown in FIG. 3, the wiring board 20 of the semiconductor device 1 includes an upper surface (front surface, main surface) 21a that forms a quadrangle in plan view, a lower surface (back surface) 21b that is located on the opposite side of the upper surface 21a, and an upper surface 21a and a lower surface. It has the insulating layer (core layer) 21 which has the side surface located between 21b. The insulating layer 21 is a resin substrate made of, for example, glass epoxy resin. The wiring board 20 has a plurality of wiring layers. 3 and 4 show two wiring layers including a wiring layer formed on the upper surface 21a and a wiring layer formed on the lower surface 21b. In each wiring layer, a plurality of wirings 23 made of, for example, copper (Cu) are formed, and the in-via wiring formed inside a plurality of vias (through holes) 25 that are interlayer conductive paths penetrating the insulating layer 21 (Wiring, interlayer wiring) The wiring 23 of each wiring layer is electrically connected via a 25a. Here, the thickness of the wiring 23 in the present embodiment is about 15 μm to 20 μm.

  On the upper surface 21 a of the insulating layer 21, a chip mounting area 20 a for mounting the semiconductor chip 2 is disposed. In the present embodiment, the chip mounting area 20a has a quadrangular shape in plan view, and is disposed at the approximate center of the upper surface 21a. A plurality of terminals (bonding leads, electrodes) 22 are formed on the upper surface 21a around the chip mounting area 20a. The plurality of terminals 22 are made of, for example, copper (Cu), and a plating film (not shown) is formed on the surface thereof. In the present embodiment, the plating film is, for example, a laminated film in which a gold (Au) film is laminated on a nickel (Ni) film. As shown in FIG. 2, the plurality of terminals 22 are arranged side by side along each side of the chip mounting area 20a. In the present embodiment, the terminals 22 are provided over a plurality of rows (two rows in the present embodiment) along each side of the chip mounting region 20a (in other words, each side of the semiconductor chip 2). Has been placed. Thus, by arranging the array of the terminals 22 along each side of the chip mounting area 20a in a plurality of rows, an increase in the arrangement space of the terminals 22 can be suppressed, and many terminals 22 can be arranged. . That is, many terminals 22 can be arranged while suppressing an increase in the planar size of the semiconductor device 1. Further, as shown in FIG. 3, the plurality of terminals 22 are formed integrally with the plurality of wirings 23a formed on the upper surface 21a, and electrically connected to the plurality of wirings 23b formed on the lower surface 21b through the vias 25. It is connected to the. That is, the conductive path connected to the plurality of terminals 22 is drawn to the lower surface 21b side via the wiring 23 and the via wiring 25a formed inside the via 25. An insulating film (solder resist film) 26 made of an insulating resin is formed on the upper surface 21 a of the insulating layer 21, and the plurality of wirings 23 a are covered with the insulating film 26. The insulating film 26 has an opening 26 a at a position overlapping the plurality of terminals 22, and the terminal 22 is exposed from the insulating film 26 in the opening 26 a.

  A plurality of lands (terminals, electrodes) 24 are formed on the lower surface 21 b of the insulating layer 21. The plurality of lands 24 are made of, for example, copper (Cu), and a plating film (not shown) is formed on the surface thereof. In the present embodiment, the plating film is, for example, a laminated film in which a gold (Au) film is laminated on a nickel (Ni) film. Although not shown, the plurality of lands 24 are arranged in an array (matrix or matrix) on the lower surface 21b. Thus, by arranging the plurality of lands 24 in an array on the lower surface 21b, a large number of lands 24 can be arranged in a space-saving manner. Further, as shown in FIG. 3, the plurality of lands 24 are formed integrally with the plurality of wirings 23b formed on the lower surface 21b, and are electrically connected to the plurality of terminals 22 through the vias 25 and the wirings 23a, respectively. Has been. Further, an insulating film (solder resist film) 27 made of an insulating resin is formed on the lower surface 21 b of the insulating layer 21, and the plurality of wirings 23 b are covered with the insulating film 27. The insulating film 27 has an opening formed at a position overlapping the plurality of lands 24, and the land 24 is exposed from the insulating film 27 in the opening.

  As shown in FIGS. 3 and 4, a plurality of solder materials (external electrodes of the semiconductor device 1 when the semiconductor device 1 is mounted on the mounting substrate 30 shown in FIG. Solder balls) 28 are joined to each other. The solder material 28 of the present embodiment is made of so-called lead-free solder that does not substantially contain lead (Pb). For example, only tin (Sn), tin-bismuth (Sn-Bi), or tin-copper- For example, silver (Sn—Cu—Ag). Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHs (Restriction of Hazardous Substances) directive. Hereinafter, in the present embodiment, when a solder or solder ball is described, it indicates a lead-free solder unless otherwise specified. The joining member 32 shown in FIG. 5 is also lead-free solder.

  3 shows a wiring board having two wiring layers in which wirings 23 are formed on the upper surface 21a and the lower surface 21b of the insulating layer 21. FIG. However, the number of wiring layers of the wiring board 20 is not limited to two. For example, a so-called multilayer wiring board in which a plurality of wiring layers (wirings 23) are formed in the insulating layer 21 may be used. In this case, by further forming a wiring layer between the uppermost wiring layer and the lowermost wiring layer, it is possible to increase the space for routing the wiring, which is particularly effective when applied to a semiconductor device having a large number of terminals. is there.

  In FIG. 2, a part of the terminal 22 is not shown for easy viewing. Therefore, the number of terminals 22 is larger than that shown in FIG. 2, and can be, for example, about 360 to 450 pins.

<Heat dissipation member>
Next, the detail of the heat radiating member 10 shown in FIGS. 1-4 is demonstrated. FIG. 6 is an enlarged cross-sectional view showing a part of the heat dissipation lead shown in FIG.

  The heat dissipating member 10 has a chip mounting portion (tab, die pad) 10a and a plurality (four in FIG. 2) of heat dissipating leads (leads) 10b formed integrally with the chip mounting portion 10a. As shown in FIG. 2, the heat radiating member 10 is disposed on the wiring board 20 so that the chip mounting area 10 a of the heat radiating member 10 overlaps the chip mounting area 20 a of the wiring board 20. At this time, as shown in FIG. 2, the plurality of heat radiating leads 10 b of the heat radiating member 10 are arranged on regions extending from the central portion of the wiring board 20 toward the corner portions.

  Here, as described above, since the plurality of terminals 22 are arranged over a plurality of rows on each side of the wiring board 20, the arrangement length constituted by the plurality of terminals 22 per row is reduced. Therefore, the plurality of leads 10b can be arranged so as to substantially overlap the corners of the wiring board 20 (regions along the diagonal of the wiring board). In other words, since the terminal 22 is not covered with the lead 10b, the wire 3 can be connected to the terminal 22.

  As described above, the heat radiating member 10 serves as a heat dissipation path for transmitting heat generated inside the sealing resin 4 to the outside of the sealing resin 4, and thus a metal material having a higher thermal conductivity than the sealing resin 4, In the present embodiment, for example, it is made of copper (Cu). In addition, the thickness of the heat dissipation lead 10 b that is a part of the heat dissipation path in the present embodiment is 100 μm or more, and is larger than the thickness of the wiring 23 formed on the wiring board 20.

  As shown in FIG. 6, the heat radiating member 10 has a plating film (exterior plating) made of, for example, palladium (Pd) on the surface of the main material 10e made of copper (Cu), which has higher solder wettability than the main material 10e. Layer) 10f is formed. As shown in FIG. 5, the semiconductor device 1 of the present embodiment joins the heat dissipation lead 10 b to the land 31 on the mounting substrate 30 side to efficiently generate heat generated in the sealing resin 4. Although it is structured to transmit to the side, the wettability of the joining member 32 to the heat dissipation lead 10b can be improved by forming the plating film 10f (see FIG. 6) on the surface of the heat dissipation lead 10b. As a result, the bonding strength between the heat dissipation lead 10b and the land 31 of the mounting substrate 30 can be improved. That is, since the breakage of the joint between the heat radiation lead 10b and the land 31 can be prevented or suppressed, high heat radiation characteristics can be stably maintained.

  Further, the heat radiating member 10 has an upper surface (main surface, chip mounting surface) 10c and a lower surface (back surface) 10d located on the opposite side of the upper surface 10c. The chip mounting portion 10a of the heat radiating member 10 is placed on the chip mounting area 20a of the wiring board 20 via the adhesive 11 (specifically, the wiring board 20 in detail) with the lower surface 10d and the upper surface 21a of the wiring board 20 facing each other. It is fixed on the insulating film 26). The adhesive 11 is also disposed between the lower surface 10 d of the heat dissipation lead 10 b and the wiring board 20, and the heat dissipation lead 10 b disposed on the upper surface 21 a of the wiring board 20 is interposed via the adhesive 11. The insulating film 26 is fixed. For this reason, deformation of the heat dissipation lead 10b can be prevented.

  The bonding material 11 can be a bonding material for die-bonding a semiconductor chip. In the present embodiment, the bonding material 11 is made of an organic bonding material such as epoxy or acrylic. In addition, as a modification of the present embodiment, a so-called conductive adhesive containing a metal filler such as silver (Ag) particles in a base resin (for example, epoxy resin) can be used. In this case, the thermal conductivity of the adhesive 11 can be increased by including a metal filler having a higher thermal conductivity than the base resin. For this reason, the heat dissipation efficiency of the heat dissipation path toward the lower surface 21 b of the wiring substrate 20 is improved via the adhesive 11. Further, by disposing the adhesive 11 in the extending direction of the heat dissipation lead 10b, the heat dissipation efficiency of the heat dissipation path toward the extending direction of the heat dissipation lead 10b is improved.

  Further, as a method of fixing the heat radiating member 10 on the wiring substrate 20, a method of directly adhering the heat radiating member 10 on the insulating layer 21 without using the insulating film 26 is also conceivable. However, in this case, there is a restriction on the wiring layout of the uppermost layer wiring (wiring 23a shown in FIGS. 3 and 4) formed on the insulating layer 21. That is, in order to prevent a short circuit between the uppermost layer wiring and the heat radiating member 10, the uppermost layer wiring needs to be routed around the heat radiating member 10. Therefore, as in the present embodiment, it is preferable that the heat radiating member 10 is fixed on the insulating film 26 covering the wiring 23a which is the uppermost layer wiring. This is because by disposing the insulating film 26 between the heat dissipation member 10 and the wiring 23a, the degree of freedom of layout of the wiring 23a is greatly increased.

  Next, the detailed structure of the heat dissipation lead 10b of the heat dissipation member 10 will be described. As shown in FIG. 4, the heat radiating lead 10 b is bent outside the outer edge of the wiring board 20, and is drawn below the lower surface 21 b of the wiring board 20 (below the land 24). Specifically, the heat radiating lead 10 b is bent outside the corner portion of the wiring substrate 20, and further extends toward the same height as the solder material 28 joined to the land 24. Thereby, when the semiconductor device 1 is mounted on the mounting substrate 30 as shown in FIG. 5, the heat dissipation lead 10 b and the land 31 can be joined.

  Further, by using a conductive member such as solder as the joining member 32 that joins the heat dissipation lead 10b and the land 31 of the mounting substrate 30, the heat dissipation lead 10b and the land 31 can be electrically connected. For this reason, the heat dissipation lead 10b can be used as an electrode (terminal) of the semiconductor device 1 in addition to a function as a heat dissipation path. For example, in the present embodiment, the heat dissipation lead 10 b is used as an electrode for supplying a reference potential to the semiconductor device 1. Therefore, the reference potential current flows through the heat dissipation lead 10b. In addition, you may use this thermal radiation lead 10b as an electrode which supplies a power supply potential.

  Further, as shown in FIG. 4, the thickness of the chip mounting portion 10 a and the heat radiating lead 10 b is thicker than the thickness of the wiring 23 of the wiring board 20. For example, in the present embodiment, the thickness of the wiring 23 is about 15 μm to 20 μm, whereas the thickness of the chip mounting portion 10a and the heat radiation lead 10b is 100 μm or more.

  By forming the heat radiating member 10 thicker than the wiring 23 as described above, the following effects can be obtained. That is, as a first effect, the heat transfer area of the heat dissipation path can be increased by increasing the thickness of the heat dissipation member 10 (particularly, the heat dissipation lead 10b). Since the heat dissipation efficiency increases in proportion to the heat transfer area of the heat dissipation path, the heat dissipation efficiency can be improved. Further, as a second effect, by increasing the thickness of the heat dissipation member 10 (particularly, the heat dissipation lead 10b), the strength of the heat dissipation member 10 is increased. As a result, in the manufacturing process of the semiconductor device 1, the handling properties of the components of the heat radiating member 10 are improved (for example, deformation at the time of transportation or processing can be prevented), and thus the productivity is improved.

  Further, as shown in FIG. 2, the width (thickness) of the heat dissipation lead 10b is thicker than the wiring 23 and the terminal 22 (thickness) formed on the wiring board 20. Thus, the heat transfer area of the heat dissipation path is also increased by increasing the width of the heat dissipation lead 10b. From the viewpoint of improving the heat dissipation characteristics, it is preferable to increase the heat transfer area (cross-sectional area). However, when the thickness of the heat dissipation member 10 is excessively increased, the package height of the semiconductor device 1 is increased. Occurs. Therefore, if the heat transfer area is increased by increasing the width of the heat dissipation lead 10b as in the present embodiment, the heat dissipation characteristics can be sufficiently improved without excessively thickening the heat dissipation member 10. it can. For example, in the present embodiment, as shown in FIGS. 3 and 4, the thickness of the heat dissipation member 10 is thinner than the thickness of the semiconductor chip 2. That is, according to the present embodiment, it is possible to improve heat dissipation characteristics and to suppress an increase in the package height of the semiconductor device 1.

  However, if the width of the heat dissipating lead 10b is made extremely large, the heat dissipating lead 10b and a plurality of terminals 22 formed along a certain side of the upper surface of the wiring board 20 (or others formed in a direction intersecting with this side) The distance from the plurality of terminals 22) formed along the side of the line is reduced. In this case, when connecting the wire 3 to a terminal arranged at the end of the plurality of terminals 22, there is a possibility that a capillary (not shown) used in the wire bonding step contacts the heat radiating lead 10 b. Therefore, when mounting the semiconductor chip 2 having the plurality of pads 2c on the wiring board 20 having a small outer size, it is preferable to use the heat dissipation member 10 having a large thickness as in the present embodiment.

  Next, the size (size in plan view; plane size) of the chip mounting portion 10a of the heat dissipation member 10 will be described. As shown in FIG. 2, the size of the chip mounting portion 10 a of the present embodiment is equal to or smaller than the size of the chip mounting region 20 a of the wiring substrate 20, in other words, the size of the semiconductor chip 2. As described above, the heat dissipation efficiency is improved in proportion to the heat transfer area of the heat dissipation path, so that the size of the chip mounting portion 10a is better from the viewpoint of improving the heat dissipation characteristics.

  However, according to the study by the present inventor, it has been found that if the size of the chip mounting portion 10a is made larger than that of the semiconductor chip 2, the following problems arise. That is, the arrangement space of the terminals 22 of the wiring board 20 is reduced. Since the terminal 22 is a bonding lead for bonding the wire 3 as shown in FIG. 2, the bonding surface of the wire 3 needs to be exposed. Therefore, if the chip mounting portion 10a of the heat dissipation member 10 covering the wiring substrate 20 is enlarged, the arrangement space of the terminals 22 is reduced. Note that Patent Document 2 discloses that a bonding pad is exposed by forming a hole in a metal plate disposed on a wiring board. However, in this case, unless the holes of the metal plate and the plurality of bonding pads are precisely aligned, a part of the bonding pad is covered with the metal plate, which causes a wire bonding failure.

  Therefore, in the present embodiment, as described above, the size of the chip mounting portion 10a is set to be equal to or smaller than the size of the chip mounting region 20a of the wiring board 20, in other words, the size of the semiconductor chip 2. As a result, as shown in FIGS. 3 and 4, the chip mounting portion 10 a is covered with the back surface 2 b of the semiconductor chip 2. Specifically, the entire chip mounting portion 10 a is covered with the back surface 2 b of the semiconductor chip 2. Thus, by setting the chip mounting portion 10a to a size that is covered by the semiconductor chip 2, a sufficient space for arranging the terminals 22 can be secured. For example, as shown in FIG. 2, even in a multi-pin type semiconductor device in which the array of terminals 22 along each side of the chip mounting area 20a is arranged in a plurality of rows, the heat dissipation member 10 is disposed on the wiring board 20. Can be arranged.

  However, since the chip mounting area 20a of the wiring substrate 20 is an area covered by the semiconductor chip 2, even if the size of the chip mounting portion 10a is extremely smaller than the size of the chip mounting area 20a, the chip mounting area 20a is not included in the chip mounting area 20a. The terminal 22 which is a lead for wire bonding cannot be formed. Therefore, the size of the chip mounting portion 10a is the same as or slightly smaller than the size of the chip mounting region 20a from the viewpoint of sufficiently securing the arrangement space of the terminals 22 and improving the heat dissipation characteristics. It is particularly preferable that the size is the same as the size of the chip mounting area 20a. In the present embodiment, the shape of the chip mounting portion 10a in plan view is described as a circle, but from the viewpoint of aligning the sizes of the chip mounting region 20a and the chip mounting portion 10a, the shape of the chip mounting portion 10a is: It is particularly preferable to form a quadrangle along the outline of the chip mounting area 20a in plan view. Further, when the planar shape of the chip mounting portion 10a is made to be a quadrangle along the outline of the chip mounting region 20a, the chip mounting portion 10a is directly below each pad 2c in the wire bonding process of the manufacturing process of the semiconductor device 1 described later. Therefore, wire bonding can be easily performed.

  Next, the extending direction of the heat dissipation lead 10b shown in FIG. 2 will be described. As shown in FIG. 2, the heat dissipation leads 10 b of the semiconductor device 1 extend from the chip mounting portion 10 a toward the corners of the wiring substrate 20. In the present embodiment, the heat radiating member 10 has four heat radiating leads 10b, and each heat radiating lead 10b is directed from the corner of the chip mounting portion 10a (the corner of the semiconductor chip 2) to the four corners of the wiring board 20. Are arranged so as to extend. As described above, the heat dissipation lead 10b serves as a heat dissipation path for transmitting the heat generated inside the sealing resin 4 to the outside of the sealing resin 4, so that the heat dissipation lead 10b is formed integrally with the chip mounting portion 10a. (Connected to the chip mounting portion 10a). This is to prevent the heat dissipation efficiency from being reduced by dividing the heat dissipation lead 10b and the chip mounting portion 10a.

  Note that Patent Document 2 describes a shape in which a metal plate is formed so as to wrap around an upper surface and a side surface of a wiring board, and a ground terminal is formed at a lower portion of the side surface. According to FIG. 4 of Patent Document 2, the ground terminal is formed on the side of the wiring board having a square planar shape. However, when the ground terminal having such a shape is formed, there are restrictions on the wiring layout of the mounting substrate on which the semiconductor device is mounted. That is, since it is necessary to lay out other wirings while avoiding the terminals and wirings on the mounting board side that are electrically connected to the ground terminals, it is difficult to route wiring on the mounting board.

  Therefore, in the present embodiment, in the wiring layout of the mounting substrate 30, the heat dissipation leads 10 b are extended toward the corners of the wiring substrate 20 in order to shorten the transmission distance. FIG. 7 is an enlarged plan view showing a positional relationship of a wiring layout connected to an external device when the semiconductor device shown in FIG. 2 is mounted on a mounting board. FIG. 43 is an enlarged plan view showing a positional relationship of a wiring layout connected to an external device when a semiconductor device which is a comparative example with respect to FIG. 7 is mounted on a mounting board. 7 and 8, in order to show the wiring layout on the mounting substrate 30, the lands 33, 34 and the wiring 35 that electrically connects them are shown by dotted lines. In addition, the wiring 36 serving as a heat dissipation path of the mounting substrate 30 is similarly indicated by a dotted line.

  Various currents such as a signal current, a power supply potential current, and a reference potential current flow through the semiconductor device 1. However, depending on the type of current, the transmission distance becomes longer, thereby increasing the impedance component and noise, thereby increasing reliability. It will cause a drop. For example, it is preferable to shorten the transmission distance of a wiring path through which a signal current flows from the viewpoint of improving reliability. Also, the wiring path connected to the analog circuit is particularly susceptible to the transmission distance. For this reason, the lands 24 (see FIG. 3) through which the signal current and the analog circuit current flow are preferably arranged on the outermost periphery of the land arrangement arranged in a matrix. As shown in FIG. 7, in the region where the semiconductor device 1 is mounted on the mounting substrate 30, the land 33 arranged on the outermost periphery is a land 34 connected to an external device (external electronic device; for example, a semiconductor device) 37. This is because the transmission distance can be shortened.

  However, like the semiconductor device 100 of the comparative example shown in FIG. 43, the heat dissipation leads 10b are extended toward the sides (between adjacent corners) of the wiring board 20 and bonded to the lands 101 of the mounting board. In this case, the wiring 102 that electrically connects the land 33 and the land 34 needs to be detoured by avoiding the land 101 and the wiring 103 connected thereto. In order to reduce the detour distance, it is necessary to reduce the distance between the wiring 102 and the wiring 103. In this case, the heat transmitted to the wiring 103 becomes a noise source of the current flowing through the wiring 102.

  On the other hand, as shown in FIG. 7, according to the present embodiment, by extending the heat radiation lead 10b toward the corner of the wiring board 20, the wiring 35 that electrically connects the land 31 and the land 33 is formed. They can be arranged substantially linearly. That is, the wiring path of the wiring 35 can be minimized. Moreover, since the distance between the land 31 connected to the heat radiating lead 10b or the wiring 35 connected thereto and the wiring 35 can be sufficiently separated, noise due to thermal influence can be reduced. For this reason, the semiconductor device 1 can improve reliability compared with the semiconductor device 100 shown in FIG.

  Further, from the viewpoint of simply increasing the number of heat dissipation paths, for example, a method of additionally forming the heat dissipation leads 10b extending toward the sides of the wiring board 20 shown in FIG. However, when the heat radiation lead 10b is extended toward the side portion of the wiring board 20, as described above, in the wiring layout of the mounting board 30, there is a problem that the transmission distance becomes long, and the wiring 23 and terminals of the wiring board 20 There arises a problem that the layout of 22 is restricted. For this reason, in the present embodiment, the number of heat radiation leads 10 b is smaller than the number of lands 24, and four heat radiation leads 10 b are arranged toward each corner of the wiring board 20.

<Semiconductor chip>
Next, the semiconductor chip 2 mounted on the wiring board 20 will be described. FIG. 8 is an enlarged plan view showing the main surface side of the semiconductor chip shown in FIG. FIG. 9 is an enlarged cross-sectional view schematically showing a connection portion between the semiconductor chip and the heat dissipation member shown in FIG.

  The semiconductor chip 2 of the present embodiment has a main surface 2a, a back surface 2b positioned on the opposite side of the main surface 2a, and a side surface positioned between the main surface 2a and the back surface 2b. The planar shape of the semiconductor chip 2 (the shape of the main surface 2a and the back surface 2b) is substantially rectangular.

  As shown in FIG. 8, a plurality of pads (electrodes, chip electrodes) 2 c are formed on the main surface 2 a of the semiconductor chip 2. The plurality of pads 2 c are arranged side by side on the peripheral edge side on the main surface 2 a along each side of the semiconductor chip 2. In the present embodiment, the pads 2c are arranged in a plurality of rows (two rows in FIG. 8) along each side of the main surface 2a. In other words, the plurality of pads 2c include a plurality of first-row pads (first-row electrodes) 2d formed in the outermost first row with respect to the main surface 2a of the semiconductor chip 2 and first-row pads. A plurality of second row pads (second row electrodes) 2e formed on the inner side (center side of the main surface 2a) than 2d are included. In this way, by arranging the plurality of pads 2c of the semiconductor chip 2 in a plurality of rows along each side of the main surface 2a, an increase in the arrangement space of the pads 2c is suppressed, and many pads 2c are arranged. can do. That is, many pads 2c can be arranged while suppressing an increase in the planar dimension of the semiconductor chip 2.

  Also, a plurality of semiconductor elements (circuit elements) such as diodes and transistors are formed on the main surface 2a of the semiconductor chip 2, and a plurality of pads are provided via wirings (wiring layers) (not shown) formed on the semiconductor elements. 2c is electrically connected to each other. Thus, the semiconductor chip 2 constitutes an integrated circuit by a plurality of semiconductor elements formed on the main surface 2a and wirings that electrically connect the plurality of semiconductor elements.

  The base material (semiconductor substrate) of the semiconductor chip 2 is made of, for example, silicon (Si). An insulating film is formed on the main surface 2a, and each surface of the plurality of pads 2c is exposed from the insulating film at an opening formed in the insulating film.

  The pad 2c is made of metal, and in this embodiment, is made of, for example, aluminum (Al). Further, a plating film is formed on the surface of the pad 2c. In the present embodiment, for example, a multilayer plating film having a multilayer structure in which a gold (Au) film is formed via a nickel (Ni) film is used. is there.

  As shown in FIGS. 3 and 4, in the present embodiment, the semiconductor chip 2 is placed on the chip mounting region 20a of the wiring board 20 with the back surface 2b facing the upper surface 10c of the chip mounting portion 10a of the heat radiating member 10. It is mounted by a so-called face-up mounting method. The semiconductor chip 2 is fixed to the upper surface of the chip mounting portion 10a through the adhesive material 12.

  Here, in the present embodiment, as shown in FIG. 9, as the adhesive 12, a base resin (for example, epoxy resin) 12 a contains a plurality of metal fillers 12 b made of, for example, silver (Ag) particles, A so-called conductive adhesive is used. As described above, the thermal conductivity of the adhesive 12 can be increased by including the metal filler 12b having a higher thermal conductivity than the base resin 12a in the adhesive 12. For this reason, the heat radiation efficiency of the heat radiation path toward the heat radiation member 10 is improved through the adhesive 12. As described above, the adhesive 11 also preferably includes a metal filler, but it is particularly preferable that the adhesive 12 for fixing the semiconductor chip 2 includes the metal filler 12b. This is because it becomes a main heat dissipation path for transferring heat from the semiconductor chip 2 to the heat dissipation member 10. In the present embodiment, the reference potential is supplied to the semiconductor chip 2 via the heat dissipation lead 10b. However, by using the adhesive 12 as a conductive adhesive, the back surface 2b of the semiconductor chip 2 and the chip mounting are provided. The upper surface 10c of the part 10a can be electrically connected. For this reason, in this Embodiment, the silver (Ag) particle | grains with small electrical resistance are used as a metal filler. Furthermore, by forming a metal plating film (not shown) on the back surface 2b of the semiconductor chip 2, the resistance at the connection interface between the back surface 2b and the adhesive 12 can be reduced. In this case, the heat resistance can also be reduced, so that the heat dissipation characteristics are also improved. In addition, if the back surface 2b of the semiconductor chip 2 is not electrically connected to the top surface 10c of the chip mounting portion 10a, the adhesive material 12 is not required to have conductivity. However, even if the electrical conductivity is not required, from the viewpoint of improving the heat dissipation characteristics, the filler (metal filler 12b or metal filler 12b or It is preferable to contain a nonmetallic filler).

  Next, wire bonding connection for electrically connecting the semiconductor chip 2 and the wiring board 20 will be described. FIG. 44 is a plan view showing the internal structure of the main surface side of the semiconductor device which is a comparative example of FIG. The semiconductor device 100 shown in FIG. 44 differs from the semiconductor device 1 shown in FIG. 2 in that the heat dissipation lead 10b of the heat dissipation member 10 extends toward the side portion (between adjacent corner portions) of the wiring board 20. Different.

  As shown in FIGS. 2 and 3, the semiconductor chip 2 is electrically connected to the wiring board 20 via a plurality of wires 3. Specifically, one end of the wire 3 is connected to the pad 2 c on the main surface 2 a of the semiconductor chip 2, and the other is connected to the terminal 22 of the wiring substrate 20. In the present embodiment, the wire 3 is made of gold (Au), and is bonded to the gold plating film formed on the surface of the pad 2c of the semiconductor chip 2 and the terminal 22 of the wiring substrate 20 by Au—Au bonding.

  Here, as in the semiconductor device 1 of the present embodiment, extending the heat dissipating leads 10b toward the corners of the wiring board 20 has the following merit in wire bonding connection. That is, since the distance between the pad 2c of the semiconductor chip 2 and the terminal 22 of the wiring substrate 20 can be reduced, the wire length of the wire 3 can be shortened.

  As in the semiconductor device 100 shown in FIG. 44, when the heat dissipation leads 10b are extended toward the sides of the wiring board 20, the terminals 22 of the wiring board 20 need to be arranged avoiding the heat dissipation leads 10b. On the other hand, the pads 2c of the semiconductor chip 2 are arranged along each side of the main surface 2a, as in FIG. As a result, in the semiconductor device 100, the wire length of the wire 3 is longer than that of the semiconductor device 1. As the wire 3 becomes longer, the impedance component increases. Moreover, since the wire 3 becomes easy to deform | transform during a manufacturing process when the wire length of the wire 3 becomes long, the concern that adjacent wires 3 contact will increase.

  On the other hand, as in the semiconductor device 1 of the present embodiment, if the heat radiating leads 10b extend toward the corners, even if the plurality of terminals 22 are arranged close to the plurality of pads 2c, they interfere with the heat radiating leads 10b. do not do. Therefore, the wire length of the wire 3 can be shortened. Thus, it is preferable from the viewpoint of wire bonding connection to extend the heat radiating lead 10b toward the corner of the wiring board.

<Sealing resin>
Next, the sealing resin 4 that seals the semiconductor chip 2, the plurality of wires 3, and the plurality of terminals 22 will be described. As shown in FIG. 3, the sealing resin 4 of the present embodiment is formed on the upper surface 21 a side of the wiring substrate 20 and seals the semiconductor chip 2, the plurality of wires 3, and the plurality of terminals 22. Moreover, as shown in FIG. 4, the sealing resin 4 seals a part of the chip mounting portion 10a of the heat dissipation member 10 and the heat dissipation lead 10b.

  Further, the sealing resin 4 does not cover the entire upper surface 21 a side of the wiring substrate 20, but the peripheral edge of the wiring substrate 20 is exposed from the sealing resin 4. For this reason, a part of the heat radiating lead 10 b extending to the outside of the outer edge of the wiring board 20 is exposed from the sealing resin 4 on the upper surface 21 a side of the wiring board 20. For this reason, compared with the structure which covers the whole upper surface 21a side of the wiring board 20 with sealing resin, since the exposed area of the radiation | emission lead 10b increases, thermal radiation efficiency improves.

  Further, the structure in which a part of the upper surface 21a side of the wiring substrate 20 is exposed from the sealing resin 4 has an advantage that it is easy to make when assembling the semiconductor device 1. This will be described later.

<Manufacturing process of semiconductor device>
Next, the manufacturing process of the semiconductor device 1 shown in FIGS. 1 to 4 will be described. The semiconductor device 1 in the present embodiment is manufactured along the assembly flow shown in FIG. FIG. 10 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIGS. Details of each step will be described below with reference to FIGS.

1. Substrate preparation step;
First, as a base material preparation step (S1) shown in FIG. 10, a base material 40 as shown in FIG. 11 is prepared. 11 is a plan view showing the overall structure of the base material prepared in the base material preparation step shown in FIG. 10, FIG. 12 is a plan view showing the wiring board constituting the base material shown in FIG. 11, and FIG. FIG. 12 is a plan view showing a lead frame constituting the base material shown in FIG. FIG. 14 is an enlarged plan view of a portion C shown in FIG. 12, showing a state where an adhesive is applied to the upper surface side of the wiring board shown in FIG. FIG. 15 is an enlarged plan view showing a state in which a lead frame is bonded onto the wiring board shown in FIG.

  As shown in FIG. 11, the base material 40 prepared in this step is formed by bonding a lead frame 42 on a wiring board 41. As shown in FIG. 12, the wiring board 41 includes a plurality of device regions 41a inside a frame portion (frame body) 41b in plan view. That is, the wiring board 41 is a so-called multi-piece board having a plurality of device regions 41a. Each device region 41a corresponds to the wiring board 20 shown in FIG. 2, and each member of the wiring board 20 described with reference to FIGS. 1 to 4 (excluding the solder material 28) is formed.

  Each device region 41a is supported by a suspending portion 41c that connects the frame portion 41b and each device region 41a. In other words, the plurality of device regions 41a are supported by the plurality of hanging portions 41c connected to the frame portion 41b. In the present embodiment, the suspension portion 41c is formed integrally with both the frame portion 41b and each device region 41a, and each device region 41a is supported by a plurality of (two in FIG. 12) suspension portions 41c. is doing. For this reason, a slit 41d penetrating from the upper surface to the lower surface of the wiring board is formed between each device region 41a.

  More specifically, as shown in FIG. 12, a plurality of hanging portions 41c are connected to each of the long sides of the frame portion 41b having a rectangular outline, and each device region 41a extends along the short side of the frame portion 41b. It is supported by two extending suspension parts 41c. Further, the hanging portions 41c are not disposed between the device regions 41a or between the device regions 41a and the short sides of the frame portion 41b. That is, each device region 41a is connected to the frame portion 41b by two-point support.

  Further, the width of each suspension part 41c (the length in the direction along the long side of the frame part 41b) is narrower than the width of the device region 41a, and each suspension part 41c is a side of the device region 41a having a rectangular planar shape. It is connected to the approximate center. Accordingly, the slits 41d are arranged outside the four corners of the device region 41a.

  As described above, when the slits 41d are formed around each device region 41a corresponding to the wiring substrate 20 shown in FIG. 2 (particularly around the corners of the device region 41a having a quadrangular planar shape), the lead processing step shown in FIG. In S7, the lead (heat radiation lead) provided in the lead frame 42 can be easily bent or cut.

  As shown in FIG. 14, each device region 41a has a chip mounting region 20a and a plurality of terminals (bonding leads) 22 arranged side by side around the chip mounting region 20a. The planar shape of the chip mounting region 20a forms a quadrangle corresponding to the planar shape of the semiconductor chip 2 (see FIG. 2) to be mounted.

  As shown in FIG. 13, the lead frame 42 in the plan view includes a plurality of device regions 42a inside a rectangular frame (frame body) 42b, like the wiring board 41 shown in FIG. In each device region 42a, a chip mounting portion (tab, die pad) 10a disposed substantially at the center of the device region 42a and the chip mounting portion 10a are formed integrally with each corner portion of the device region 42a from the chip mounting portion 10a. And a plurality of (four in FIG. 3) leads (heat dissipating leads) 42c extending toward the bottom. In other words, each device region 42a is arranged inside the device region 42a (or the frame portion 42) in a plan view and supported by the plurality of leads 42c. Chip mounting portion 10a.

  The plurality of leads 42c are processed in the lead processing step S7 (details will be described later) shown in FIG. 10 to become the heat radiating leads 10b shown in FIG. 2, but at this stage, one end is a chip. The other end of the mounting portion 10a is connected to the frame portion 42b. That is, the lead 42 c functions as a suspension lead that supports the chip mounting portion 10 a of the lead frame 42. In the present embodiment, in order to prevent deformation of the lead frame 42 during processing, reinforcing leads 42d are formed between the device regions 42a, and the reinforcing leads 42d are connected to the frame portion 42b.

  Further, on the surface of the lead 42c shown in FIG. 13, a plating film (exterior plating layer) 10f (see FIG. 6) made of, for example, palladium (Pd), which has higher wettability to solder than the main material 10e (see FIG. 6). Is formed in advance. In other words, the plating film 10f shown in FIG. 6 is formed by a so-called tip plating method. In general, when forming an exterior plating layer on the surface of a plurality of leads of a lead frame type semiconductor device, the substrate 40 is immersed in a solder plating solution after the sealing step S5 shown in FIG. It is formed by a so-called post plating method. However, since the lead frame 42 according to the present embodiment is mounted on the wiring board 41, the plating layer is also formed on the surface of the land 24 (see FIG. 3) exposed on the lower surface of the wiring board 41 when the post-plating method is used. Will be formed. If a plating layer is formed on the surface of the land 24, a ball mounting defect occurs in the ball mounting step S6 shown in FIG. Even when the post-plating method is used, if the land 24 (see FIG. 3) exposed on the lower surface of the wiring substrate 41 is covered with a mask (not shown), the formation of a plating layer on the surface of the land 24 is prevented. can do. However, in this case, since a step of covering with a mask is added, it is preferable to use a pre-plating method as in the present embodiment from the viewpoint of improving manufacturing efficiency.

  Next, the planar positional relationship between the members constituting the wiring board 41 and the lead frame 42 will be described. As shown in FIG. 11, the chip mounting portion 10a of the lead frame 42 is disposed on the device region 41a of the wiring board 41, specifically, on the chip mounting region 20a (see FIG. 12). Further, some of the plurality of leads 42 c (protrusions protruding outward from the device region 41 a) and the reinforcing leads 42 d are disposed on the slits 41 d of the wiring board 41. Thus, by arranging a part of the plurality of leads 42c on the slit 41d of the wiring board 41, the lead 42c can be easily bent or cut in the lead processing step S7 shown in FIG. . The frame part 42 b of the lead frame 42 is disposed on the frame part 41 b of the wiring board 41.

  Next, the formation method of the base material 40 shown in FIG. 11 is demonstrated. A base material 40 shown in FIG. 11 is formed by bonding and fixing a lead frame 42 on a wiring board 41.

  Specifically, first, as shown in FIG. 14, an adhesive paste (bond material) 11 a is applied (arranged) on each device region 41 a of the wiring substrate 41. The bonding paste 11a is made of, for example, a thermosetting resin such as epoxy or acrylic, and has a paste-like property (a state having fluidity) before curing. This is applied to a plurality of points in each device region 41a from a nozzle (not shown). For example, as shown in FIG. 14, the application position is applied to the position where the chip mounting portion 10a (see FIG. 13) of the lead frame 42 (see FIG. 13) and the plurality of leads 42c (see FIG. 13) are arranged. ing. The reason why the bonding paste 11a is applied to the position where the plurality of leads 42c is arranged is to firmly bond and fix a part of the leads 42c on the wiring board 41.

  Next, as shown in FIG. 15, the lead frame 42 is overlaid on the wiring board 41 so that the chip mounting portion 10 a of the lead frame 42 is disposed on the chip mounting area 20 a of the wiring board 20 in a plan view. Bonding (fixing) is performed via the bonding paste 11a. At this time, for example, when the lead frame 42 is pressed in the direction of the wiring board 41, the adhesive paste 11a (see FIG. 14) applied in advance is applied to the chip mounting region 20a and the leads 42c and the wiring board 41. Spreads wet in a plane. That is, the chip mounting portion 10a and the lead 42c of the lead frame 42 are bonded to the wiring substrate 41 via the bonding paste 11a (see FIG. 14).

  Subsequently, the bonding paste 11a is cured, and the lead frame 42 and the wiring board 41 are firmly fixed. In the present embodiment, since the bonding paste 11a is made of a thermosetting resin, the base material 40 to which the lead frame 42 is bonded is subjected to a heat treatment (baking process), and the bonding paste 11a is thermally cured, as shown in FIG. The adhesive material 11 is used. The heat treatment temperature is, for example, about 150 ° C to 200 ° C. In this embodiment, the adhesive paste 11a uses an adhesive that does not contain a metal filler, but the adhesive paste 11a is a so-called conductive paste in which a metal filler is contained in a resin. The bonding procedure is the same.

2. Semiconductor chip preparation process;
Further, as the semiconductor chip preparation step (S2) shown in FIG. 10, the semiconductor chip 2 shown in FIG. 8 is prepared. In this step, for example, a semiconductor wafer made of a plurality of semiconductor elements and a wiring layer electrically connected thereto is prepared on the main surface side of a semiconductor wafer made of silicon (not shown). Thereafter, the semiconductor wafer is cut along the dicing line of the semiconductor wafer to obtain a plurality of semiconductor chips 2 shown in FIG.

3. Die bonding process;
Next, the die bonding step (S3) shown in FIG. 10 will be described. 16 is an enlarged plan view showing a state in which an adhesive is disposed on the lead frame shown in FIG. 15. FIG. 17 is an enlarged plan view showing a state in which the semiconductor chip shown in FIG. 8 is mounted on the lead frame shown in FIG. It is. 18 and 19 are enlarged cross-sectional views taken along lines DD and EE in FIG. 17, respectively.

  In this step, first, as shown in FIG. 16, an adhesive paste (die bond material) 12c is applied (arranged) on the lead frame 42 (adhesive material arranging step). Specifically, the adhesive paste 12c is applied from a nozzle (not shown) to a plurality of locations of the lead frame 42 disposed in the chip mounting area 20a of the wiring board 41. More specifically, the adhesive paste 12c is applied on the chip mounting portion 10a and the lead 42c of the lead frame 42. In this embodiment, the size of the chip mounting portion 10a is smaller than the chip mounting area 20a of the wiring substrate 41, and a part of the lead 42c is disposed in the chip mounting area 20a. This is because that.

  The adhesive paste 12c shown in FIG. 16 is, for example, a paste-like adhesive containing a thermosetting resin, and has fluidity before it is cured (thermoset). Further, as shown in FIG. 9, the bonding paste 12c is a so-called conductive paste containing a plurality of metal fillers 12b made of, for example, silver (Ag) particles in a base resin (for example, epoxy resin) 12a. It is.

  Next, as shown in FIGS. 17 to 19, the semiconductor chip 2 is mounted (adhered) on the chip mounting portion 10a (chip mounting step). The semiconductor chip 2 is mounted on the chip mounting region 20a (chip mounting portion 10a) so that the back surface 2b of the semiconductor chip 2 faces the upper surface 21a of the chip mounting region 20a (upper surface 10c of the chip mounting portion 10a) ( Face-up implementation).

  In the chip mounting process, first, the semiconductor chip 2 prepared in the semiconductor chip preparing process (S2) is transferred onto the chip mounting area 20a using a holding jig (not shown). Subsequently, the back surface 2 b of the semiconductor chip 2 is mounted (adhered) close to the upper surface 21 a of the wiring substrate 41. At this time, since the bonding paste 12c has fluidity as described above, when the semiconductor chip 2 is pressed toward the chip mounting portion 10a, the bonding paste 12c is placed on the chip mounting portion 10a and a plurality of leads. Between the surface 42c and the semiconductor chip 2, it spreads in a plane. That is, the semiconductor chip 2 is bonded to the chip mounting portion 10a and the lead 42c of the lead frame 42 through the bonding paste 12c. At this time, the plurality of metal fillers 12b (see FIG. 9) included in the adhesive paste 12c are in close contact with each other as shown in FIG. 9, and connects the back surface 2b of the semiconductor chip 2 and the upper surface 10c of the chip mounting portion 10a. A heat transfer path (and a conductive path) is formed.

  Subsequently, the adhesive paste 12c is cured, and the chip mounting portion 10a of the lead frame 42 and the semiconductor chip 2 are firmly fixed. In the present embodiment, since the bonding paste 12c includes a thermosetting resin, the base material 40 to which the semiconductor chip 2 is bonded is subjected to a heat treatment (baking process), and the bonding paste 12c is heat-cured and bonded. The material 12 is used. The heat treatment temperature is, for example, about 150 ° C to 200 ° C.

4). Wire bonding process;
Next, the wire bonding step (S4) shown in FIG. 10 will be described. 20 is an enlarged plan view showing a state in which the semiconductor chip and the wiring board shown in FIG. 17 are wire-bonded, and FIG. 21 is an enlarged plan view further enlarging the portion F of FIG. FIG. 22 is an enlarged cross-sectional view along the line DD in FIG.

  In this step, as shown in FIG. 20, the wiring substrate 41 and the plurality of semiconductor chips 2 are electrically connected through the wires 3. In this embodiment, as shown in FIGS. 21 and 22, wire bonding is performed by a so-called positive bonding method in which the pads 2c of the semiconductor chip 2 are on the first bond side and the terminals 22 of the wiring board 41 are on the second bond side. The pad 2c and the terminal 22 are electrically connected.

  In the normal bonding method, first, the tip of a wire 3 made of, for example, gold is formed in a ball shape by an electric torch, and this is pressed against the pad 2c on the first bond side with a capillary (not shown) and bonded. Subsequently, while feeding the wire 3, the capillary is moved to the terminal 22 on the second bond side to form a wire loop shape and bonded to the terminal 22. After joining the second bond side, if the excess wire is cut, the pad 2 c and the terminal 22 can be electrically connected via the wire 3.

  In addition, as a method for bonding the first bond side, there are a thermocompression bonding method, an ultrasonic method using ultrasonic vibration, and a combined method using these in combination. In this embodiment, the combined method is used. ing. As shown in FIG. 22, in the present embodiment, the semiconductor chip 2 is mounted on the wiring substrate 41 via the chip mounting portion 10 a of the lead frame 42. Further, as described above, the size of the chip mounting portion 10 a is smaller than the size of the back surface 2 b of the semiconductor chip 2. Further, as shown in FIG. 21, the chip mounting portion 10a has a circular shape in plan view. Therefore, depending on the position of the pad 2c, there is an area where the chip mounting portion 10a or the lead 42c is not disposed immediately below the pad 2c. In this region, a space is formed between the back surface 2b of the semiconductor chip 2 and the wiring board 41. Therefore, if the semiconductor chip 2 is deformed by the pressing force from the capillary during wire bonding, bonding failure or damage to the semiconductor chip 2 occurs. It causes the occurrence of wire bonding failure. Therefore, in the present embodiment, a combined method that can join the wire 3 and the pad 2c with a lower pressing force than other methods is applied.

  The wire 3 is made of metal, and in the present embodiment, is made of, for example, gold (Au). Therefore, as described above, by forming gold (Au) on the surface of the pad 2c of the semiconductor chip 2, the bondability between the wire 3 and the pad 2c can be improved. From the viewpoint of preventing wire bonding defects. preferable.

  As described above, if the chip mounting portion 10a has a quadrangular shape along the shape of the back surface 2b of the semiconductor chip 2 and is substantially the same size as the back surface 2b, the chip mounting is performed immediately below all the pads 2c. Since the portion 10a can be disposed, wire bonding failure can be prevented more reliably.

5. Sealing step;
Next, the sealing step (S5) shown in FIG. 10 will be described. FIG. 23 is an enlarged plan view showing a state in which the semiconductor chip and the wire shown in FIG. 20 are sealed with resin. FIGS. 24, 25, and 26 are enlarged cross-sectional views showing a state in which the base material shown in FIG. 20 is clamped by a molding die, and are respectively a GG line, a HH line in FIG. It is a cross section along line JJ. 27 and 28 are enlarged cross-sectional views showing a state in which the sealing resin is supplied into the cavities shown in FIGS. 24 and 25, respectively.

  The sealing process is a mold preparing process for preparing a molding die, a base material arranging process for placing a base material on which a semiconductor chip is mounted in the molding die, a clamping process for sandwiching and clamping a wiring board with the molding die, A sealing body forming step of supplying a sealing resin into the cavity of the molding die to form a sealing body, a base material taking out step of taking out the base material from the molding die, and a base on which the sealing body is formed It has a baking process which heat-processes to a material and hardens a sealing body.

  In the present embodiment, after the main sealing step, in order to process the plurality of leads 42c of the lead frame 42, each device region 41a is sealed using a molding die in which a cavity is formed for each device region 41a. A sealing method for forming the resin 4 (referred to as an individual mold method) is used. Hereinafter, a method for forming the sealing resin 4 shown in FIG. 23 will be described in detail.

  First, the molding die 50 shown in FIGS. 24, 25, and 26 is prepared (mold preparing step). The molding die 50 has a lower surface 51a, an upper die (die) 51 having a cavity (recessed portion, hollow portion) 51b formed on the lower surface 51a side, and a lower die having an upper surface 52a facing the lower surface 51a ( A mold) 52 is provided. 24 to 26 are enlarged sectional views, and therefore, one cavity 51 b is shown, but the cavity 51 b of the upper mold 51 is formed for each device region 41 a of the wiring board 41. For example, since the wiring board 41 of the present embodiment has six device regions 41a as shown in FIG. 12, the upper mold 51 shown in FIGS. 24 to 26 has six cavities 51b. is doing.

  Each cavity 51b has a substantially rectangular planar shape with four corners chamfered. Further, the upper mold 51 is arranged at a position different from the gate part 51d (see FIG. 24) connected to the runner part 51c, which is a supply path of the sealing resin to the cavity 51b, and the gate part 51d. Air vent portions 51e (see FIGS. 25 and 26) are respectively formed.

  The runner portion 51c and the gate portion 51d connected to the runner portion 51c are formed on one side of a cavity 51b having a substantially square planar shape. The runner 51c extends from the device region 41a of the wiring board 41 toward the suspension 41c as shown in FIG. By forming the runner portion 51c on the hanging portion 41c, it is possible to prevent the sealing resin from leaking into the slit 41d (see FIG. 12) of the wiring board 41 when supplying the sealing resin. .

  Moreover, in this Embodiment, the air vent part 51e (refer FIG. 25, FIG. 26) is each formed in each of the four corner | angular parts of the cavity 51b. For example, the air vent portion 51e can be formed at the opposite corners of the gate portion 51d (see FIG. 24). Yes. In the cavity 51b, the sealing resin flows from the gate portion 51d toward the air vent portion 51e. Therefore, by arranging the air vent portions 51e at the four corner portions, the sealing resin is firmly attached to the corner portions of the cavity 51b. It is because it can be filled.

  In the present embodiment, the film 53 is disposed on the lower surface 51 a side of the upper mold 51. The film 53 is a sheet-like thin film made of, for example, a polyimide resin, and is attached following the shape of the lower surface 51a. For this reason, the cavity 51b, the runner portion 51c, the gate portion 51d, and the air vent portion 51e of the upper mold 51 are covered with the film 53. In this way, by arranging the film 53 on the lower surface 51a side of the upper mold 51 and clamping the wiring substrate 41, the wiring substrate 41 and the film 53 can be firmly adhered to each other. Leakage can be prevented. Moreover, after the sealing resin 4 shown in FIG. 23 is formed, the releasability when taking it out from the molding die 50 is improved.

  Next, in the base material placement step, the base material 40 is placed on the lower mold 52 of the molding die 50. The cavity 51b formed in the upper mold 51 combined with the lower mold 52 has a smaller area than each device region 41a of the wiring board 41, and the peripheral portion of the device region 41a is positioned outside the cavity 51b. Deploy.

  Next, in the clamping step, the distance between the upper mold 51 and the lower mold 52 is reduced, and the wiring board 41 is clamped with the upper mold 51 and the lower mold 52. As a result, the film 53 and the wiring substrate 41 (specifically, the insulating film 26 covering the upper surface 21a of the wiring substrate 41) are in close contact with each other in the regions other than the cavity 51b, the runner portion 51c, the gate portion 51d, and the air vent portion 51e. Further, since the gate part 51d shown in FIG. 24 serves as a sealing resin supply port into the cavity 51b, the film 53 and the wiring board 41 are not in close contact with each other and are separated from each other. In other words, a gap is formed between the film 53 and the wiring board 41 in the gate portion 51d. In addition, the air vent 51e shown in FIGS. 25 and 26 serves as an exhaust port for discharging the gas (air) in the cavity 51b to the outside of the cavity 51b when supplying the sealing resin. The film 53 and the wiring board 41 are not in close contact with each other, and for example, a gap as shown in FIG. 26 is formed. However, the air vent 51e only needs to be able to discharge the gas in the cavity 51b. If the clearance is excessively wide, the supplied sealing resin leaks from the air vent 51e. Therefore, the gap of the air vent part 51e shown in FIG. 26 is narrower than the gap of the gate part 51d shown in FIG.

  Next, in the sealing body forming step, a sealing resin is supplied into the cavity 51b and cured to form a sealing resin. In this step, a resin tablet disposed in a pot portion (not shown) is heated and softened, and a sealing resin is supplied into the cavity 51b from the gate portion 51d shown in FIG. The resin tablet is made of, for example, an epoxy-based resin that is a thermosetting resin, and has a characteristic of being softened by heating and improving fluidity at a temperature lower than the curing temperature. Therefore, for example, when a softened resin tablet is pushed in by a plunger (not shown), the sealing resin flows into the cavity 51b (specifically, on the upper surface 21a side of the wiring board 41) from the gate portion 51d formed in the molding die 50. . The gas in the cavity 51b is discharged from the air vent 51e by the pressure at which the sealing resin flows, and the cavity 51b is filled with the sealing resin 4a shown in FIGS. As a result, the semiconductor chip 2 and the plurality of wires 3 mounted on the upper surface 21a side of the wiring board 41 are sealed with the sealing resin 4a. At this time, the terminals 22 of the wiring board 41 and the leads 42c disposed in the cavity 51b are also sealed.

  Thereafter, by heating the inside of the cavity 51b, the sealing resin 4a is heat-cured (temporarily cured) to form the sealing resin 4 shown in FIG.

  Next, in the base material taking-out step, the base material 40 on which the sealing resin 4 shown in FIG. 23 is formed is taken out from the molding die 50 used in the sealing body forming step.

  Next, in the baking process, the base material 40 taken out from the molding die 50 is conveyed to a baking furnace (not shown), and the base material 40 is heat-treated again. The sealing resin 4a heated in the molding die 50 is in a so-called temporary curing state in which more than half (for example, about 70%) of the curing component in the resin is cured. In this temporarily cured state, not all of the cured components in the resin are cured, but more than half of the cured components are cured, and at this point, the semiconductor chip 2 and the wires 3 are sealed. . However, since it is preferable to completely cure all the curing components from the viewpoint of strength stability of the sealing resin 4, so-called main curing, in which the temporarily cured sealing resin 4 is heated again in the baking step. I do. In this way, by dividing the process of curing the sealing resin 4a into two times, it is possible to quickly perform the sealing process on the next base material 40 that is next conveyed to the molding die 50. For this reason, manufacturing efficiency can be improved.

  Next, the resin 4c formed on the runner portion 51c of the molding die 50 shown in FIG. 27 is removed. Although the removal method is not particularly limited, for example, it can be removed by laser irradiation. Further, if a resin burr is generated by the sealing resin 4a flowing into the air vent 51e (see FIG. 28), it is removed as necessary.

6). Ball mounting process;
Next, the ball mounting step (S6) shown in FIG. 10 will be described. 29 is an enlarged plan view showing a state in which a plurality of solder balls are bonded to the lower surface of the wiring board shown in FIG. 23, and FIG. 30 is an enlarged sectional view taken along the line HH in FIG.

  In this step, a plurality of solder materials (solder balls) 28 are mounted on each of the plurality of lands 24 formed on the lower surface 21b side of the wiring board 41 shown in FIG. More specifically, first, as shown in FIG. 30, the base material 40 is turned upside down, and a plurality of solder materials 28 are respectively disposed on the plurality of lands 24 formed on the lower surface 21 b side of the wiring board 41. Since the lands 24 are arranged in an array (matrix or matrix) on the lower surface 21b, the solder materials 28 are arranged in an array as shown in FIG.

  Here, as described above, in the present embodiment, the plating film 10f shown in FIG. 6 is formed by a so-called tip plating method. For this reason, the exterior plating layer is not formed on the surface of the land 24 shown in FIG. 30, and the opening of the insulating film 27 where the land 24 is exposed is recessed as compared with the surroundings. Therefore, positioning can be easily performed by disposing the ball-shaped solder material 28 in the recess.

  Subsequently, the base material 40 on which the solder material 28 is disposed is subjected to a heat treatment (reflow), and the plurality of solder materials 28 are respectively melted and joined to the plurality of lands 24. In the reflow process, the base material 40 is placed in a reflow furnace and heated to a temperature higher than the melting point of the solder material 28, for example, 260 ° C. or higher. In this step, in order to reliably bond the solder material 28 and the land 24, for example, the bonding is performed by using an activator called a flux. For example, the flux can be removed by coming into contact with an oxide film formed on the surface of the solder material 28, so that the wettability of the solder material 28 can be improved. When bonding is performed using the flux in this way, cleaning is performed to remove the residue of the flux component after the heat treatment.

7). Lead machining process;
Next, the lead processing step (S7) shown in FIG. 10 will be described. In this step, after the connecting portions of the plurality of leads 42c connected to the frame portion 42b of the lead frame 42 are cut, the leads 42c are bent and molded. Subsequently, the tip of the lead 42c is cut to form the heat dissipation lead 10b shown in FIG.

  First, a plurality of leads 42c connected to and integrated with the frame portion 42b shown in FIG. 31 are cut at the connecting portions to form independent members (lead cutting step). 31 is an enlarged plan view showing the upper surface side of the substrate shown in FIG. 29, and FIG. 32 is an enlarged cross-sectional view taken along the line KK of FIG.

  In the lead cutting process, for example, as shown in FIG. 32, a die (support member) 61 is disposed on the lower surface side of the lead frame 42 and a punch (cutting blade) 62 is disposed on the upper surface side, and the lead 42c is cut by pressing. To do. The punch 62 is disposed at a position overlapping the gap formed in the die 61. When the punch 62 is pushed down toward the gap of the die 61, the lead 42c can be cut. Here, in the present embodiment, the wiring substrate 41 is fixed to the lower surface side of the lead frame 42. However, since the cut portion of the lead 42c is disposed on the slit 41d of the wiring substrate 41, the punch 62 and The die 61 can be brought into contact with the lead 42c that is the object to be cut.

  In this step, the solder material 28 is already formed. However, a recess 60a is formed in the stage 60 shown in FIG. Specifically, the stage 60 includes a substrate support portion 60b that abuts on the lower surface side of the wiring substrate 41, and a recess portion 60a that is formed on the inner side with respect to the wiring substrate 41 than the substrate support portion 60b. For this reason, the damage of the solder material 28 in this process can be prevented by arranging the base material 40 so that the solder material 28 is positioned in the recess 60a.

  Next, the plurality of cut leads 42c are bent and molded (bending step). 33 is an enlarged cross-sectional view showing a state in which the base material shown in FIG. 32 is arranged in a lead bending apparatus, and FIG. 34 is an enlarged cross-sectional view showing a state in which the lead shown in FIG. 33 is bent.

  As shown in FIG. 34, in the present embodiment, the lead 42c is bent in the direction of the lower surface of the wiring board 41 and formed into a gull wing shape. As shown in FIG. 5, the gull wing is formed in order to join the heat dissipation leads 10 b and the lands 31 of the mounting substrate 30 when the semiconductor device 1 is mounted on the mounting substrate 30 (surface mounting).

  In the bending process, first, as shown in FIG. 33, a die including a die (first support member) 63a disposed on the upper surface side of the lead 42c and a die (second support member) 63b disposed on the lower surface side of the lead 42c. The lead 42c is sandwiched by (a bending support member, support member) 63, and the lead 42c is fixed. The fixing position of the lead 42c is located outside the wiring board 41 as shown in FIG. In other words, the lead 42c is sandwiched between the dies 63a and 63b at a position where the lead 42c protrudes from the wiring board 41. This is because the die 63b is brought into contact with the lower surface side of the lead 42c. Further, the surface of the die 63b facing the lead 42c is formed corresponding to the shape of the lead 42c (in this embodiment, the gull wing shape).

  Next, bending is performed by pressing with a punch (pressing member) 64 from the upper surface side of the lead 42 c fixed by the die 63. The surface of the punch 64 facing the lead is formed to follow the shape of the surface of the die 63b facing the lead 42c. When the punch 64 is pushed down toward the die 63b, the lead 42c is wired as shown in FIG. It is bent in the direction of the lower surface of the substrate 41 and formed into a predetermined shape (in this embodiment, a gull wing shape).

  In the present embodiment, the processing is performed in a state where the length of the lead 42c is longer than the required length from the viewpoint of improving the stability of the bending processing. That is, the length of the lead 42c shown in FIGS. 33 and 34 is longer than the heat radiation lead 10b of the finally obtained semiconductor device 1 (see FIG. 1).

  In addition, similarly to the stage 60 shown in FIG. 32, a recessed portion 60a and a substrate support portion 60b are also formed in the stage 65 that performs lead bending. Therefore, by disposing the base material 40 so that the solder material 28 is located in the recess 60a, damage to the solder material 28 in this step can be prevented.

  Next, the tip of the lead 42c is cut, and the length of the lead 42c is shortened to form the heat dissipation lead 10b shown in FIG. 1 (lead tip cutting step). 35 is an enlarged cross-sectional view showing a state in which the base material shown in FIG. 34 is arranged in a lead tip cutting device, and FIG. 36 is an enlarged cross-sectional view showing a state in which the lead tip shown in FIG. 35 is cut. FIG. 37 is an enlarged plan view showing a state after the lead shown in FIG. 31 is subjected to the lead processing step shown in FIG.

  In this lead tip cutting step, first, as shown in FIG. 35, a die (first support member) 66a disposed on the upper surface side of the lead 42c and a die (second support member) 66b disposed on the lower surface side of the lead 42c are provided. The lead 42c is sandwiched and fixed by a die (bending support member, support member) 66 provided. Next, as shown in FIG. 36, the tip of the lead 42c is cut by pressing with a punch (cutting blade) 67 from the upper surface side of the lead 42c fixed by the die 66.

  In this lead tip cutting process, since cutting is performed by press working, the end portion of the cut lead 42c has a substantially flat cut surface, and the heat radiating lead 10b is formed from the plating film 10f (see FIG. 6) on the cut surface. Exposed.

  Further, similarly to the stage 60 shown in FIG. 32, a recess portion 60a and a substrate support portion 60b are also formed on the stage 68 for performing lead bending. Therefore, by disposing the base material 40 so that the solder material 28 is located in the recess 60a, damage to the solder material 28 in this step can be prevented.

  When the lead cutting process, the bending process, and the lead tip cutting process described above are performed on each of the plurality of leads 42c shown in FIG. 31, they are separated from the lead frame 42 as shown in FIG. A plurality of formed heat dissipation leads 10b are obtained.

8). Individualization step;
Next, the individualizing step (S8) shown in FIG. 10 will be described. FIG. 38 is an enlarged plan view showing a state in which the base material shown in FIG. 37 is separated for each device region, and FIG. 39 is an enlarged cross-sectional view showing the individualization step, taken along line LL in FIG. FIG.

  In this step, the suspension part 41c connected to the frame part (frame body) 41b of the wiring substrate 41 is cut, and is separated into pieces for each device region 41a to obtain a plurality of semiconductor devices 1. For example, as shown in FIG. 39, a means for cutting the suspension portion 41c is arranged by pressing a die (support member) 71 on the lower surface side of the wiring board 41 and a punch (cutting blade) 72 on the upper surface side. The hanging part 41c is cut. The punch 72 is disposed at a position overlapping the gap formed in the die 71. When the punch 72 is pushed down toward the gap of the die 71, the hanging portion 41c is cut.

  Here, as shown in FIG. 12, the wiring board 41 according to the present embodiment has a hanging portion 41c disposed between two long sides of the frame portion 41b and each device region 41a, and between each device region 41a. The hanging part 41c is not arranged between the device region 41a and the short side of the frame part 41b. Therefore, in the singulation process, the number of cut portions can be reduced, and the manufacturing efficiency is improved.

  In dividing into pieces, the efficiency is further improved by providing a cut or the like at the cutting position of the wiring board. Moreover, a router process etc. can also be used without using a cutting die.

  Further, as shown in FIG. 39, the die 71 has a substrate support portion 71 a that supports the lower surface side of the wiring substrate 41, and a recess portion 71 b that is positioned inside the substrate support portion 71 a with respect to the wiring substrate 41. ing. Therefore, by disposing the base material 40 so that the solder material 28 is positioned in the recess 71b, damage to the solder material 28 in this step can be prevented. In addition, since the semiconductor device 1 after being cut is held by the substrate support portion 71a, for example, by picking up the sealing resin 4 with a suction jig (not shown), the next process (inspection process or packaging process) is performed. Can be transported.

  Thereafter, necessary inspections and tests such as an appearance inspection are performed, and the semiconductor device 1 is completed.

(Embodiment 2)
40 is a plan view showing a modification of the semiconductor device shown in FIG. 2 described in the first embodiment. The difference between the semiconductor device 80 shown in FIG. 40 and the semiconductor device 1 shown in FIG. 2 is the shape of the chip mounting portion 80 a of the heat dissipation member 10. Since the other configuration of the semiconductor device 80 of the present embodiment is the same as that of the semiconductor device 1 described in the first embodiment, a duplicate description is omitted, and the description is given in the first embodiment as necessary. This will be described with reference to the drawings.

  The chip mounting portion 80a of the heat dissipation member 10 of the semiconductor device 80 has a quadrangular shape along the shape of the back surface 2b of the semiconductor chip 2 (see FIG. 3). Further, the chip mounting portion 80a has substantially the same size as the back surface 2b of the semiconductor chip 2, and as shown in FIG. 40, all the pads 2c of the semiconductor chip 2 are arranged on the chip mounting portion 80a.

  Thus, by disposing the chip mounting portion 10a immediately below all the pads 2c, it is possible to more reliably prevent the wire bonding failure in the wire bonding process described in the first embodiment.

  However, in order to make the sizes of the semiconductor chip 2 and the chip mounting portion 80b uniform, it is necessary to change the size of the chip mounting portion 80b in accordance with the planar dimensions of the semiconductor chip 2. Therefore, from the viewpoint of versatility of the lead frame 42 (see FIG. 13) described in the first embodiment, the circular chip mounting portion 10a (see FIG. 2) is used as described in the first embodiment. Is preferred.

(Embodiment 3)
41 is a plan view showing a modification of the semiconductor device shown in FIG. 2 described in the first embodiment. The difference between the semiconductor device 81 shown in FIG. 41 and the semiconductor device 1 shown in FIG. 2 is the shape and planar size of the chip mounting portion 81a of the heat dissipation member 10. The second difference is the arrangement of pads 2c and terminals 22 and the number of terminals. Since the other configuration of the semiconductor device 81 of the present embodiment is the same as that of the semiconductor device 1 described in the first embodiment, a duplicate description is omitted, and the description has been given in the first embodiment as necessary. This will be described with reference to the drawings.

  The chip mounting portion 81a of the heat dissipation member 10 of the semiconductor device 81 has a quadrangular shape along the shape of the back surface 2b of the semiconductor chip 2 (see FIG. 3). The chip mounting portion 81 a has a larger planar dimension than the back surface 2 b of the semiconductor chip 2, and the outer edge portion of the chip mounting portion 81 a is located outside the outer edge portion of the semiconductor chip 2.

  As described above, when the planar dimension of the chip mounting portion 81a is larger than the planar dimension of the semiconductor chip 2, as shown in FIG. 41, all the pads 2c of the semiconductor chip 2 are arranged on the chip mounting portion 81a. Become. Therefore, as described in the second embodiment, wire bonding defects in the wire bonding process can be prevented more reliably.

  In addition, from the viewpoint of heat dissipation characteristics, compared to the semiconductor device 1 described in the first embodiment, the cross-sectional area of the heat dissipation path can be increased, so that the heat dissipation characteristics can be improved.

  However, as shown in FIG. 41, when the chip mounting portion 81a is larger than the semiconductor chip 2, it is necessary to arrange the terminals 22 while avoiding the chip mounting portion 81a, so that the arrangement of the terminals 22 is restricted. For this reason, in the semiconductor device 81 of the third embodiment, as shown in FIG. 41, a plurality of terminals 22 are arranged in one row along each side of the semiconductor chip 2 having a rectangular planar shape. . Accordingly, the number of pads 2c of the semiconductor chip 2 is reduced as compared with the semiconductor device 1 of the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment, the heat radiation lead 10a of the semiconductor device is formed in a gull wing shape and surface-mounted on the mounting substrate 30. However, the shape of the heat radiation lead is not limited to this. FIG. 42 is an enlarged cross-sectional view showing a modification of the electronic device shown in FIG.

  For example, it may be a pin type shape that extends below the solder material 28, such as a heat dissipation lead 82b of the semiconductor device 82 shown in FIG. In this case, as shown in FIG. 42, holes can be formed in the terminals 84 of the mounting substrate 83 to which the heat radiation leads 82b are joined, and the heat radiation leads 82b can be inserted into the holes and joined by the joining member 32.

  Further, for example, in the first embodiment, as a lead processing step, a plurality of leads 42c that are respectively connected and integrated with the frame portion 42b are cut at the connecting portions to form independent members, and then bending is performed. The embodiment of performing the process has been described. However, the lead cutting process described in the first embodiment may be omitted, and the bending process may be performed in a state where the plurality of leads 42c are connected to the frame portion 42b. In this case, since a part of the lead 42c is stretched and bent when the bending process is performed, it is preferable that the length of the lead 42c is longer than that shown in FIG. Therefore, although the dimension of the lead frame 42 becomes larger than that of the first embodiment, the manufacturing efficiency can be improved by omitting the lead cutting step. However, from the viewpoint of the strength of the lead frame 42, it is preferable to shorten the length of the lead 42c. In this respect, as described in the first embodiment, a lead cutting process is performed before the bending process. It is preferable.

  The present invention is applicable to a semiconductor device in which a semiconductor chip is mounted on a wiring board and the semiconductor chip is sealed with a resin.

DESCRIPTION OF SYMBOLS 1, 80, 81, 82 Semiconductor device 2 Semiconductor chip 2a Main surface 2b Back surface 2c, 2d, 2e Pad 3 Wire 4 Sealing resin 4a Sealing resin 4c Resin 10 Heat radiation member 10a, 80a, 81a Chip mounting part 10b, 82b Radiation lead 10c Upper surface 10d Lower surface 10e Main material 10f Plating film (exterior plating layer)
11, 12 Adhesives 11a, 12c Adhesive paste 12a Base resin 12b Metal filler 20 Wiring board 20a Chip mounting area 21 Insulating layer 21a Upper surface 21b Lower surface 22 Terminals 23, 23a, 23b Wiring 24 Land 25 Via (through hole)
25a In-via wiring 26, 27 Insulating film 26a Opening 28 Solder material 30, 83 Mounting substrate 31, 33, 34 Land 32 Bonding member 35, 36 Wiring 40 Base material 41 Wiring substrate 41a Device region 41b Frame (frame)
41c Hanging part 41d Slit 42 Lead frame 42a Device region 42b Frame part 42c Lead 42d Reinforcing lead 50 Mold 51 Upper mold 51a Lower surface 51b Cavity 51c Runner part 51d Gate part 51e Air vent part 52 Lower mold 52a Upper surface 53 Film 60 65, 68 Stages 60a, 71b Recessed portions 60b, 71a Substrate support portions 61, 63, 63a, 63b, 66, 71 Dies 62, 64, 72 Punch 84 Terminal 100 Semiconductor device 101 Land 102 Wiring 103 Wiring

Claims (19)

A rectangular upper surface, a lower surface opposite to the upper surface, a plurality of terminals formed on the upper surface, and a plurality of lands formed on the lower surface and electrically connected to the plurality of terminals. A wiring board having,
A chip mounting portion, a plurality of leads extending from the chip mounting portion toward the outer edge of the wiring board, and mounted on the wiring board via a first adhesive;
The chip has a main surface, a plurality of electrodes formed on the main surface, and a back surface opposite to the main surface, and the back surface faces the chip mounting portion via a second adhesive. A semiconductor chip mounted on the mounting portion;
A plurality of conductive members that electrically connect the plurality of electrodes and the plurality of terminals, respectively;
On the wiring board, a sealing body that seals the semiconductor chip and the plurality of conductive members;
Have
Some of the leads are exposed from the sealing body,
The semiconductor device, wherein the heat dissipation member is made of a material having a higher thermal conductivity than the sealing body. In claim 1,
The plurality of leads extend from the chip mounting portion toward each corner of the wiring board, and are led out below the land on the outside of the wiring board. . In claim 2,
The plurality of terminals are arranged in a plurality of rows on the outside of the semiconductor chip along each side of the semiconductor chip having a quadrangular shape in plan view. In claim 3,
The chip mounting portion of the heat dissipation member is covered with the back surface of the semiconductor chip. In claim 4,
The semiconductor device, wherein the plurality of leads arranged on the wiring board are fixed to the wiring board via the first adhesive. In claim 5,
The chip mounting portion of the heat radiating member and the plurality of leads are fixed on an insulating film covering the uppermost layer wiring of the wiring board. In claim 1,
The plurality of leads are formed thicker than the plurality of wirings formed on the wiring board. In claim 1,
The semiconductor device is characterized in that the plurality of leads are formed with a width wider than the plurality of wires formed on the wiring board. In claim 1,
The second adhesive material includes a base resin and a plurality of metal fillers having higher thermal conductivity than the base resin.   2. The semiconductor device according to claim 1, wherein the number of the plurality of leads is smaller than that of the plurality of lands. In claim 2,
The plurality of lands are arranged in a matrix on the lower surface of the wiring board, and a signal current or an analog circuit current flows through a first land disposed on the outermost periphery of the lower surface. . (A) a first frame part, a plurality of suspension parts connected to the first frame part, and a plurality of device regions arranged inside the first frame part in plan view and supported by the plurality of suspension parts And a plurality of leads connected to the second frame portion, and a plurality of leads disposed inside the second frame portion in plan view and supported by the plurality of leads. A step of preparing a base material fixed via a first adhesive so that a lead frame having a chip mounting portion is arranged on the plurality of device regions in a plurality of device mounting portions in plan view,
(B) a plurality of semiconductor chips having a main surface, a plurality of electrodes formed on the main surface, and a back surface opposite to the main surface, the back surface facing the chip mounting portion, Mounting on a plurality of chip mounting portions via a second adhesive,
(C) electrically connecting the plurality of electrodes and a plurality of terminals formed in each device region of the wiring board via a plurality of conductive members;
(D) forming a sealing body in each device region of the wiring board so that a part of the plurality of leads is exposed, and sealing the plurality of semiconductor chips and the plurality of conductive members;
(E) cutting the plurality of leads outside the device regions and separating the leads from the second frame portion;
(F) cutting the plurality of suspension portions of the wiring board to singulate the plurality of device regions;
Including
Between the device regions adjacent to each other among the plurality of device regions in the wiring substrate prepared in the step (a), a slit penetrating from the upper surface to the lower surface of the wiring substrate is formed,
A method of manufacturing a semiconductor device, wherein a part of the plurality of leads in the lead frame prepared in the step (a) is disposed on the slit. In claim 12,
In the step (e),
(E1) cutting the plurality of leads outside the device regions;
(E2) a step of bending the plurality of leads toward the lower surface of the wiring board outside the device regions;
Is included, a method for manufacturing a semiconductor device. In claim 12,
The plurality of leads of the base material prepared in the step (a) are made of a main material having a higher thermal conductivity than the sealing body formed in the step (d),
A method of manufacturing a semiconductor device, wherein an exterior plating layer made of a material having higher wettability to solder than the main material is formed in advance on the surfaces of the plurality of leads. In claim 12,
The plurality of leads of the base material prepared in the step (a) extend from the chip mounting portion toward a corner portion of the device region of the wiring board having a quadrangular planar shape. A method for manufacturing a semiconductor device. In claim 12,
In the step (a),
(A1) applying the paste-like first adhesive on the device region of the wiring board;
(A2) a step of superimposing and bonding the lead frame on the paste-like first adhesive;
(A3) curing the paste-like first adhesive;
Contains
In the step (a1), the paste-like first adhesive is applied to the position where the chip mounting portion of the lead frame is disposed and the position where the plurality of leads are disposed in the step (a2). A method of manufacturing a semiconductor device. In claim 12,
In the step (b),
(B1) applying the paste-like second adhesive material to the chip mounting portion;
(B2) a step of bonding the semiconductor chip onto the paste-like second adhesive;
(B3) curing the paste-like second adhesive;
Contains
The method for manufacturing a semiconductor device, wherein the second adhesive material includes a base resin and a plurality of metal fillers having higher thermal conductivity than the base resin. In claim 12,
The first frame portion of the wiring board of the base material prepared in the step (a) has a rectangular outer shape,
The wiring board is
A suspension portion is disposed between the two long sides of the first frame portion and each device region,
The method of manufacturing a semiconductor device, wherein the suspension portion is not disposed between the device regions and between the device region and a short side of the first frame portion. A mounting substrate having an upper surface and a plurality of first and second lands formed on the upper surface;
A semiconductor device mounted on the upper surface of the mounting substrate,
The semiconductor device includes:
A rectangular upper surface, a lower surface opposite to the upper surface, a plurality of terminals formed on the upper surface, and formed on the lower surface, electrically connected to the plurality of terminals, and A wiring board having a plurality of lands electrically connected to the plurality of first lands;
A chip mounting portion, and a plurality of leads extending from the chip mounting portion toward each corner of the wiring board and joined to the plurality of second lands of the mounting board outside the wiring board. A heat dissipation member mounted on the wiring board via a first adhesive;
The chip has a main surface, a plurality of electrodes formed on the main surface, and a back surface opposite to the main surface, and the back surface faces the chip mounting portion via a second adhesive. A semiconductor chip mounted on the mounting portion;
A plurality of conductive members that electrically connect the plurality of electrodes and the plurality of terminals, respectively;
On the wiring board, a sealing body that seals the semiconductor chip and the plurality of conductive members;
Have
Some of the leads are exposed from the sealing body,
The heat dissipation member is made of a material having a higher thermal conductivity than the sealing body.

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