CN115602656B - Semiconductor assembly, preparation method thereof and semiconductor device - Google Patents

Semiconductor assembly, preparation method thereof and semiconductor device Download PDF

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Publication number
CN115602656B
CN115602656B CN202211590512.9A CN202211590512A CN115602656B CN 115602656 B CN115602656 B CN 115602656B CN 202211590512 A CN202211590512 A CN 202211590512A CN 115602656 B CN115602656 B CN 115602656B
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carrier plate
electric carrier
electrode
semiconductor device
electric
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CN115602656A (en
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朱益峰
曹凯
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Innoscience Suzhou Semiconductor Co Ltd
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Innoscience Suzhou Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention discloses a semiconductor component, a preparation method thereof and a semiconductor device, wherein the semiconductor component comprises: the first electric carrier plate and the second electric carrier plate; the first electrode of the semiconductor device is electrically connected with the first electric carrier plate, and the second electrode of the semiconductor device is electrically connected with the second electric carrier plate; the packaging body wraps the semiconductor device, the junction of the first electrode and the first electric carrier plate and the junction of the second electrode and the second electric carrier plate; the first electric carrier plate is provided with a first heat dissipation part, the second electric carrier plate is provided with a second heat dissipation part, and at least a part of the electric connection part, the first heat dissipation part and the second heat dissipation part are exposed out of the packaging body. According to the semiconductor component provided by the embodiment of the invention, two heat dissipation paths can be formed, the heat conduction area of the semiconductor device is increased, and the heat dissipation efficiency of the semiconductor device is further improved, so that the internal temperature of the semiconductor device can be limited to be not more than a certain value, and the use reliability of the semiconductor component is improved.

Description

Semiconductor assembly, preparation method thereof and semiconductor device
Technical Field
The present invention relates to the field of semiconductor packaging technology, and in particular, to a semiconductor assembly, a method for manufacturing the same, and a semiconductor device.
Background
Document CN111933598A discloses a heat-dissipating semiconductor package product, which comprises a chip carrier, a chip and a packaging colloid, wherein the chip is fixed in a core carrying area of the chip carrier, an electrode of the chip is connected with the chip carrier through a metal wire, the packaging colloid wraps the chip and is connected with the chip carrier, and a metal heat-dissipating tube is arranged on one side of the chip carrier, which is opposite to the chip.
Furthermore, document CN201616430U discloses a package structure of an integrated circuit, wherein a chip and a pin are disposed on a side surface of a chip carrier, the chip and the chip carrier are bonded together by solder, an insulating pad is disposed between the pin and the chip carrier, the pin is electrically connected to the chip through a connecting wire, and the chip carrier are covered by the package colloid.
In the two schemes, as the bottom of the chip is contacted with the chip carrier plate, the side part and the top of the chip are contacted with the packaging colloid, so that the heat generated by the chip is not easy to dissipate, and the service performance of the chip is affected.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, an object of the present invention is to propose a semiconductor assembly which is high in reliability and heat dissipation efficiency.
The invention also provides a semiconductor device with the semiconductor component.
The invention also provides a preparation method of the semiconductor component.
A semiconductor assembly according to an embodiment of the first aspect of the present invention includes: the first electric carrier plate and the second electric carrier plate are respectively provided with an electric connection part connected with an external circuit; the semiconductor device is arranged between the first electric carrier plate and the second electric carrier plate, a first electrode of the semiconductor device is electrically connected with the first electric carrier plate, and a second electrode of the semiconductor device is electrically connected with the second electric carrier plate; the packaging body wraps the semiconductor device, the connection part of the first electrode and the first electric carrier plate and the connection part of the second electrode and the second electric carrier plate; the first electric carrier plate is provided with a first heat dissipation part, the second electric carrier plate is provided with a second heat dissipation part, and at least a part of the electric connection part, the first heat dissipation part and the second heat dissipation part are exposed out of the packaging body.
According to the semiconductor assembly provided by the embodiment of the invention, the first electric carrier plate and the second electric carrier plate which are electrically connected with the semiconductor device are arranged, at least one part of the first electric carrier plate is exposed out of the packaging body to form the first heat dissipation part, at least one part of the second electric carrier plate is exposed out of the packaging body to form the second heat dissipation part, and therefore heat dissipation can be carried out through the first heat dissipation part and the second heat dissipation part, namely two heat dissipation paths are formed, the heat conduction area of the semiconductor device is increased, the heat dissipation efficiency of the semiconductor device is further improved, the internal temperature of the semiconductor device can be limited to be not more than a certain value, and the use reliability of the semiconductor assembly is improved.
According to some embodiments of the invention, the semiconductor device is mounted on the first electric carrier, the first heat dissipation portion forms a first heat dissipation surface, and a projection of the first electrode on a plane where the first heat dissipation surface is located is at least partially overlapped with the first heat dissipation surface.
In some embodiments, a projection of the first electrode on a plane of the first radiating surface is located in the first radiating surface.
In some embodiments, the first heat dissipating surface is flush with an outer surface of the package.
In some embodiments, a projection of the second electrode on a plane of the first radiating surface is at least partially coincident with the first radiating surface.
In some examples, a projection of the second electrode on a plane in which the first cooling surface lies is located within the first cooling surface.
According to some embodiments of the invention, the semiconductor assembly further comprises: and one end of the first connecting piece is electrically connected with the first electrode, the other end of the first connecting piece is electrically connected with the first electric carrier plate, and the packaging body wraps the first connecting piece.
In some examples, a first connection layer is disposed between the one end of the first connection member and the first electrode, and between the other end of the first connection member and the first electrical carrier plate.
According to some embodiments of the invention, the semiconductor assembly further comprises: and one end of the second connecting piece is electrically connected with the second electrode, the other end of the second connecting piece is electrically connected with the second electric carrier plate, and the second connecting piece is wrapped by the packaging body.
In some embodiments, the second heat dissipation portion forms a second heat dissipation surface, and a projection of the other end of the second connecting piece on a plane where the second heat dissipation surface is located is at least partially overlapped with the second heat dissipation surface.
In some examples, a projection of the other end of the second connection member on a plane in which the second heat dissipating surface is located in the second heat dissipating surface.
In some examples, the second heat dissipating surface is flush with an outer surface of the package.
In some embodiments, the second connector forms a metal connection post.
In some examples, the cross-sectional dimension of the other end of the second connector is greater than the cross-sectional dimension of the middle portion of the second connector.
According to some specific embodiments of the invention, each of the first and second electrical carrier plates comprises: the carrier plate body of the first electric carrier plate and the carrier plate body of the second electric carrier plate are opposite to each other and are arranged at intervals, and the first heat dissipation part/the second heat dissipation part is positioned on the carrier plate body; the semiconductor device is arranged between the two carrier plate bodies, the first electrode is connected with the electric connection part of the first electric carrier plate, and the second electrode is electrically connected with the carrier plate bodies of the second electric carrier plate.
In some examples, two opposite side surfaces of the carrier body expose the package body to form the first heat dissipation portion and the second heat dissipation portion, respectively.
In some examples, the electrical connection portion includes pins, one ends of the two pins are connected to the corresponding peripheral edge of the carrier body through connection segments, and the other ends of the two pins extend out of two opposite sides of the package body.
In some specific examples, the two connection sections extend obliquely in a direction away from each other and in a direction away from the carrier plate body.
In some specific examples, the pins of each of the first and second electrical carrier plates are bent toward the first or second heat dissipation portion by a cut-and-rib bending process.
In some specific examples, the pins of each of the first and second electrical carrier plates are flush with the first or second heat sink.
According to some embodiments of the invention, the first and second electrical carrier plates are metal frames.
A semiconductor device according to an embodiment of a second aspect of the present invention includes: the semiconductor assembly according to the above embodiment; and the radiator is arranged on the first radiating part or the second radiating part.
According to the semiconductor device provided by the embodiment of the invention, the semiconductor component and the radiator are adopted, so that the radiating efficiency of the semiconductor device can be improved, the internal temperature of the semiconductor device can be limited to be not more than a certain value, and the use reliability of the semiconductor component can be improved.
A method for manufacturing a semiconductor assembly according to an embodiment of the third aspect of the present invention includes the steps of: providing a semiconductor device, a first electric carrier plate and a second electric carrier plate; mounting the semiconductor device on the first electric carrier plate, and electrically connecting a first electrode of the semiconductor device with the first electric carrier plate; the second electric carrier plate is arranged on one side, facing away from the first electric carrier plate, of the semiconductor device, and a second electrode of the semiconductor device is electrically connected with the second electric carrier plate, so that a preassembled structure is obtained; encapsulating the pre-fabricated structure to form an encapsulation outside the pre-fabricated structure; the first electric carrier plate is provided with a first heat dissipation part, the second electric carrier plate is provided with a second heat dissipation part, the first electric carrier plate and the second electric carrier plate are provided with electric connection parts, and the first heat dissipation part, the second heat dissipation part and the electric connection parts are exposed out of the packaging body.
According to the manufacturing method of the semiconductor component, the first electric carrier plate and the second electric carrier plate which are electrically connected with the semiconductor device are arranged, at least one part of the first electric carrier plate is exposed out of the packaging body to form the first radiating part, at least one part of the second electric carrier plate is exposed out of the packaging body to form the second radiating part, and therefore heat can be radiated through the first radiating part and the second radiating part, namely two radiating paths are formed, the heat conducting area of the semiconductor device is increased, the radiating efficiency of the semiconductor device is further improved, the internal temperature of the semiconductor device can be limited to be not more than a certain value, and the use reliability of the semiconductor component is improved.
According to some embodiments of the invention, the electrically connecting the first electrode of the semiconductor device with the first electrical carrier plate comprises: and connecting the first electrode with the electric connection part of the first electric carrier plate by adopting a first connecting piece.
In some embodiments, the first connector forms a metal wire or a metal tab.
According to some embodiments of the invention, the electrically connecting the second electrode of the semiconductor device with the second electrical carrier plate comprises: and connecting the second electrode with the second electric carrier plate by adopting a second connecting piece.
In some embodiments, the second connector forms a metal connection post.
According to a further embodiment of the present invention, the electrical connection portion includes a pin, and after the pre-packaged structure is packaged by using a packaging process, the method further includes: and bending pins of each of the first electric carrier plate and the second electric carrier plate towards the first heat dissipation part or the second heat dissipation part by adopting a rib cutting and bending process.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural view of a semiconductor assembly according to an embodiment of the present invention;
fig. 2 is a schematic structural view of a semiconductor assembly according to another embodiment of the present invention;
fig. 3 is a schematic structural view of a first electric carrier of a semiconductor assembly according to an embodiment of the present invention;
fig. 4 is a schematic view of a structure in which a semiconductor device of a semiconductor assembly according to an embodiment of the present invention is mounted on a first electric carrier plate;
Fig. 5 is a schematic structural view of a semiconductor device of a semiconductor assembly according to an embodiment of the present invention electrically connected to a first electric carrier through a first connection member;
fig. 6 is a schematic structural view of a first electric carrier plate, a semiconductor device, a first connection member and a second connection member of a semiconductor assembly according to an embodiment of the present invention;
fig. 7 is a schematic view of a pre-assembled structure of a semiconductor assembly according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a semiconductor assembly after pre-packaged structure packaging in accordance with an embodiment of the present invention;
fig. 9 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Reference numerals:
the semiconductor device 100 is formed such that,
the first electric carrier plate 11, the first heat dissipation part 111,
the second electrical carrier 12, the second heat sink 121,
carrier body 131, connecting section 132, electrical connection 133,
the semiconductor device 20, the first electrode 21, the second electrode 22,
the package 30, the first connector 41, the second connector 42,
a thermally conductive connection layer 51, a first connection layer 52, a second connection layer 53.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the embodiments of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like should be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; or may be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention will be understood by those of ordinary skill in the art according to specific circumstances.
The manufacturing process of semiconductor products is generally divided into eight steps: wafer processing, oxidization, photoetching, etching, film deposition, interconnection, testing and packaging.
Wafer processing refers to cutting the single crystal pillars made into wafer slices. The oxidation process refers to the flow of oxygen or vapor over the wafer surface to form an oxide layer. Photolithography refers to "printing" a circuit pattern onto a wafer by light, and after the circuit pattern is etched on the wafer, an etching process is required to remove the excess oxide film, leaving only the circuit pattern. In order to create micro devices inside the chip, it is necessary to continuously deposit a layer of thin film and remove the excess portion thereof by etching, thereby finally forming a multi-layered semiconductor structure. Then, they are connected to realize the transmission and reception of power and signals, and then, whether the quality of the semiconductor chip reaches a certain standard is checked by testing, so that bad products are eliminated and the reliability of the chip is improved.
The wafer processed by the process can form square chips with equal size, then the individual chips are obtained by cutting, and finally the cut chips are packaged by adopting a packaging process, wherein the packaging refers to a shell for mounting a semiconductor device, which not only plays roles of placing, fixing, sealing and protecting the semiconductor device, but also is connected to pins of the packaging shell through wires for connecting the semiconductor device with a bridge of an external circuit, namely the joints on the semiconductor device, and the pins are connected with other devices through wires on a printed board.
When the semiconductor device is in operation, if the power consumption exceeds a critical value, the thermal instability and the thermal breakdown are caused, and many parameters of the semiconductor device are also adversely affected due to the temperature rise, so that the package structure needs to ensure the heat dissipation performance to limit the internal temperature of the semiconductor device not to exceed a certain value on the basis of ensuring the fixation and the sealing.
Document CN111933598A discloses a heat-dissipating semiconductor package product, which comprises a chip carrier, a chip and a packaging colloid, wherein the chip is fixed in a core carrying area of the chip carrier, an electrode of the chip is connected with the chip carrier through a metal wire, the packaging colloid wraps the chip and is connected with the chip carrier, and a metal heat-dissipating tube is arranged on one side of the chip carrier, which is opposite to the chip.
Document CN201616430U discloses a package structure of an integrated circuit, where a chip and a pin are disposed on a surface of one side of a chip carrier, the chip and the chip carrier are bonded together by solder, an insulating pad is disposed between the pin and the chip carrier, the pin is electrically connected to the chip through a connection wire, and the chip carrier are covered by the package colloid.
In the two schemes, as the bottom of the chip is contacted with the chip carrier plate, the side part and the top of the chip are contacted with the packaging colloid, so that the heat generated by the chip is not easy to dissipate, and the service performance of the chip is affected. Therefore, the invention provides a semiconductor component, a preparation method thereof and a semiconductor device, which increase the effective heat conduction area and improve the heat dissipation efficiency, thereby limiting the internal temperature of the semiconductor component not to exceed a certain value and improving the use reliability.
A semiconductor assembly 100 according to an embodiment of the present invention is described below with reference to fig. 1-8.
As shown in fig. 1 and 2, a semiconductor assembly 100 according to an embodiment of the present invention includes a first electrical carrier 11, a second electrical carrier 12, and a semiconductor device 20.
The first electric carrier plate 11 and the second electric carrier plate 12 have electric connection portions 133, respectively, so that an external circuit can be connected through the electric connection portions 133, the semiconductor device 20 is provided between the first electric carrier plate 11 and the second electric carrier plate 12, the first electrode 21 of the semiconductor device 20 is electrically connected to the first electric carrier plate 11, and the second electrode 22 of the semiconductor device 20 is electrically connected to the second electric carrier plate 12.
Further, the semiconductor assembly 100 further includes a package body 30, where the package body 30 wraps the semiconductor device 20, the connection between the first electrode 21 and the first electric carrier plate 11, and the connection between the second electrode 22 and the second electric carrier plate 12, that is, the package body 30 forms a housing of the semiconductor assembly 100, so that the connection between the semiconductor device 20, the first electrode 21 and the first electric carrier plate 11, and the connection between the second electrode 22 and the second electric carrier plate 12 can be protected, on one hand, the semiconductor device 20 can be isolated from the outside, and impurities in the air can be prevented from corroding the semiconductor device 20, thereby degrading the electrical performance, and on the other hand, the mounting and fixing functions can be performed, so that the packaged semiconductor device 20 is more convenient to mount and transport.
The first electric carrier 11 has a first heat dissipation portion 111, the second electric carrier 12 has a second heat dissipation portion 121, at least a portion of the electrical connection portion 133 is exposed out of the package 30, so that connection to an external circuit is facilitated, the first heat dissipation portion 111 is exposed out of the package 30, and the second heat dissipation portion 121 is exposed out of the package 30, so that heat generated by the semiconductor device 20 can be dissipated by the first heat dissipation portion 111 and the second heat dissipation portion 121.
According to the semiconductor assembly 100 of the embodiment of the invention, the first electric carrier plate 11 and the second electric carrier plate 12 which are electrically connected with the semiconductor device 20 are arranged, at least one part of the first electric carrier plate 11 is exposed out of the package body 30 to form the first heat dissipation part 111, at least one part of the second electric carrier plate 12 is exposed out of the package body 30 to form the second heat dissipation part 121, so that heat dissipation can be performed through the first heat dissipation part 111 and the second heat dissipation part 121, namely two heat dissipation paths are formed, the heat conduction area of the semiconductor device 20 is increased, the heat dissipation efficiency of the semiconductor device 20 is further improved, the internal temperature of the semiconductor device 20 can be limited to be not exceed a certain value, and the use reliability of the semiconductor assembly 100 is improved.
As shown in fig. 3-4, according to some embodiments of the present invention, the semiconductor device 20 is mounted on the first electric carrier 11, the first heat dissipation portion 111 forms a first heat dissipation surface, and a projection of the first electrode 21 on a plane of the first heat dissipation surface at least partially coincides with the first heat dissipation surface.
Thus, the heat generated by the semiconductor device 20 can be directly transferred to the first electric carrier plate 11, especially the heat generated by the first electrode 21 can be directly transferred to the position of the first electric carrier plate 11 opposite to the first electrode 21, and the first heat dissipation surface exposes the package body 30, so that the heat transferred to the first electric carrier plate 11 can be quickly dissipated from the first heat dissipation surface, thereby shortening the heat dissipation path and being beneficial to improving the heat dissipation efficiency.
In some embodiments, the projection of the first electrode 21 on the plane of the first heat dissipation surface is located in the first heat dissipation surface, so that the heat dissipation area exposed out of the package body 30 is increased, and the heat generated by the first electrode 21 can be directly conducted to the first heat dissipation surface, so that the heat dissipation efficiency of the semiconductor device 20 is further improved, and the reliability of the semiconductor assembly 100 is improved.
Specifically, the first electrode 21 is disposed opposite to the first heat dissipation surface, and a projection of the first electrode 21 on a plane where the first heat dissipation surface is located is smaller than or equal to an area of the first heat dissipation surface, where a shape of the first heat dissipation surface may be a circle, a square, or the like, and may be selected according to practical situations.
In some embodiments, the first heat dissipating surface is flush with an outer surface of the package 30. That is, the exposed portion of the first electric carrier 11 is flush with the outer surface of the package 30, so as to avoid interference between the exposed portion of the first electric carrier 11 and other structures, and ensure that the semiconductor assembly 100 can be normally mounted.
As shown in fig. 4, in some embodiments, the semiconductor device 20 is attached to the first electrical carrier plate 11 by a thermally conductive connection layer 51.
Thus, by providing the heat conductive connection layer 51, not only the connection reliability between the first electric carrier plate 11 and the semiconductor device 20 is ensured, but also part of the heat generated by the semiconductor device 20 can be conducted to the first electric carrier plate 11 through the heat conductive connection layer 51, and finally dissipated from the first heat dissipation part 111, thereby improving the heat dissipation efficiency of the semiconductor device 20.
The thickness of the thermally conductive connection layer 51 may be controlled between 20 micrometers and 70 micrometers, for example, the thickness of the thermally conductive connection layer 51 may be 20 micrometers, 40 micrometers, 50 micrometers, 70 micrometers, etc.
In some examples, the thermally conductive connection layer 51 is provided between the semiconductor device 20 and the first electrical carrier plate 11 by a printing process.
Specifically, before the semiconductor device 20 is mounted on the first electric carrier plate 11, the heat conducting connection layer 51 may be printed at a predetermined position of the first electric carrier plate 11, and then the semiconductor device 20 is placed on the heat conducting connection layer 51, so as to implement positioning and mounting of the semiconductor device 20. The printing process is simple to operate and easy to implement, and the heat conduction connecting layer 51 formed by the printing process is better in quality and higher in production efficiency.
In other examples, the thermally conductive connection layer 51 is provided between the semiconductor device 20 and the first electrical carrier plate 11 by a coating process. The heat conductive connection layer 51 formed through the coating process has high material utilization rate, avoids waste of materials, and has high production efficiency.
In some examples, the material of the thermally conductive connection layer 51 is tin or silver. Specifically, the heat conducting connection layer 51 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the heat conducting connection layer can play a role in connecting the semiconductor device 20 and the first electric carrier 11, and can play a role in conducting heat generated by the semiconductor device 20 to the first electric carrier 11.
In some embodiments, as shown in fig. 4, the projection of the second electrode 22 on the plane of the first radiating surface at least partially coincides with the first radiating surface. Therefore, the heat generated by the second electrode 22 can be directly conducted to the position of the first electric carrier plate 11 opposite to the second electrode 21, and the first heat dissipation surface exposes the package body 30, so that the heat conducted to the first electric carrier plate 11 can be dissipated from the first heat dissipation surface, thereby shortening the heat dissipation path and being beneficial to improving the heat dissipation efficiency.
In some examples, the projection of the second electrode 22 on the plane of the first heat dissipation surface is located in the first heat dissipation surface, so that the heat dissipation area exposed out of the package body 30 is increased, and the heat generated by the second electrode 22 can be directly conducted to the second heat dissipation surface, so that the heat dissipation efficiency of the semiconductor device 20 is further improved, and the use reliability of the semiconductor assembly 100 is improved.
Specifically, the second electrode 22 is disposed opposite to the first heat dissipation surface, and the projection of the second electrode 22 on the plane where the first heat dissipation surface is located is smaller than or equal to the area of the first heat dissipation surface, where the shape of the first heat dissipation surface may be circular, square, etc., and may be selected according to practical situations.
As shown in fig. 1-2 and fig. 4, in the present embodiment, the projection of the semiconductor device 20 on the plane where the first heat dissipation surface is located in the first heat dissipation surface, so that the heat dissipation area exposed out of the package 30 is increased, the heat dissipation efficiency of the semiconductor device 20 is further improved, and the reliability of the semiconductor assembly 100 is improved.
As shown in fig. 5, according to some embodiments of the present invention, the semiconductor assembly 100 further includes a first connector 41, one end of the first connector 41 is electrically connected to the first electrode 21, the other end of the first connector 41 is electrically connected to the first electric carrier 11, and the package 30 wraps the first connector 41.
That is, after packaging, the package 30 may encapsulate the semiconductor device 20, the junction between the first electrode 21 of the semiconductor device 20 and one end of the first connection member 41, and the junction between the other end of the first connection member 41 and the first electric carrier plate 11, so as to avoid breakage of the junction between the first electrode 21 and one end of the first connection member 41, the junction between the other end of the first connection member 41 and the first electric carrier plate 11, and ensure connection reliability between the first connection member 41 and the first electric carrier plate 11, and between the first connection member 41 and the first electrode 21 of the semiconductor device 20.
In some embodiments, the first connector 41 forms a metal wire.
Specifically, the first electrode 21 of the semiconductor device 20 may be electrically connected to the electrical connection portion 133 of the first electrical carrier 11 using a wire bonding process, so that the first connection 41 is formed between the first electrode 21 and the electrical connection portion 133 of the first electrical carrier 11.
It should be noted that, wire bonding refers to using a metal wire to complete connection of internal interconnection wires of a solid circuit in a microelectronic device by using hot pressing or ultrasonic energy, so that the first electrode 21 and the electrical connection portion 133 of the first electric carrier plate 11 are connected together through a wire bonding process, and a metal connection wire can be formed therebetween.
In other embodiments, the first connector 41 forms a metallic connecting piece. The structural strength of the metal connecting sheet is higher, so that the connection reliability between the first connecting piece 41 and the first electrode 21 and the connection reliability between the first connecting piece 41 and the first electric carrier plate 11 can be guaranteed.
As shown in fig. 5, in some examples, a first connection layer 52 is disposed between one end of the first connection member 41 and the first electrode 21, the first connection layer 52 may electrically connect one end of the first connection member 41 with the first electrode 21, a first connection layer 52 is disposed between the other end of the first connection member 41 and the first electric carrier 11, and the first connection layer 52 may electrically connect the other end of the first connection member 41 with the first electric carrier 11, so that the first electrode 21 of the semiconductor device 20 is electrically connected with the first electric carrier 11.
The thickness of the first connection layer 52 may be controlled between 20 micrometers and 70 micrometers, for example, the thickness of the first connection layer 52 may be 20 micrometers, 40 micrometers, 50 micrometers, 70 micrometers, etc.
In some specific examples, the first connection layer 52 is provided on the first electric carrier plate 11 by a printing process.
Specifically, before the first electric carrier plate 11 is electrically connected to the first electrode 21 of the semiconductor device 20, the first connection layer 52 may be printed on a predetermined position of the first electric carrier plate 11 and on the first electrode 21, and then two ends of the first connection member 41 are respectively connected to the first connection layer 52 on the first electric carrier plate 11 and the first connection layer 52 on the first electrode 21, so that the first connection member 41 is used to electrically connect the first electrode 21 to the first electric carrier plate 11. The printing process is simple to operate and easy to implement, and the quality of the first connection layer 52 formed by the printing process is better and the production efficiency is higher.
Of course, the first connection layer 52 may also be provided at a predetermined position of the first electric carrier plate 11 and on the first electrode 21 by a coating process. The first connection layer 52 formed through the coating process has high material utilization, avoids waste of materials, and has high production efficiency.
Wherein, the material of the first connection layer 52 is tin or silver.
Specifically, the first connection layer 52 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the first connection layer 52 located between the first connection piece 41 and the first electrode 21 may play a role of connecting one end of the first connection piece 41 with the first electrode 21, may play a role of heat conduction, and the first connection layer 52 located between the first connection piece 41 and the first electric carrier plate 11 may play a role of connecting the other end of the first connection piece 41 with the first electric carrier plate 11, and may play a role of heat conduction.
As shown in fig. 6 and 7, according to some embodiments of the present invention, the semiconductor assembly 100 further includes a second connection member 42, one end of the second connection member 42 is electrically connected to the second electrode 22, the other end of the second connection member 42 is electrically connected to the second electric carrier 12, and the package 30 wraps the second connection member 42.
That is, after packaging, the package 30 may encapsulate the semiconductor device 20, the connection between the second electrode 22 of the semiconductor device 20 and one end of the second connection member 42, and the connection between the other end of the second connection member 42 and the second electric carrier 12, so as to avoid breakage of the connection between the second electrode 22 of the semiconductor device 20 and one end of the second connection member 42, the connection between the other end of the second connection member 42 and the second electric carrier 12, and ensure connection reliability between the second connection member 42 and the second electric carrier 12, and between the second connection member 42 and the second electrode 22 of the semiconductor device 20.
In some embodiments, the second heat dissipation portion 121 forms a second heat dissipation surface, and a projection of the other end of the second connecting member 42 on the plane of the second heat dissipation surface at least partially coincides with the second heat dissipation surface.
Thus, the heat generated by the semiconductor device 20 can be conducted to the second electric carrier plate 12, especially, the heat generated by the second electrode 22 can be conducted to the position where the second electric carrier plate 12 faces the second connecting piece 42 through the second connecting piece 42, and the second heat dissipation surface exposes the package body 30, so that the heat conducted to the second electric carrier plate 12 can be dissipated from the second heat dissipation surface, another heat dissipation path is added, double-sided heat dissipation is realized, and the heat dissipation efficiency is improved.
In some examples, the projection of the other end of the second connecting member 42 on the plane of the second heat dissipation surface is located in the second heat dissipation surface, so that the heat dissipation area exposed out of the package body 30 is increased, and the heat generated by the second electrode 22 can be conducted to the second heat dissipation surface through the second connecting member 42, so that the heat dissipation efficiency of the semiconductor device 20 is further improved, and the use reliability of the semiconductor assembly 100 is improved.
Specifically, the other end of the second connecting piece 42 is opposite to the second heat dissipating surface, and the projection of the other end of the second connecting piece 42 on the plane where the second heat dissipating surface is located is smaller than or equal to the area of the second heat dissipating surface, where the shape of the second heat dissipating surface may be circular, square, etc., and may be selected according to practical situations.
In some examples, the second heat dissipating surface is flush with an outer surface of the package 30. That is, the exposed portion of the second electric carrier 12 is flush with the outer surface of the package 30, so as to avoid interference between the exposed portion of the second electric carrier 12 and other structures, and ensure that the semiconductor assembly 100 can be mounted normally.
As shown in fig. 6-8, in some embodiments, the second connector 42 forms a metal connection post. The metal connection posts are disposed between the first and second electric carrier plates 11 and 12 so as to separate the first and second electric carrier plates 11 and 12 and provide a mounting space for the semiconductor device 20.
Specifically, as shown in fig. 7 and 8, in the present embodiment, the first electric carrier plate 11 and the second electric carrier plate 12 are arranged at intervals in the up-down direction, the second connection member 42 forms a metal connection column extending in the up-down direction, the lower end of the second connection member 42 is electrically connected to the second electrode 22 of the first electric carrier plate 11, and the upper end of the second connection member 42 is electrically connected to the second electric carrier plate 12, so that the second electrode 22 is electrically connected to the second electric carrier plate 12 by the second connection member 42.
In some examples, the cross-sectional dimension of the other end (the upper end as shown in fig. 7 and 8) of the second connecting member 42 is larger than the cross-sectional dimension of the middle portion of the second connecting member 42, so as to improve the structural strength of the second connecting member 42 and ensure the reliability of the support of the second connecting member 42 to the second electric carrier plate 12.
For example, the cross-sectional area of the second connection member 42 gradually increases from the first electrical carrier 11 to the second electrical carrier 12; for another example, the second connecting member 42 is divided into a plurality of connecting columns along its axial direction, and the cross-sectional dimension of one connecting column near the second electric carrier plate 12 is larger than the cross-sectional dimension of one connecting column near the first electric carrier plate 11.
As shown in fig. 7, in some embodiments, a second connection layer 53 is disposed between one end of the second connection member 42 and the second electrode 22, the second connection layer 53 may electrically connect one end of the second connection member 42 with the second electrode 22, a second connection layer 53 is disposed between the other end of the second connection member 42 and the second electrical carrier 12, and the second connection layer 53 may electrically connect the other end of the second connection member 42 with the second electrical carrier 12, so as to electrically connect the second electrode 22 of the semiconductor device 20 with the second electrical carrier 12.
The thickness of the second connection layer 53 may be controlled between 20 micrometers and 70 micrometers, for example, the thickness of the second connection layer 53 may be 20 micrometers, 40 micrometers, 50 micrometers, 70 micrometers, etc.
In some specific examples, the second connection layer 53 is provided at a predetermined position of the second electrical carrier 12, the second electrode 22 of the semiconductor device 20, by a printing process.
Specifically, before the second electric carrier plate 12 is electrically connected to the second electrode 22 of the semiconductor device 20, a second connection layer 53 may be printed on a predetermined position of the second electric carrier plate 12 and on the second electrode 22, and then two ends of the second connection member 42 are respectively connected to the second connection layer 53 on the second electric carrier plate 12 and the second connection layer 53 on the second electrode 22, so that the second connection member 42 is used to electrically connect the second electrode 22 to the second electric carrier plate 12. The printing process is simple to operate and easy to implement, and the quality of the second connection layer 53 formed by the printing process is better, and the production efficiency is higher.
Of course, the second connection layer 53 may also be provided at a predetermined position of the second electric carrier plate 12 and on the second electrode 22 by a coating process. The second connection layer 53 formed through the coating process has high material utilization, avoids waste of materials, and has high production efficiency.
The material of the second connection layer 53 is tin or silver.
Specifically, the second connection layer 53 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the second connection layer 53 located between the second connection member 42 and the second electrode 22 may serve to connect one end of the second connection member 42 with the second electrode 22, and may also serve to conduct heat. The second connection layer 53 located between the second connection member 42 and the second electric carrier 12 may serve to connect the other end of the second connection member 42 with the second electric carrier 12, and may also serve to conduct heat.
As shown in fig. 3, 7-8, according to some embodiments of the present invention, each of the first and second electric carrier plates 11 and 12 includes a carrier plate body 131, and the carrier plate bodies 131 of the first and second electric carrier plates 11 and 12 are disposed opposite to and spaced apart from each other.
Further, the first heat dissipation portion 111 is located on the carrier body 131 of the first electric carrier 11, and the second heat dissipation portion 121 is located on the carrier body 131 of the second electric carrier 12.
The semiconductor device 20 is disposed between two carrier bodies 131, the two carrier bodies 131 can protect the semiconductor device 20, the first electrode 21 is connected to the electrical connection portion 133 of the first electrical carrier 11, and the second electrode 22 is electrically connected to the carrier body 131 of the second electrical carrier 12.
Specifically, as shown in fig. 7, in the present embodiment, the first electric carrier plate 11 includes a carrier plate body 131 and an electric connection portion 133 that are connected, the second electric carrier plate 12 includes a carrier plate body 131 and an electric connection portion 133 that are connected, and the carrier plate body 131 of the first electric carrier plate 11 and the carrier plate body 131 of the second electric carrier plate 12 are disposed opposite to each other in the vertical direction, the electric connection portion 133 of the first electric carrier plate 11 is disposed on one side of the carrier plate body 131 of the first electric carrier plate 11, the electric connection portion 133 of the second electric carrier plate 12 is disposed on the other side of the carrier plate body 131 of the second electric carrier plate 12, that is, the electric connection portion 133 of the first electric carrier plate 11 and the electric connection portion 133 of the second electric carrier plate 12 are disposed on different sides of the corresponding carrier plate body 131, so that the electric connection portion 133 can be led out from different directions, and the mounting reliability of the semiconductor assembly 100 can be ensured.
The semiconductor device 20 is disposed between the carrier body 131 of the first electric carrier 11 and the carrier body 131 of the second electric carrier 12, the active surface of the semiconductor device 20 faces the carrier body 131 of the second electric carrier 12, and the surface of the semiconductor device 20 opposite to the active surface faces the carrier body 131 of the first electric carrier 11.
In some examples, one side surface of the two carrier bodies 131 opposite to each other exposes the package body 30 to form the first heat dissipation part 111 and the second heat dissipation part 121, respectively.
That is, the first heat dissipation portion 111 faces the first electrode 21 and the second electrode 21 of the semiconductor device 20, and particularly, the heat generated by the semiconductor device 20, especially the heat generated by the first electrode 21 and the second electrode 22, can be directly transferred to the first heat dissipation portion 111, the second heat dissipation portion 121 faces the first electrode 21 and the second electrode 21 of the semiconductor device 20, and the heat generated by the second electrode 21 can be transferred to the second heat dissipation portion 121 through the second connection member 42, so that the heat is finally dissipated, the requirement of double-side heat dissipation of the semiconductor device is realized, the internal temperature of the semiconductor device 20 can be limited to be not more than a certain value, and the use reliability of the semiconductor assembly 100 is improved.
In some examples, the electrical connection portion 133 includes pins, one ends of which are connected to the outer peripheral edge of the corresponding carrier body 131 through the connection section 132, and the other ends of which extend out of opposite sides of the package body 30, thereby facilitating connection with an external circuit.
Specifically, as shown in fig. 8, each of the first and second electric carrier plates 11 and 12 includes a carrier plate body 131, a connection section 132, and pins, the connection section 132 being connected between the carrier plate body 131 and one end of the pins, and after the first and second electric carrier plates 11 and 12 and the semiconductor device 10 are packaged, the formed package 30 wraps the semiconductor device 20, the first connector 41, the second connector 42, and the connection section 132 of each of the first and second electric carrier plates 11 and 12, a portion of the carrier plate body 131, one end of the pins, thereby forming a protection, guaranteeing the reliability of the structure and electrical performance of the semiconductor assembly 100.
In some specific examples, the two connection sections 132 extend obliquely in a direction away from each other and a direction away from the carrier body 131, so that pins can be led out from different directions, meeting the mounting requirements of the semiconductor assembly 100.
As shown in fig. 1, in some specific examples, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 are bent toward the second heat dissipation portion 121 by a dicing bending process, so that a side where the second heat dissipation portion 121 is located may be mounted on a substrate, and the pins of the first electric carrier plate 11 and the pins of the second electric carrier plate 12 may be connected with pads on the substrate, so that the mounting of the semiconductor assembly 100 on the substrate and the connection of the semiconductor device 20 and an external circuit are realized.
In some specific examples, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 are flush with the second heat dissipation portion 121, so that the second heat dissipation portion 121 does not interfere with the substrate when the pins of the first electric carrier plate 11 and the pins of the second electric carrier plate 12 are connected with the substrate.
As shown in fig. 2, in other specific examples, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 are bent toward the first heat dissipation portion 111 by a dicing bending process, so that the side where the first heat dissipation portion 111 is located can be mounted on a substrate, and the pins of the first electric carrier plate 11 and the pins of the second electric carrier plate 12 can be connected with pads on the substrate, so that the mounting of the semiconductor assembly 100 on the substrate and the connection of the semiconductor device 20 and an external circuit are realized.
In some specific examples, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 are flush with the first heat dissipation portion 111, so that the first heat dissipation portion 111 does not interfere with the substrate when the pins of the first electric carrier plate 11 and the pins of the second electric carrier plate 12 are connected with the substrate.
It should be noted that, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 may be bent by a rib cutting and bending process, so as to realize different planar designs, and different bending depths may be designed to meet the requirements of the packages 30 with different thicknesses.
In addition, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 may be bent in different directions by a rib cutting and bending process according to the difference of the heat dissipation requirement and the heat dissipation path, for example, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 may be bent toward the first heat dissipation portion 111 or the second heat dissipation portion 121 by the rib cutting and bending process, so as to realize the top or bottom exposure.
According to some embodiments of the present invention, the number of semiconductor devices 20 may be two.
Specifically, one of the semiconductor devices 20 is mounted on the upper surface of the first electric carrier plate 11, the first electrode 21 of the semiconductor device 20 is electrically connected to the first electric carrier plate 11, and the second electrode 22 of the semiconductor device 20 is electrically connected to the second electric carrier plate 12. The other semiconductor device 20 is mounted on the lower surface of the second electric carrier plate 12, the first electrode 21 of the semiconductor device 20 is electrically connected with the second electric carrier plate 12, the second electrode 22 of the semiconductor device 20 is electrically connected with the first electric carrier plate 11, and after packaging, the two semiconductor devices 20 are sealed together, and each semiconductor device 20 can realize double-sided heat dissipation, and has higher heat dissipation efficiency.
Of course, the number of the semiconductor devices 20 may also include only one or two or more. The selection and arrangement can be specifically carried out according to actual requirements. For the embodiment in which the semiconductor device 20 includes more than two, the arrangement of the plurality of semiconductor devices 20 may be similar to the embodiment in which the semiconductor device 20 includes two, and will not be described here again.
According to some embodiments of the invention, the first and second electrical carrier plates 11, 12 are metal frames. For example, the first and second electrical carrier plates 11, 12 are copper frames.
The first electric carrier plate 11 is used as a carrier of the semiconductor device 20, not only can support the semiconductor device 20, but also can play roles of heat conduction and electric conduction, and the structural strength of the first electric carrier plate 11 can be ensured while the effect can be ensured by arranging the first electric carrier plate 11 into a metal frame.
Similarly, by providing the second electrical carrier plate 12 as a metal frame, protection can be provided to the semiconductor device 20, and also thermal and electrical conduction can be achieved.
In addition, the semiconductor device 20 is disposed between the first electric carrier 11 and the second electric carrier 12, and the first electric carrier 11 and the second electric carrier 12 are sealed in the same package 30, so that the semiconductor assembly 100 has the advantage of low packaging cost.
A semiconductor device according to an embodiment of the present invention is described below with reference to the accompanying drawings.
The semiconductor device according to the embodiment of the present invention includes the semiconductor assembly 100 according to the above-described embodiment and a heat sink (not shown in the drawings) provided to the first heat sink member 111 or the second heat sink member 121.
Since the semiconductor assembly according to the embodiment of the present invention has the above technical effects, the semiconductor device according to the embodiment of the present invention also has the above technical effects, that is, by adopting the semiconductor assembly 100 and the heat sink, the heat can be dissipated through the first heat dissipation portion 111 and the second heat dissipation portion 121, and the heat sink can dissipate the heat of the first heat dissipation portion 111 or the second heat dissipation portion 121, that is, form two heat dissipation paths, thereby increasing the heat conduction area of the semiconductor device 20, further improving the heat dissipation efficiency of the semiconductor device 20, so that the internal temperature of the semiconductor device 20 can be limited not to exceed a certain value, and improving the reliability of the semiconductor assembly 100 in use.
In some embodiments, the heat sink is connected to the first heat dissipation part 111, and the side of the second heat dissipation part 121 may be mounted on the substrate, so that the heat on the first heat dissipation part 111 may be further dissipated by using the heat sink, and the heat on the second heat dissipation part 121 may be further dissipated by using the substrate.
In other embodiments, the heat sink is connected to the second heat dissipation part 121, and the side of the first heat dissipation part 111 may be mounted on the substrate, so that the heat on the second heat dissipation part 121 may be further dissipated by using the heat sink, and the heat on the first heat dissipation part 111 may be further dissipated by using the substrate.
According to some embodiments of the present invention, the heat sink includes a heat radiating plate and a plurality of heat radiating fins provided at intervals on one side surface of the heat radiating plate, and the other side surface of the heat radiating plate is connected to the first heat radiating part 111 or the second heat radiating part 121. The structure of the radiator is not limited, and the structure capable of realizing heat conduction and heat dissipation belongs to the protection scope of the invention.
A method of fabricating a semiconductor assembly 100 according to an embodiment of the present invention is described below with reference to fig. 1-9.
As shown in fig. 1 to 8, a semiconductor assembly 100 according to an embodiment of the present invention includes a first electric carrier 11, a second electric carrier 12, and a semiconductor device 20, the semiconductor device 20 is mounted on the first electric carrier 11, the second electric carrier 12 is covered on the semiconductor device 20 such that the semiconductor device 20 is located between the first electric carrier 11 and the second electric carrier 12, a first electrode 21 of the semiconductor device 20 is electrically connected to the first electric carrier 11, and a second electrode 22 of the semiconductor device 20 is electrically connected to the second electric carrier 12.
As shown in fig. 9, the method for manufacturing the semiconductor assembly includes the steps of:
s1, providing a semiconductor device, a first electric carrier plate and a second electric carrier plate;
s2, mounting the semiconductor device on a first electric carrier plate, and electrically connecting a first electrode of the semiconductor device with the first electric carrier plate;
specifically, the semiconductor device 20 may be mounted on the first electric carrier plate 11 through the thermally conductive connection layer 51. By providing the heat conductive connection layer 51, not only the connection reliability of the first electric carrier plate 11 and the semiconductor device 20 is ensured, but also part of heat generated by the semiconductor device 20 can be conducted to the first electric carrier plate 11 through the heat conductive connection layer 51, and finally dissipated from the first heat dissipation part 111, thereby improving the heat dissipation efficiency of the semiconductor device 20.
The thermally conductive connection layer 51 is provided between the semiconductor device 20 and the first electrical carrier 11 by a printing process. Specifically, before the semiconductor device 20 is mounted on the first electric carrier plate 11, the heat conducting connection layer 51 may be printed at a predetermined position of the first electric carrier plate 11, and then the semiconductor device 20 is placed on the heat conducting connection layer 51, so as to implement positioning and mounting of the semiconductor device 20. The printing process is simple to operate and easy to implement, and the heat conduction connecting layer 51 formed by the printing process is better in quality and higher in production efficiency. Of course, the thermally conductive connection layer 51 is also provided between the semiconductor device 20 and the first electrical carrier plate 11 by a coating process. The heat conductive connection layer 51 formed through the coating process has high material utilization rate, avoids waste of materials, and has high production efficiency.
The material of the thermally conductive connection layer 51 is tin or silver. Specifically, the heat conducting connection layer 51 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the heat conducting connection layer can play a role in connecting the semiconductor device 20 and the first electric carrier 11, and can play a role in conducting heat generated by the semiconductor device 20 to the first electric carrier 11.
S3, arranging a second electric carrier plate on one side of the semiconductor device, which is opposite to the first electric carrier plate, and electrically connecting a second electrode of the semiconductor device with the second electric carrier plate to obtain a preassembled structure;
s4, packaging the preassembled structure to form a package body outside the preassembled structure;
specifically, before the encapsulation, an encapsulation mold corresponding to the pre-fabricated structure may be fabricated, and then both the pre-fabricated structure and an Epoxy Molding Compound (EMC) may be placed in the encapsulation mold and sealed, so that the epoxy molding compound encapsulates the semiconductor device 20, the peripheral wall of the first electric carrier plate 11, and the side facing the semiconductor device 20, the peripheral wall of the second electric carrier plate 12, and the side facing the semiconductor device 20, that is, in the structure of the first electric carrier plate 11, the second electric carrier plate 12, only the pins, the first heat dissipation portion 111, and the second heat dissipation portion 121 are exposed, thereby obtaining the semiconductor assembly 100 as shown in fig. 8.
After packaging, the formed package 30 is used as a shell of the semiconductor assembly 100, and can protect the semiconductor device 20, the connection part of the first electrode 21 and the first electric carrier plate 11 and the connection part of the second electrode 22 and the second electric carrier plate 12, so that on one hand, the semiconductor device 20 can be isolated from the outside, and impurities in the air are prevented from corroding the semiconductor device 20, thereby causing the reduction of electrical performance, and on the other hand, the mounting and fixing functions can be realized, so that the packaged semiconductor device 20 is more convenient to mount and transport.
The first electric carrier 11 has a first heat dissipation portion 111 and an electrical connection portion 133, the electrical connection portion 133 is used for connecting an external circuit, the second electric carrier 12 has a second heat dissipation portion 121 and an electrical connection portion 133, the electrical connection portion 133 is used for connecting the external circuit, and the first heat dissipation portion 111, the two electrical connection portions 133, and the second heat dissipation portion 121 are exposed out of the package 30.
According to the manufacturing method of the semiconductor assembly 100 of the embodiment of the invention, by arranging the first electric carrier plate 11 and the second electric carrier plate 12 which are electrically connected with the semiconductor device 20, exposing at least a part of the first electric carrier plate 11 out of the package body 30 to form the first heat dissipation part 111, exposing at least a part of the second electric carrier plate 12 out of the package body 30 to form the second heat dissipation part 121, heat dissipation can be performed through the first heat dissipation part 111 and the second heat dissipation part 121, namely, two heat dissipation paths are formed, the heat conduction area of the semiconductor device 20 is increased, the heat dissipation efficiency of the semiconductor device 20 is further improved, and therefore the internal temperature of the semiconductor device 20 can be limited to be not exceed a certain value, and the use reliability of the semiconductor assembly 100 is improved.
As shown in fig. 5 and 8, electrically connecting the first electrode 21 of the semiconductor device 20 with the first electrical carrier plate 11 according to some embodiments of the invention comprises: the first electrode 21 is connected to the electrical connection portion 133 of the first electric carrier 11 by the first connector 41.
After packaging, the package 30 may encapsulate the semiconductor device 20, the junction between the first electrode 21 of the semiconductor device 20 and one end of the first connection member 41, and the junction between the other end of the first connection member 41 and the first electric carrier plate 11, so as to avoid breakage of the junction between the first electrode 21 and one end of the first connection member 41, the junction between the other end of the first connection member 41 and the first electric carrier plate 11, and ensure connection reliability between the first connection member 41 and the first electric carrier plate 11, and between the first connection member 41 and the first electrode 21 of the semiconductor device 20.
In some embodiments, the first connector 41 forms a metal wire.
Specifically, the first electrode 21 of the semiconductor device 20 may be electrically connected to the electrical connection portion 133 of the first electrical carrier 11 using a wire bonding process, so that the first connection 41 is formed between the first electrode 21 and the electrical connection portion 133 of the first electrical carrier 11.
It should be noted that, wire bonding refers to using a metal wire to complete connection of internal interconnection wires of a solid circuit in a microelectronic device by using hot pressing or ultrasonic energy, so that the first electrode 21 and the electrical connection portion 133 of the first electric carrier plate 11 are connected together through a wire bonding process, and a metal connection wire can be formed therebetween.
In other embodiments, the first connector 41 forms a metallic connecting piece. The structural strength of the metal connecting sheet is higher, so that the connection reliability between the first connecting piece 41 and the first electrode 21 and the connection reliability between the first connecting piece 41 and the first electric carrier plate 11 can be guaranteed.
As shown in fig. 5, in some examples, a first connection layer 52 is disposed between one end of the first connection member 41 and the first electrode 21, the first connection layer 52 may electrically connect one end of the first connection member 41 with the first electrode 21, a first connection layer 52 is disposed between the other end of the first connection member 41 and the first electric carrier 11, and the first connection layer 52 may electrically connect the other end of the first connection member 41 with the first electric carrier 11, so that the first electrode 21 of the semiconductor device 20 is electrically connected with the first electric carrier 11.
Wherein, the material of the first connection layer 52 is tin or silver.
Specifically, the first connection layer 52 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the first connection layer 52 located between the first connection piece 41 and the first electrode 21 may play a role of connecting one end of the first connection piece 41 with the first electrode 21, may play a role of heat conduction, and the first connection layer 52 located between the first connection piece 41 and the first electric carrier plate 11 may play a role of connecting the other end of the first connection piece 41 with the first electric carrier plate 11, and may play a role of heat conduction.
As shown in fig. 6-8, electrically connecting the second electrode 22 of the semiconductor device 20 with the second electrical carrier 12, according to some embodiments of the invention, comprises: a second connector 42 is used to connect the second electrode 22 to the second electrical carrier 12.
After packaging, the package 30 may encapsulate the semiconductor device 20, the connection between the second electrode 22 of the semiconductor device 20 and one end of the second connection member 42, and the connection between the other end of the second connection member 42 and the second electric carrier plate 12, so as to avoid breakage of the connection between the second electrode 22 of the semiconductor device 20 and one end of the second connection member 42, the connection between the second connection member 42 and the other end of the second connection member 42 and the second electric carrier plate 12, and ensure connection reliability between the second connection member 42 and the second electric carrier plate 12, and between the second connection member 42 and the second electrode 22 of the semiconductor device 20.
In some embodiments, the second heat dissipation portion 121 forms a second heat dissipation surface, and a projection of the other end of the second connecting member 42 on the plane of the second heat dissipation surface at least partially coincides with the second heat dissipation surface.
Thus, the heat generated by the semiconductor device 20 can be conducted to the second electric carrier plate 12, especially, the heat generated by the second electrode 22 can be conducted to the position where the second electric carrier plate 12 faces the second connecting piece 42 through the second connecting piece 42, and the second heat dissipation surface exposes the package body 30, so that the heat conducted to the second electric carrier plate 12 can be dissipated from the second heat dissipation surface, another heat dissipation path is added, double-sided heat dissipation is realized, and the heat dissipation efficiency is improved.
In some examples, the projection of the other end of the second connecting member 42 on the plane of the second heat dissipating surface is located in the second heat dissipating surface, which increases the heat dissipating area exposed outside the package 30. The heat generated by the second electrode 22 can be conducted to the second heat dissipating surface through the second connection member 42, so as to further improve the heat dissipating efficiency of the semiconductor device 20 and the reliability of the semiconductor assembly 100.
Specifically, the other end of the second connecting piece 42 is opposite to the second heat dissipating surface, and the projection of the other end of the second connecting piece 42 on the plane where the second heat dissipating surface is located is smaller than or equal to the area of the second heat dissipating surface, where the shape of the second heat dissipating surface may be circular, square, etc., and may be selected according to practical situations.
In some examples, the second heat dissipating surface is flush with an outer surface of the package 30. That is, the exposed portion of the second electric carrier 12 is flush with the outer surface of the package 30, so as to avoid interference between the exposed portion of the second electric carrier 12 and other structures, and ensure that the semiconductor assembly 100 can be mounted normally.
As shown in fig. 6-8, in some embodiments, the second connector 42 forms a metal connection post. The metal connection posts are disposed between the first and second electric carrier plates 11 and 12 so as to separate the first and second electric carrier plates 11 and 12 and provide a mounting space for the semiconductor device 20.
Specifically, as shown in fig. 7 and 8, in the present embodiment, the first electric carrier plate 11 and the second electric carrier plate 12 are arranged at intervals in the up-down direction, the second connection member 42 forms a metal connection column extending in the up-down direction, the lower end of the second connection member 42 is electrically connected to the second electrode 22 of the first electric carrier plate 11, and the upper end of the second connection member 42 is electrically connected to the second electric carrier plate 12, so that the second electrode 22 is electrically connected to the second electric carrier plate 12 by the second connection member 42.
In some examples, the cross-sectional dimension of the other end (the upper end as shown in fig. 7 and 8) of the second connecting member 42 is larger than the cross-sectional dimension of the middle portion of the second connecting member 42, so as to improve the structural strength of the second connecting member 42 and ensure the reliability of the support of the second connecting member 42 to the second electric carrier plate 12.
For example, the cross-sectional area of the second connection member 42 gradually increases from the first electrical carrier 11 to the second electrical carrier 12; for another example, the second connecting member 42 is divided into a plurality of connecting columns along its axial direction, and the cross-sectional dimension of one connecting column near the second electric carrier plate 12 is larger than the cross-sectional dimension of one connecting column near the first electric carrier plate 11.
As shown in fig. 7, in some embodiments, a second connection layer 53 is disposed between one end of the second connection member 42 and the second electrode 22, the second connection layer 53 may electrically connect one end of the second connection member 42 with the second electrode 22, a second connection layer 53 is disposed between the other end of the second connection member 42 and the second electrical carrier 12, and the second connection layer 53 may electrically connect the other end of the second connection member 42 with the second electrical carrier 12, so as to electrically connect the second electrode 22 of the semiconductor device 20 with the second electrical carrier 12.
The material of the second connection layer 53 is tin or silver.
Specifically, the second connection layer 53 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the second connection layer 53 located between the second connection member 42 and the second electrode 22 may serve to connect one end of the second connection member 42 with the second electrode 22, and may also serve to conduct heat. The second connection layer 53 located between the second connection member 42 and the second electric carrier 12 may serve to connect the other end of the second connection member 42 with the second electric carrier 12, and may also serve to conduct heat.
According to a further embodiment of the present invention, the electrical connection portions 133 each include a pin, and after the pre-assembled structure is encapsulated by using the encapsulation process, the method further includes:
the pins of each of the first and second electric carrier plates 11 and 12 are bent toward the first heat dissipation portion 111 or the second heat dissipation portion 121 using a bar cutting bending process.
Specifically, as shown in fig. 1, in the present embodiment, after the package of the pre-packaged structure, the pins of each of the first electric carrier 11 and the second electric carrier 12 are bent toward the second heat dissipation portion 121 by the dicing bending process, so that when the semiconductor assembly 100 needs to be mounted on the substrate, the side where the second heat dissipation portion 121 is located can be mounted on the substrate, and the pins of the first electric carrier 11 and the pins of the second electric carrier 12 are connected with the pads on the substrate, so that the mounting of the semiconductor assembly 100 on the substrate and the connection of the semiconductor device 20 and the external circuit are realized.
Wherein, the pin of each of the first electric carrier plate 11 and the second electric carrier plate 12 is flush with the second heat dissipation portion 121, when guaranteeing that the pin of the first electric carrier plate 11, the pin of the second electric carrier plate 12 and the substrate are connected, the second heat dissipation portion 121 will not interfere with the substrate, after the semiconductor assembly 100 is mounted on the substrate, the substrate may contact or separate from the second heat dissipation portion 121, and the substrate may also conduct heat, thereby guaranteeing heat dissipation efficiency.
As shown in fig. 2, in the present embodiment, after the package of the pre-packaged structure, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 are bent toward the first heat dissipation portion 111 by the dicing bending process, so that when the semiconductor assembly 100 needs to be mounted on the substrate, the side on which the first heat dissipation portion 111 is located can be mounted on the substrate, and the pins of the first electric carrier plate 11 and the pins of the second electric carrier plate 12 are connected with the pads on the substrate, so that the mounting of the semiconductor assembly 100 on the substrate and the connection of the semiconductor device 20 and the external circuit are realized.
Wherein, the pin of each of the first electric carrier plate 11 and the second electric carrier plate 12 is flush with the first heat dissipation portion 111, when guaranteeing that the pin of the first electric carrier plate 11, the pin of the second electric carrier plate 12 and the substrate are connected, the first heat dissipation portion 111 will not interfere with the substrate, after the semiconductor assembly 100 is mounted on the substrate, the substrate may contact with or separate from the first heat dissipation portion 111, and the substrate may also conduct heat conduction, thereby guaranteeing heat dissipation efficiency.
Therefore, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 can be bent through a rib cutting and bending process, different plane designs are realized, and the requirements of the package body 30 with different thicknesses can be met through different bending depths.
In addition, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 may be bent in different directions by a rib cutting and bending process according to the difference of the heat dissipation requirement and the heat dissipation path, for example, the pins of each of the first electric carrier plate 11 and the second electric carrier plate 12 may be bent toward the first heat dissipation portion 111 or the second heat dissipation portion 121 by the rib cutting and bending process, so as to realize the top or bottom exposure.
A specific embodiment of the semiconductor assembly 100 according to the present invention is described below with reference to the accompanying drawings.
As shown in fig. 1, 3-8, in the present embodiment, in preparing the semiconductor assembly 100, the first electrical carrier 11, the second electrical carrier 12, the semiconductor device 20, the first connector 41, and the second connector 42 are provided first.
The first electric carrier plate 11 and the second electric carrier plate 12 are both metal frames, and the first electric carrier plate 11 and the second electric carrier plate 12 have the same structure, the first electric carrier plate 11 and the second electric carrier plate 12 each comprise a carrier plate body 131, a connecting section 132 and an electric connecting portion 133, the electric connecting portion 133 and the carrier plate body 131 extend along the horizontal direction, the electric connecting portion 133 is located at one side of the carrier plate body 131 in the horizontal direction, the electric connecting portion 133 and the carrier plate body 131 are staggered in the up-down direction, the connecting section 132 extends obliquely relative to the horizontal direction, and two ends of the connecting section 132 are respectively connected with the carrier plate body 131 and the electric connecting portion 133. One side of the semiconductor device 20 has an active region on which a first electrode 21 and a second electrode 22 are arranged at intervals.
As shown in fig. 4, a heat conductive connection layer 51 having a certain thickness is printed or coated on the upper surface of the carrier body 131 of the first electric carrier plate 11, and a side of the semiconductor device 20 facing away from the active region is attached to the heat conductive connection layer 51, so that the semiconductor device 20 is fixed on the carrier body 131 of the first electric carrier plate 11 through the heat conductive connection layer 51.
As shown in fig. 5, a first connection layer 52 is printed or coated with a certain thickness on the first electrode 21 on the active region of the semiconductor device 20, the electrical connection portion 133 of the first electric carrier plate 11, and then the first electrode 21 of the semiconductor device 20 is led out to the electrical connection portion 133 of the first electric carrier plate 11 through the first connection member 41, one end of the first connection member 41 is connected to the first connection layer 52 on the first electrode 21, and the other end of the first connection member 41 is connected to the electrical connection portion 133 of the first electric carrier plate 11, thereby achieving electrical connection of the first electrode 21 of the semiconductor device 20 and the electrical connection portion 133 of the first electric carrier plate 11.
As shown in fig. 6, a second connection layer 53 is printed or coated on the second electrode 22 on the active region of the semiconductor device 20 to a certain thickness, one end of the second connection member 42 is attached to the second connection layer 53, the end face of one end of the second connection member 42 is connected to the second electrode 22, and then the second connection layer 53 is printed or coated on the end face of the other end of the second connection member 42.
As shown in fig. 7, the structure assembled in fig. 6 is reversely attached to the carrier body 131 of the second electric carrier plate 12, and the other end of the second connecting member 42 is connected to the carrier body 131 of the second electric carrier plate 12 through the second connecting layer 53, so as to obtain the pre-assembled structure shown in fig. 7.
As shown in fig. 8, the pre-packaged structure is packaged by a packaging process, so that a part of the formed package 30 is filled between the first electric carrier 11 and the second electric carrier 12, and thus the package 30 can wrap the semiconductor device 20, the first connector 41, the connection between the first electrode 21 and one end of the first connector 41, the connection between the electrical connection 133 of the first electric carrier 11 and the other end of the first connector 41, the connection between the second connector 42, the connection between the second electrode 22 and one end of the second connector 42, the connection between the electrical connection 133 of the second electric carrier 12 and the other end of the second connector 42, and the other end of the electrical connection 133 of the first electric carrier 11 and the other end of the electrical connection 133 of the second electric carrier 12 all extend out of the package 30.
As shown in fig. 1, the electrical connection portion 133 of the first electrical carrier 11 and the electrical connection portion 133 of the second electrical carrier 12 are bent toward the side where the second heat dissipation portion 121 is located by using a bar cutting and bending process, and the electrical connection portion 133 of the first electrical carrier 11 and the electrical connection portion 133 of the second electrical carrier 12 are made flush with the second heat dissipation portion 121, thereby obtaining the semiconductor assembly 100 as shown in fig. 1.
Another embodiment of the semiconductor assembly 100 according to the present invention is described below with reference to the accompanying drawings.
As shown in fig. 2 to 8, in preparing the semiconductor assembly 100, the first electrical carrier 11, the second electrical carrier 12, the semiconductor device 20, the first connector 41, and the second connector 42 are first provided.
The first electric carrier plate 11 and the second electric carrier plate 12 are both metal frames, and the first electric carrier plate 11 and the second electric carrier plate 12 have the same structure, the first electric carrier plate 11 and the second electric carrier plate 12 each comprise a carrier plate body 131, a connecting section 132 and an electric connecting portion 133, the electric connecting portion 133 and the carrier plate body 131 extend along the horizontal direction, the electric connecting portion 133 is located at one side of the carrier plate body 131 in the horizontal direction, the electric connecting portion 133 and the carrier plate body 131 are staggered in the up-down direction, the connecting section 132 extends obliquely relative to the horizontal direction, and two ends of the connecting section 132 are respectively connected with the carrier plate body 131 and the electric connecting portion 133. One side of the semiconductor device 20 has an active region on which a first electrode 21 and a second electrode 22 are arranged at intervals.
As shown in fig. 4, a heat conductive connection layer 51 having a certain thickness is printed or coated on the upper surface of the carrier body 131 of the first electric carrier plate 11, and a side of the semiconductor device 20 facing away from the active region is attached to the heat conductive connection layer 51, so that the semiconductor device 20 is fixed on the carrier body 131 of the first electric carrier plate 11 through the heat conductive connection layer 51.
As shown in fig. 5, a first connection layer 52 is printed or coated with a certain thickness on the first electrode 21 on the active region of the semiconductor device 20, the electrical connection portion 133 of the first electric carrier plate 11, and then the first electrode 21 of the semiconductor device 20 is led out to the electrical connection portion 133 of the first electric carrier plate 11 through the first connection member 41, one end of the first connection member 41 is connected to the first connection layer 52 on the first electrode 21, and the other end of the first connection member 41 is connected to the electrical connection portion 133 of the first electric carrier plate 11, thereby achieving electrical connection of the first electrode 21 of the semiconductor device 20 and the electrical connection portion 133 of the first electric carrier plate 11.
As shown in fig. 6, a second connection layer 53 is printed or coated on the second electrode 22 on the active region of the semiconductor device 20 to a certain thickness, one end of the second connection member 42 is attached to the second connection layer 53, the end face of one end of the second connection member 42 is connected to the second electrode 22, and then the second connection layer 53 is printed or coated on the end face of the other end of the second connection member 42.
As shown in fig. 7, the structure assembled in fig. 6 is reversely attached to the carrier body 131 of the second electric carrier plate 12, and the other end of the second connecting member 42 is connected to the carrier body 131 of the second electric carrier plate 12 through the second connecting layer 53, so as to obtain the pre-assembled structure shown in fig. 7.
As shown in fig. 8, the pre-packaged structure is packaged by a packaging process, so that a part of the formed package 30 is filled between the first electric carrier 11 and the second electric carrier 12, and thus the package 30 can wrap the semiconductor device 20, the first connector 41, the connection between the first electrode 21 and one end of the first connector 41, the connection between the electrical connection 133 of the first electric carrier 11 and the other end of the first connector 41, the connection between the second connector 42, the connection between the second electrode 22 and one end of the second connector 42, the connection between the electrical connection 133 of the second electric carrier 12 and the other end of the second connector 42, and the other end of the electrical connection 133 of the first electric carrier 11 and the other end of the electrical connection 133 of the second electric carrier 12 all extend out of the package 30.
As shown in fig. 2, the electrical connection portion 133 of the first electrical carrier 11 and the electrical connection portion 133 of the second electrical carrier 12 are bent toward the side where the first heat dissipation portion 111 is located by using a bar cutting and bending process, and the electrical connection portion 133 of the first electrical carrier 11 and the electrical connection portion 133 of the second electrical carrier 12 are made flush with the first heat dissipation portion 111, thereby obtaining the semiconductor assembly 100 as shown in fig. 2.
The first electric carrier 11 and the second electric carrier 12 have the same structure, and after packaging, the electric connection portion 133 is bent and cut by a rib cutting and bending process, so as to be separated into individual units.
After packaging, the electrical connection portion 133 of the first electrical carrier 11 exposes the package body 30, and the electrical connection portion 133 of the second electrical carrier 12 exposes the package body 30, so that connection with an external circuit is facilitated, the package body 30 is exposed from the surface of the carrier body 131 of the first electrical carrier 11, which is opposite to the semiconductor device 20, so as to form the first heat dissipation portion 111, the package body 30 is exposed from the surface of the carrier body 131 of the second electrical carrier 12, which is opposite to the semiconductor device 20, so as to form the second heat dissipation portion 121, and heat is dissipated through the first heat dissipation portion 111 and the second heat dissipation portion 121, so that two heat dissipation paths are formed, the heat conduction area of the semiconductor device 20 is increased, the heat dissipation efficiency of the semiconductor device 20 is further improved, the internal temperature of the semiconductor device 20 can be limited not to exceed a certain value, and the use reliability of the semiconductor assembly 100 is improved.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Other configurations and operations of the semiconductor assembly 100 according to embodiments of the present invention are known to those of ordinary skill in the art and will not be described in detail herein.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.

Claims (24)

1. A semiconductor assembly, comprising:
The first electric carrier plate and the second electric carrier plate are metal frames, and are respectively provided with an electric connection part connected with an external circuit;
the semiconductor device is arranged between the first electric carrier plate and the second electric carrier plate, a first electrode of the semiconductor device is electrically connected with the first electric carrier plate, a second electrode of the semiconductor device is electrically connected with the second electric carrier plate, and the first electrode and the second electrode are positioned on the same side of the semiconductor device;
the packaging body wraps the semiconductor device, the connection part of the first electrode and the first electric carrier plate and the connection part of the second electrode and the second electric carrier plate;
the first connecting piece is characterized by comprising a first electrode, a first connecting piece, a second connecting piece and a packaging body, wherein one end of the first connecting piece is electrically connected with the first electrode, the other end of the first connecting piece is electrically connected with the electric connecting part of the first electric carrier plate, and the packaging body wraps the first connecting piece;
the second connecting piece, one end of the second connecting piece is electrically connected with the second electrode and the other end of the second connecting piece is electrically connected with the electrical connection part of the second electrical carrier plate, and the packaging body wraps the second connecting piece;
The first electric carrier plate is provided with a first heat dissipation part, the second electric carrier plate is provided with a second heat dissipation part, and at least a part of the electric connection part, the first heat dissipation part and the second heat dissipation part are exposed out of the packaging body.
2. The semiconductor assembly of claim 1, wherein the semiconductor device is mounted on the first electrical carrier, the first heat dissipation portion forms a first heat dissipation surface, and a projection of the first electrode on a plane of the first heat dissipation surface is at least partially coincident with the first heat dissipation surface.
3. The semiconductor assembly of claim 2, wherein a projection of the first electrode onto a plane in which the first cooling surface is located within the first cooling surface.
4. The semiconductor assembly of claim 2, wherein the first heat dissipating surface is flush with an outer surface of the package.
5. The semiconductor assembly of claim 2, wherein a projection of the second electrode on a plane of the first cooling surface at least partially coincides with the first cooling surface.
6. The semiconductor assembly of claim 5, wherein a projection of the second electrode onto a plane in which the first cooling surface is located within the first cooling surface.
7. The semiconductor assembly of claim 1, wherein a first connection layer is disposed between the one end of the first connection member and the first electrode, and between the other end of the first connection member and the first electrical carrier.
8. The semiconductor assembly of claim 1, wherein the second heat sink portion forms a second heat sink surface, a projection of the other end of the second connection member on a plane of the second heat sink surface at least partially coinciding with the second heat sink surface.
9. The semiconductor assembly of claim 8, wherein a projection of the other end of the second connection member onto a plane in which the second heat dissipating surface is located within the second heat dissipating surface.
10. The semiconductor assembly of claim 8, wherein the second heat dissipating surface is flush with an outer surface of the package.
11. The semiconductor assembly of claim 1, wherein the second connection forms a metal connection post.
12. The semiconductor assembly of claim 11, wherein the cross-sectional dimension of the other end of the second connector is greater than the cross-sectional dimension of the middle portion of the second connector.
13. The semiconductor assembly of any one of claims 1-12, wherein each of the first and second electrical carrier plates comprises:
the carrier plate body of the first electric carrier plate and the carrier plate body of the second electric carrier plate are opposite to each other and are arranged at intervals, and the first heat dissipation part/the second heat dissipation part is positioned on the carrier plate body;
the semiconductor device is arranged between the two carrier plate bodies, the first electrode is connected with the electric connection part of the first electric carrier plate, and the second electrode is electrically connected with the carrier plate bodies of the second electric carrier plate.
14. The semiconductor package according to claim 13, wherein two opposite side surfaces of the carrier bodies expose the package body to form the first heat sink portion and the second heat sink portion, respectively.
15. The semiconductor package according to claim 13, wherein the electrical connection portion includes pins, one ends of the two pins are connected to the peripheral edge of the corresponding carrier body through connection segments, and the other ends of the two pins extend out of opposite sides of the package body.
16. The semiconductor assembly of claim 15, wherein two of the connection segments extend obliquely in a direction away from each other and away from the carrier body.
17. The semiconductor assembly of claim 15, wherein the pins of each of the first and second electrical carrier plates are bent toward the first or second heat sink portions by a dicing bending process.
18. The semiconductor assembly of claim 17, wherein the pins of each of the first and second electrical carrier plates are flush with the first or second heat sink portions.
19. The semiconductor assembly of any one of claims 1-12, wherein the first and second electrical carrier plates are metal frames.
20. A semiconductor device, comprising:
the semiconductor component of any one of claims 1-19;
and the radiator is arranged on the first radiating part or the second radiating part.
21. A method of fabricating a semiconductor device, comprising the steps of:
Providing a semiconductor device, a first electric carrier plate and a second electric carrier plate, wherein the first electric carrier plate and the second electric carrier plate are metal frames;
mounting the semiconductor device on the first electric carrier plate, and electrically connecting a first electrode of the semiconductor device with the first electric carrier plate, wherein the electrically connecting the first electrode of the semiconductor device with the first electric carrier plate comprises an electric connecting part for connecting the first electrode with the first electric carrier plate by adopting a first connecting piece;
the second electric carrier plate is arranged on one side, facing away from the first electric carrier plate, of the semiconductor device, a second electrode of the semiconductor device is electrically connected with the second electric carrier plate, and the second electrode is connected with the second electric carrier plate by adopting a second connecting piece to obtain a preassembled structure;
encapsulating the pre-fabricated structure to form an encapsulation outside the pre-fabricated structure;
the first electrode and the second electrode are located on the same side of the semiconductor device, the first electric carrier plate is provided with a first radiating part, the second electric carrier plate is provided with a second radiating part, the first electric carrier plate and the second electric carrier plate are provided with electric connecting parts, and the first radiating part, the second radiating part and the electric connecting parts are exposed out of the packaging body.
22. The method of manufacturing a semiconductor package according to claim 21, wherein the first connecting member forms a metal connecting wire or a metal connecting sheet.
23. The method of manufacturing a semiconductor package according to claim 21, wherein the second connection member forms a metal connection post.
24. The method of any one of claims 21-23, wherein the electrical connection includes a pin, and wherein after the pre-packaged structure is packaged using a packaging process, further comprising:
and bending pins of each of the first electric carrier plate and the second electric carrier plate towards the first heat dissipation part or the second heat dissipation part by adopting a rib cutting and bending process.
CN202211590512.9A 2022-12-12 2022-12-12 Semiconductor assembly, preparation method thereof and semiconductor device Active CN115602656B (en)

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Citations (5)

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Publication number Priority date Publication date Assignee Title
CN1430268A (en) * 2001-12-27 2003-07-16 株式会社电装 Semiconductor power device
CN107039289A (en) * 2015-10-26 2017-08-11 英飞凌科技奥地利有限公司 The thermobond materials of heat with restriction, mechanically and electrically characteristic
CN211578743U (en) * 2019-12-10 2020-09-25 杰群电子科技（东莞）有限公司 Semiconductor packaging structure and electronic product
CN113632214A (en) * 2019-03-19 2021-11-09 株式会社电装 Semiconductor module and semiconductor device used for the same
CN217507316U (en) * 2022-03-07 2022-09-27 绍兴中芯集成电路制造股份有限公司 Chip packaging structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1430268A (en) * 2001-12-27 2003-07-16 株式会社电装 Semiconductor power device
CN107039289A (en) * 2015-10-26 2017-08-11 英飞凌科技奥地利有限公司 The thermobond materials of heat with restriction, mechanically and electrically characteristic
CN113632214A (en) * 2019-03-19 2021-11-09 株式会社电装 Semiconductor module and semiconductor device used for the same
CN211578743U (en) * 2019-12-10 2020-09-25 杰群电子科技（东莞）有限公司 Semiconductor packaging structure and electronic product
CN217507316U (en) * 2022-03-07 2022-09-27 绍兴中芯集成电路制造股份有限公司 Chip packaging structure

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