CN115602656A - Semiconductor assembly, preparation method thereof and semiconductor device - Google Patents

Semiconductor assembly, preparation method thereof and semiconductor device Download PDF

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Publication number
CN115602656A
CN115602656A CN202211590512.9A CN202211590512A CN115602656A CN 115602656 A CN115602656 A CN 115602656A CN 202211590512 A CN202211590512 A CN 202211590512A CN 115602656 A CN115602656 A CN 115602656A
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heat dissipation
carrier plate
semiconductor device
electrode
electrical
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CN202211590512.9A
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CN115602656B (en
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朱益峰
曹凯
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Innoscience Suzhou Semiconductor Co Ltd
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Innoscience Suzhou Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention discloses a semiconductor assembly, a preparation method thereof and a semiconductor device, wherein the semiconductor assembly comprises: the first electric carrier plate and the second electric carrier plate; a first electrode of the semiconductor device is electrically connected with the first electric carrier plate, and a second electrode of the semiconductor device is electrically connected with the second electric carrier plate; the packaging body wraps the semiconductor device, the connection position of the first electrode and the first electric carrier plate and the connection position of the second electrode and the second electric carrier plate; the first electric carrier plate is provided with a first heat dissipation part, the second electric carrier plate is provided with a second heat dissipation part, and at least one part of the electric connection part, the first heat dissipation part and the second heat dissipation part are exposed out of the packaging body. According to the semiconductor assembly provided by the embodiment of the invention, two heat dissipation paths can be formed, the heat conduction area of the semiconductor device is increased, and the heat dissipation efficiency of the semiconductor device is further improved, so that the internal temperature of the semiconductor device can be limited not to exceed a certain value, and the use reliability of the semiconductor assembly is improved.

Description

Semiconductor assembly, preparation method thereof and semiconductor device
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor assembly, a preparation method thereof and a semiconductor device.
Background
Document CN111933598A discloses a heat dissipation type semiconductor package product, which comprises a chip carrier, a chip and a package colloid, wherein the chip is fixed in a chip carrying area of the chip carrier, an electrode of the chip is connected with the chip carrier through a metal wire, the package colloid wraps the chip and is connected with the chip carrier, and a metal heat dissipation tube is arranged on one side of the chip carrier, which is back to the chip.
Furthermore, CN201616430U discloses a package structure of an ic, in which a chip and a pin are disposed on a surface of a chip carrier, the chip and the chip carrier are bonded together by a solder, an insulating pad is disposed between the pin and the chip carrier, the pin is electrically connected to the chip by a connecting wire, and a molding compound encapsulates the chip and the chip carrier.
In the two schemes, the bottom of the chip is in contact with the chip carrier, and the side part and the top of the chip are in contact with the packaging colloid, so that heat generated by the chip is not easy to dissipate, and the service performance of the chip is influenced.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. To this end, it is an object of the present invention to provide a semiconductor component having high reliability and heat dissipation efficiency.
The invention also provides a semiconductor device with the semiconductor component.
The invention also provides a preparation method of the semiconductor component.
According to a first aspect of the invention, a semiconductor assembly comprises: the first electric carrier plate and the second electric carrier plate are respectively provided with an electric connection part connected with an external circuit; the semiconductor device is arranged between the first electric carrier plate and the second electric carrier plate, a first electrode of the semiconductor device is electrically connected with the first electric carrier plate, and a second electrode of the semiconductor device is electrically connected with the second electric carrier plate; the packaging body wraps the semiconductor device, the connection position of the first electrode and the first electric carrier plate and the connection position of the second electrode and the second electric carrier plate; the first electric carrier plate is provided with a first heat dissipation part, the second electric carrier plate is provided with a second heat dissipation part, and at least one part of the electric connection part, the first heat dissipation part and the second heat dissipation part are exposed out of the packaging body.
According to the semiconductor assembly provided by the embodiment of the invention, the first electric carrier plate and the second electric carrier plate which are electrically connected with the semiconductor device are arranged, at least one part of the first electric carrier plate is exposed out of the packaging body to form the first heat dissipation part, and at least one part of the second electric carrier plate is exposed out of the packaging body to form the second heat dissipation part, so that heat dissipation can be carried out through the first heat dissipation part and the second heat dissipation part, namely two heat dissipation paths are formed, the heat conduction area of the semiconductor device is increased, the heat dissipation efficiency of the semiconductor device is further improved, the internal temperature of the semiconductor device is limited not to exceed a certain value, and the use reliability of the semiconductor assembly is improved.
According to some embodiments of the invention, the semiconductor device is mounted on the first electrical carrier, the first heat sink portion forms a first heat sink surface, and a projection of the first electrode on a plane of the first heat sink surface at least partially coincides with the first heat sink surface.
In some embodiments, a projection of the first electrode on a plane of the first heat dissipation surface is located in the first heat dissipation surface.
In some embodiments, the first heat dissipation surface is flush with an outer surface of the package body.
In some embodiments, a projection of the second electrode on the plane of the first heat dissipation surface is at least partially coincident with the first heat dissipation surface.
In some examples, a projection of the second electrode on a plane of the first heat dissipation surface is located within the first heat dissipation surface.
According to some embodiments of the invention, the semiconductor assembly further comprises: and one end of the first connecting piece is electrically connected with the first electrode, the other end of the first connecting piece is electrically connected with the first electric carrier plate, and the packaging body wraps the first connecting piece.
In some examples, a first connection layer is disposed between the one end of the first connection member and the first electrode, and between the other end of the first connection member and the first electrical carrier.
According to some embodiments of the invention, the semiconductor assembly further comprises: and one end of the second connecting piece is electrically connected with the second electrode, the other end of the second connecting piece is electrically connected with the second electric carrier plate, and the packaging body wraps the second connecting piece.
In some embodiments, the second heat dissipation part forms a second heat dissipation surface, and a projection of the other end of the second connector on a plane where the second heat dissipation surface is located at least partially coincides with the second heat dissipation surface.
In some examples, a projection of the other end of the second connecting piece on a plane of the second heat dissipation surface is located in the second heat dissipation surface.
In some examples, the second heat dissipation surface is flush with an outer surface of the package body.
In some embodiments, the second connector forms a metal connection post.
In some examples, the other end of the second connector has a cross-sectional dimension that is greater than a cross-sectional dimension of a middle portion of the second connector.
According to some specific embodiments of the invention, each of the first and second electrical carrier plates comprises: the carrier plate body of the first electric carrier plate is opposite to the carrier plate body of the second electric carrier plate and arranged at intervals, and the first heat dissipation part/the second heat dissipation part are positioned on the carrier plate body; the semiconductor device is arranged between the two carrier plate bodies, the first electrode is connected with the electric connection part of the first electric carrier plate, and the second electrode is electrically connected with the carrier plate body of the second electric carrier plate.
In some examples, one side surfaces of the two carrier plate bodies, which are opposite to each other, expose the package body to form the first heat dissipation part and the second heat dissipation part respectively.
In some examples, the electrical connection portion includes pins, one end of each of the two pins is connected to the outer periphery of the corresponding carrier body through a connection section, and the other end of each of the two pins extends out of the two opposite sides of the package body.
In some specific examples, the two connecting sections extend obliquely in a direction away from each other and in a direction away from the carrier body.
In some specific examples, the pins of each of the first and second electrical carrier plates are bent toward the first or second heat sink portions by a bar-cutting bending process.
In some specific examples, the pins of each of the first and second electrical carrier plates are flush with the first or second heat sink portions.
According to some embodiments of the present invention, the first and second electrical carrier plates are metal frames.
The semiconductor device according to an embodiment of the second aspect of the present invention includes: the semiconductor assembly according to the above embodiment; a heat sink provided in the first heat sink portion or the second heat sink portion.
According to the semiconductor device of the embodiment of the invention, by adopting the semiconductor component and the radiator, the radiating efficiency of the semiconductor device can be improved, so that the internal temperature of the semiconductor device can be limited not to exceed a certain value, and the use reliability of the semiconductor component is improved.
According to the method for manufacturing a semiconductor component of the embodiment of the third aspect of the present invention, the method includes the steps of: providing a semiconductor device, a first electric carrier plate and a second electric carrier plate; mounting the semiconductor device on the first electric carrier plate, and electrically connecting a first electrode of the semiconductor device with the first electric carrier plate; arranging the second electrical carrier plate on one side of the semiconductor device, which is opposite to the first electrical carrier plate, and electrically connecting a second electrode of the semiconductor device with the second electrical carrier plate to obtain a pre-assembly structure; encapsulating the pre-assembly structure to form an encapsulation outside the pre-assembly structure; the first electric carrier plate is provided with a first heat dissipation part, the second electric carrier plate is provided with a second heat dissipation part, the first electric carrier plate and the second electric carrier plate are respectively provided with an electric connection part, and the first heat dissipation part, the second heat dissipation part and the electric connection part are exposed out of the packaging body.
According to the preparation method of the semiconductor assembly, the first electric carrier plate and the second electric carrier plate which are electrically connected with the semiconductor device are arranged, at least one part of the first electric carrier plate is exposed out of the packaging body to form the first heat dissipation part, at least one part of the second electric carrier plate is exposed out of the packaging body to form the second heat dissipation part, so that heat dissipation can be carried out through the first heat dissipation part and the second heat dissipation part, namely two heat dissipation paths are formed, the heat conduction area of the semiconductor device is increased, the heat dissipation efficiency of the semiconductor device is further improved, the internal temperature of the semiconductor device is limited not to exceed a certain value, and the use reliability of the semiconductor assembly is improved.
According to some embodiments of the invention, said electrically connecting a first electrode of said semiconductor device with said first electrical carrier comprises: and connecting the first electrode with the electric connection part of the first electric carrier plate by adopting a first connecting piece.
In some embodiments, the first connector forms a metal connecting wire or a metal connecting piece.
According to some embodiments of the invention, said electrically connecting the second electrode of the semiconductor device with the second electrical carrier comprises: and connecting the second electrode and the second electric carrier plate by using a second connecting piece.
In some embodiments, the second connector forms a metal connection post.
According to a further embodiment of the present invention, the electrical connection portion includes a pin, and after the pre-assembly structure is packaged by a packaging process, the electrical connection portion further includes: and bending the pins of each of the first electric carrier plate and the second electric carrier plate towards the first heat dissipation part or the second heat dissipation part by adopting a rib cutting and bending process.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a semiconductor device according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first electrical carrier of a semiconductor device according to an embodiment of the invention;
fig. 4 is a schematic structural view illustrating a semiconductor device of a semiconductor assembly mounted on a first electrical carrier according to an embodiment of the present invention;
fig. 5 is a schematic structural view illustrating that the semiconductor device of the semiconductor assembly is electrically connected to the first electrical carrier board through the first connecting member according to the embodiment of the present invention;
fig. 6 is a schematic structural view of a first electrical carrier plate, a semiconductor device, a first connecting member and a second connecting member of a semiconductor assembly according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a pre-assembly structure of a semiconductor assembly according to an embodiment of the invention;
fig. 8 is a schematic view of a semiconductor assembly according to an embodiment of the present invention after packaging in a pre-assembled configuration;
fig. 9 is a flow chart of a method of fabricating a semiconductor assembly according to an embodiment of the present invention.
Reference numerals:
the semiconductor device (100) is provided with a semiconductor element,
a first electrical carrier 11, a first heat sink 111,
a second electrical carrier 12, a second heat sink 121,
a carrier body 131, a connecting section 132, an electrical connection portion 133,
a semiconductor device 20, a first electrode 21, a second electrode 22,
the package 30, the first connector 41, the second connector 42,
a thermally conductive bonding layer 51, a first bonding layer 52, and a second bonding layer 53.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention and are not to be construed as limiting the present invention.
In the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; mechanical connection or electrical connection is also possible; either directly or indirectly through intervening media, either internally or in any other relationship. Specific meanings of the above terms in the embodiments of the present invention can be understood by those of ordinary skill in the art according to specific situations.
The manufacturing process of semiconductor products is generally divided into eight steps: wafer processing → oxidation → photolithography → etching → thin film deposition → interconnection → test → packaging.
The wafer processing means that the manufactured single crystal cylinder is cut into a circular slice. The oxidation process refers to the formation of an oxide layer by the flow of oxygen or vapor over the wafer surface. Photolithography refers to "printing" a circuit pattern on a wafer by light, and after the photolithography of the circuit pattern on the wafer is completed, an etching process is required to remove an excess oxide film, and only the circuit pattern is left. In order to create a micro device inside a chip, it is necessary to continuously deposit a layer of thin film and remove the redundant portion thereof by etching, thereby finally forming a multi-layer semiconductor structure. Then, the power and the signal are connected to realize the transmission and the reception of the power and the signal, and then whether the quality of the semiconductor chip reaches a certain standard is checked through a test, so that the defective products are eliminated, and the reliability of the chip is improved.
The packaging is a shell for mounting the semiconductor device, which not only plays a role in placing, fixing, sealing and protecting the semiconductor device, but also is a bridge for communicating the semiconductor device with an external circuit, and a joint on the semiconductor device is connected to pins of the packaging shell by leads, and the pins are connected with other devices by leads on a printed board.
When the semiconductor device is in operation, if the power consumption exceeds a critical value, the problems of thermal instability and thermal breakdown are caused, and many parameters of the semiconductor device are also adversely affected due to temperature rise, so that the package structure needs to ensure heat dissipation performance on the basis of ensuring fixation and sealing so as to limit the internal temperature of the semiconductor device not to exceed a certain value.
Document CN111933598A discloses a heat dissipation type semiconductor package product, which comprises a chip carrier, a chip and a package colloid, wherein the chip is fixed in a chip carrying area of the chip carrier, an electrode of the chip is connected with the chip carrier through a metal wire, the package colloid wraps the chip and is connected with the chip carrier, and a metal heat dissipation tube is arranged on one side of the chip carrier, which is back to the chip.
Document CN201616430U discloses a package structure of an integrated circuit, in which a chip and a pin are disposed on a surface of a chip carrier, the chip and the chip carrier are bonded together by a solder, an insulating pad is disposed between the pin and the chip carrier, the pin is electrically connected to the chip by a connecting wire, and a package colloid covers the chip and the chip carrier.
In the two schemes, the bottom of the chip is in contact with the chip carrier, and the side part and the top of the chip are in contact with the packaging colloid, so that heat generated by the chip is not easy to dissipate, and the service performance of the chip is influenced. Therefore, the invention provides a semiconductor component, a preparation method thereof and a semiconductor device, which increase the effective heat conduction area and can improve the heat dissipation efficiency, thereby limiting the internal temperature of the semiconductor component not to exceed a certain value and improving the use reliability.
A semiconductor assembly 100 according to an embodiment of the invention is described below with reference to fig. 1-8.
As shown in fig. 1 and 2, a semiconductor assembly 100 according to an embodiment of the present invention includes a first electrical carrier plate 11, a second electrical carrier plate 12 and a semiconductor device 20.
The first electrical carrier 11 and the second electrical carrier 12 respectively have an electrical connection portion 133 so as to be capable of connecting an external circuit through the electrical connection portion 133, the semiconductor device 20 is disposed between the first electrical carrier 11 and the second electrical carrier 12, the first electrode 21 of the semiconductor device 20 is electrically connected to the first electrical carrier 11, and the second electrode 22 of the semiconductor device 20 is electrically connected to the second electrical carrier 12.
Further, the semiconductor assembly 100 further includes a package 30, the package 30 encloses the semiconductor device 20, the connection between the first electrode 21 and the first electrical carrier 11, and the connection between the second electrode 22 and the second electrical carrier 12, that is, the package 30 forms a housing of the semiconductor assembly 100, and can protect the semiconductor device 20, the connection between the first electrode 21 and the first electrical carrier 11, and the connection between the second electrode 22 and the second electrical carrier 12, so that on one hand, the semiconductor device 20 can be isolated from the outside, and the corrosion of the semiconductor device 20 by impurities in the air to cause the decrease of electrical performance can be prevented, and on the other hand, the mounting and fixing effects can be achieved, so that the packaged semiconductor device 20 is more convenient to mount and transport.
The first electrical carrier 11 has a first heat sink portion 111, the second electrical carrier 12 has a second heat sink portion 121, at least a portion of the electrical connection portion 133 is exposed out of the package 30 for facilitating connection with an external circuit, the first heat sink portion 111 is exposed out of the package 30, and the second heat sink portion 121 is exposed out of the package 30, so that heat generated by the semiconductor device 20 can be dissipated by the first heat sink portion 111 and the second heat sink portion 121.
According to the semiconductor assembly 100 of the embodiment of the invention, the first electrical carrier plate 11 and the second electrical carrier plate 12 electrically connected to the semiconductor device 20 are arranged, at least a part of the first electrical carrier plate 11 is exposed out of the package 30 to form the first heat dissipation part 111, and at least a part of the second electrical carrier plate 12 is exposed out of the package 30 to form the second heat dissipation part 121, so that heat dissipation can be performed through the first heat dissipation part 111 and the second heat dissipation part 121, that is, two heat dissipation paths are formed, the heat conduction area of the semiconductor device 20 is increased, the heat dissipation efficiency of the semiconductor device 20 is further improved, the internal temperature of the semiconductor device 20 is limited not to exceed a certain value, and the use reliability of the semiconductor assembly 100 is improved.
As shown in fig. 3-4, according to some embodiments of the present invention, the semiconductor device 20 is mounted on the first electrical carrier board 11, the first heat dissipation portion 111 forms a first heat dissipation surface, and a projection of the first electrode 21 on a plane of the first heat dissipation surface at least partially coincides with the first heat dissipation surface.
In this way, the heat generated by the semiconductor device 20 can be directly conducted to the first electrical carrier 11, and particularly, the heat generated by the first electrode 21 can be directly conducted to the position of the first electrical carrier 11 opposite to the first electrode 21, and since the first heat dissipation surface is exposed out of the package 30, the heat conducted to the first electrical carrier 11 can be quickly dissipated from the first heat dissipation surface, thereby shortening the heat dissipation path and facilitating the improvement of the heat dissipation efficiency.
In some embodiments, the projection of the first electrode 21 on the plane of the first heat dissipation surface is located in the first heat dissipation surface, so as to increase the heat dissipation area exposed outside the package 30, and the heat generated by the first electrode 21 can be directly conducted to the first heat dissipation surface, thereby further improving the heat dissipation efficiency of the semiconductor device 20 and improving the reliability of the semiconductor assembly 100.
Specifically, the first electrode 21 is disposed opposite to the first heat dissipation surface, and a projection of the first electrode 21 on a plane where the first heat dissipation surface is located is smaller than or equal to an area of the first heat dissipation surface, where the shape of the first heat dissipation surface may be circular, square, or the like, and may be selected according to actual situations.
In some embodiments, the first heat dissipation surface is flush with the outer surface of the package 30. That is, the exposed portion of the first electrical carrier 11 is flush with the outer surface of the package 30, so as to prevent the exposed portion of the first electrical carrier 11 outside the package 30 from interfering with other structures, thereby ensuring that the semiconductor assembly 100 can be normally mounted.
As shown in fig. 4, in some embodiments, the semiconductor device 20 is attached to the first electrical carrier plate 11 by a thermally conductive connection layer 51.
Thus, by providing the heat conductive connection layer 51, not only is the connection reliability between the first electrical carrier 11 and the semiconductor device 20 ensured, but also a part of the heat generated by the semiconductor device 20 can be conducted to the first electrical carrier 11 through the heat conductive connection layer 51 and finally dissipated from the first heat dissipation portion 111, thereby improving the heat dissipation efficiency of the semiconductor device 20.
The thickness of the thermal conductive connection layer 51 may be controlled to be between 20 micrometers and 70 micrometers, for example, the thickness of the thermal conductive connection layer 51 may be 20 micrometers, 40 micrometers, 50 micrometers, 70 micrometers, and the like.
In some examples, the thermally conductive connection layer 51 is provided between the semiconductor device 20 and the first electrical carrier plate 11 by a printing process.
Specifically, before the semiconductor device 20 is mounted on the first electrical-carrier plate 11, the heat-conducting connection layer 51 may be printed on a predetermined position of the first electrical-carrier plate 11, and then the semiconductor device 20 is placed on the heat-conducting connection layer 51, so as to achieve the positioning and mounting of the semiconductor device 20. The printing process is simple to operate and easy to implement, and the heat-conducting connecting layer 51 formed by the printing process is better in quality and higher in production efficiency.
In other examples, the thermally conductive connection layer 51 is provided between the semiconductor device 20 and the first electrical carrier plate 11 by a coating process. The heat-conducting connecting layer 51 formed by the coating process has high material utilization rate, avoids material waste and has high production efficiency.
In some examples, the material of the thermally conductive connection layer 51 is tin or silver. Specifically, the heat conductive connection layer 51 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the heat conductive connection layer may not only serve to connect the semiconductor device 20 and the first electrical carrier 11, but also serve to conduct heat generated by the semiconductor device 20 to the first electrical carrier 11.
As shown in fig. 4, in some embodiments, the projection of the second electrode 22 onto the plane of the first heat dissipation surface at least partially coincides with the first heat dissipation surface. Thus, the heat generated by the second electrode 22 can be directly conducted to the position of the first electrical carrier 11 opposite to the second electrode 21, and the first heat dissipation surface exposes out of the package 30, so that the heat conducted to the first electrical carrier 11 can be dissipated from the first heat dissipation surface, thereby shortening the heat dissipation path and being beneficial to improving the heat dissipation efficiency.
In some examples, the projection of the second electrode 22 on the plane of the first heat dissipation surface is located in the first heat dissipation surface, so as to increase the heat dissipation area exposed outside the package 30, and the heat generated by the second electrode 22 can be directly conducted to the second heat dissipation surface, thereby further improving the heat dissipation efficiency of the semiconductor device 20 and improving the reliability of the semiconductor assembly 100.
Specifically, the second electrode 22 is disposed opposite to the first heat dissipation surface, a projection of the second electrode 22 on a plane where the first heat dissipation surface is located is smaller than or equal to an area of the first heat dissipation surface, and the shape of the first heat dissipation surface may be circular, square, or the like, which may be selected according to actual situations.
As shown in fig. 1-2 and 4, in this embodiment, the projection of the semiconductor device 20 on the plane of the first heat dissipation surface is located in the first heat dissipation surface, so as to increase the heat dissipation area exposed outside the package 30, further improve the heat dissipation efficiency of the semiconductor device 20, and improve the reliability of the semiconductor assembly 100.
As shown in fig. 5, according to some embodiments of the present invention, the semiconductor assembly 100 further includes a first connecting element 41, one end of the first connecting element 41 is electrically connected to the first electrode 21, the other end of the first connecting element 41 is electrically connected to the first electrical carrier 11, and the package 30 encloses the first connecting element 41.
That is to say, after the packaging, the package 30 may wrap the semiconductor device 20, the connection between the first electrode 21 of the semiconductor device 20 and one end of the first connecting element 41, and the connection between the first connecting element 41 and the other end of the first connecting element 41 and the first electrical carrier 11, so as to prevent the connection between the first electrode 21 and one end of the first connecting element 41, and the connection between the first connecting element 41, the other end of the first connecting element 41 and the first electrical carrier 11 from being broken, and ensure the connection reliability between the first connecting element 41 and the first electrical carrier 11, and between the first connecting element 41 and the first electrode 21 of the semiconductor device 20.
In some embodiments, the first connectors 41 form metal connecting wires.
Specifically, a wire bonding process may be adopted to electrically connect the first electrode 21 of the semiconductor device 20 and the electrical connection portion 133 of the first electrical carrier 11, so as to form the first connection member 41 between the first electrode 21 and the electrical connection portion 133 of the first electrical carrier 11.
It should be noted that the wire bonding refers to using a metal wire and utilizing a thermal pressing or an ultrasonic energy to complete the connection of the interconnection wires inside the solid circuit in the microelectronic device, so that the first electrode 21 and the electrical connection portion 133 of the first electrical carrier 11 are connected together by a wire bonding process, and a metal connection wire can be formed therebetween.
In other embodiments, the first connector 41 forms a metal tab. The metal connecting sheet has higher structural strength, which is beneficial to ensuring the connection reliability between the first connecting piece 41 and the first electrode 21 and between the first connecting piece 41 and the first electrical carrier 11.
As shown in fig. 5, in some examples, a first connection layer 52 is disposed between one end of the first connection element 41 and the first electrode 21, the first connection layer 52 may electrically connect one end of the first connection element 41 with the first electrode 21, the first connection layer 52 is disposed between the other end of the first connection element 41 and the first electrical carrier 11, and the first connection layer 52 may electrically connect the other end of the first connection element 41 with the first electrical carrier 11, so that the first electrode 21 of the semiconductor device 20 is electrically connected with the first electrical carrier 11.
The thickness of the first connection layer 52 may be controlled to be between 20 micrometers and 70 micrometers, for example, the thickness of the first connection layer 52 may be 20 micrometers, 40 micrometers, 50 micrometers, 70 micrometers, and the like.
In some specific examples, the first connection layer 52 is provided to the first electrical carrier 11 by a printing process.
Specifically, before electrically connecting the first electrical carrier plate 11 with the first electrode 21 of the semiconductor device 20, the first connection layer 52 may be printed on a predetermined position of the first electrical carrier plate 11 and the first electrode 21, and then both ends of the first connecting member 41 are connected to the first connection layer 52 on the first electrical carrier plate 11 and the first connection layer 52 on the first electrode 21, respectively, so as to electrically connect the first electrode 21 with the first electrical carrier plate 11 by using the first connecting member 41. The printing process is simple to operate and easy to implement, and the quality of the first connection layer 52 formed by the printing process is better and the production efficiency is higher.
Of course, the first connection layer 52 may also be provided on the predetermined position of the first electrical support plate 11 and on the first electrode 21 by a coating process. The first connection layer 52 formed by the coating process has a high material utilization rate, avoids waste of materials, and has high production efficiency.
Wherein, the material of the first connection layer 52 is tin or silver.
Specifically, the first connection layer 52 may be curable liquid tin, liquid silver, or the like, after the liquid tin or the liquid silver is cured, the first connection layer 52 located between the first connecting member 41 and the first electrode 21 may function to connect one end of the first connecting member 41 and the first electrode 21, and may also function as a heat conducting layer, and the first connection layer 52 located between the first connecting member 41 and the first electrical carrier 11 may function to connect the other end of the first connecting member 41 and the first electrical carrier 11, and may also function as a heat conducting layer.
As shown in fig. 6 and 7, according to some embodiments of the present invention, the semiconductor assembly 100 further includes a second connecting member 42, one end of the second connecting member 42 is electrically connected to the second electrode 22, the other end of the second connecting member 42 is electrically connected to the second electrical carrier 12, and the package 30 encapsulates the second connecting member 42.
That is to say, after the package is packaged, the package 30 may wrap the semiconductor device 20, the connection between the second electrode 22 of the semiconductor device 20 and one end of the second connecting member 42, and the connection between the second connecting member 42 and the other end of the second connecting member 42 and the second electrical carrier 12, so as to prevent the connection between the second electrode 22 of the semiconductor device 20 and one end of the second connecting member 42, and the connection between the second connecting member 42 and the other end of the second connecting member 42 and the second electrical carrier 12 from being broken, and ensure the connection reliability between the second connecting member 42 and the second electrical carrier 12, and between the second connecting member 42 and the second electrode 22 of the semiconductor device 20.
In some embodiments, the second heat dissipating portion 121 forms a second heat dissipating surface, and a projection of the other end of the second connecting member 42 on a plane of the second heat dissipating surface at least partially coincides with the second heat dissipating surface.
In this way, the heat generated by the semiconductor device 20 can be conducted to the second electrical carrier 12, and particularly, the heat generated by the second electrode 22 can be conducted to the position of the second electrical carrier 12 opposite to the second connecting member 42 through the second connecting member 42, and since the second heat dissipation surface is exposed out of the package 30, the heat conducted to the second electrical carrier 12 can be dissipated from the second heat dissipation surface, so that another heat dissipation path is added, thereby achieving double-sided heat dissipation and facilitating improvement of heat dissipation efficiency.
In some examples, the projection of the other end of the second connecting member 42 on the plane of the second heat dissipation surface is located in the second heat dissipation surface, so as to increase the heat dissipation area exposed outside the package body 30, and the heat generated by the second electrode 22 can be conducted to the second heat dissipation surface through the second connecting member 42, thereby further improving the heat dissipation efficiency of the semiconductor device 20 and the reliability of the semiconductor assembly 100.
Specifically, the other end of the second connecting member 42 is disposed opposite to the second heat dissipating surface, and a projection of the other end of the second connecting member 42 on a plane where the second heat dissipating surface is located is smaller than or equal to an area of the second heat dissipating surface, where the second heat dissipating surface may be circular, square, or the like, and may be selected according to actual conditions.
In some examples, the second heat dissipation surface is flush with an outer surface of the package body 30. That is, the exposed portion of the second electrical carrier 12 is flush with the outer surface of the package 30, so as to prevent the exposed portion of the second electrical carrier 12 outside the package 30 from interfering with other structures, thereby ensuring that the semiconductor device 100 can be normally mounted.
As shown in fig. 6-8, in some embodiments, the second connector 42 forms a metal connection post. The metal connection posts are disposed between the first electrical carrier 11 and the second electrical carrier 12, so that the first electrical carrier 11 and the second electrical carrier 12 can be separated to provide a mounting space for the semiconductor device 20.
Specifically, as shown in fig. 7 and 8, in the present embodiment, the first electrical carrier 11 and the second electrical carrier 12 are arranged at intervals in the up-down direction, the second connecting member 42 forms a metal connecting column extending in the up-down direction, the lower end of the second connecting member 42 is electrically connected to the second electrode 22 of the first electrical carrier 11, and the upper end of the second connecting member 42 is electrically connected to the second electrical carrier 12, so that the second electrode 22 is electrically connected to the second electrical carrier 12 by the second connecting member 42.
In some examples, the cross-sectional dimension of the other end (the upper end as shown in fig. 7 and 8) of the second connector 42 is larger than the cross-sectional dimension of the middle portion of the second connector 42, so as to improve the structural strength of the second connector 42 and ensure the supporting reliability of the second connector 42 on the second electrical carrier 12.
For example, the cross-sectional area of the second connection member 42 gradually increases from the first electrical carrier 11 to the second electrical carrier 12; for another example, the second connecting element 42 is divided into a plurality of connecting posts along the axial direction thereof, and the cross-sectional dimension of one connecting post close to the second electrical carrier 12 is larger than that of one connecting post close to the first electrical carrier 11.
As shown in fig. 7, in some embodiments, a second connection layer 53 is disposed between one end of the second connection element 42 and the second electrode 22, the second connection layer 53 may electrically connect one end of the second connection element 42 with the second electrode 22, a second connection layer 53 is disposed between the other end of the second connection element 42 and the second electrical carrier 12, and the second connection layer 53 may electrically connect the other end of the second connection element 42 with the second electrical carrier 12, so as to electrically connect the second electrode 22 of the semiconductor device 20 with the second electrical carrier 12.
The thickness of the second connection layer 53 may be controlled between 20 micrometers and 70 micrometers, for example, the thickness of the second connection layer 53 may be 20 micrometers, 40 micrometers, 50 micrometers, 70 micrometers, or the like.
In some specific examples, the second connection layer 53 is disposed on the second electrode 22 of the semiconductor device 20 at a predetermined position of the second electrical carrier 12 through a printing process.
Specifically, before electrically connecting the second electrical carrier 12 with the second electrode 22 of the semiconductor device 20, the second connection layer 53 may be printed on the second electrode 22 and a predetermined position of the second electrical carrier 12, and then both ends of the second connector 42 are connected to the second connection layer 53 on the second electrical carrier 12 and the second connection layer 53 on the second electrode 22, respectively, so as to electrically connect the second electrode 22 with the second electrical carrier 12 by using the second connector 42. The printing process is simple to operate and easy to implement, and the second connection layer 53 formed by the printing process has better quality and higher production efficiency.
Of course, the second connection layer 53 can also be disposed on the predetermined position of the second electrical carrier 12 and the second electrode 22 by a coating process. The second connection layer 53 formed through the coating process has a high material utilization rate, avoids waste of materials, and has high production efficiency.
Wherein, the material of the second connection layer 53 is tin or silver.
Specifically, the second connection layer 53 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the second connection layer 53 located between the second connection member 42 and the second electrode 22 may serve to connect one end of the second connection member 42 to the second electrode 22 and also serve to conduct heat. The second connection layer 53 located between the second connection element 42 and the second electrical carrier 12 can serve to connect the other end of the second connection element 42 to the second electrical carrier 12 and also serve to conduct heat.
As shown in fig. 3, 7-8, each of the first and second electrical carriers 11 and 12 includes a carrier body 131, and the carrier body 131 of the first electrical carrier 11 and the carrier body 131 of the second electrical carrier 12 are disposed opposite to and spaced apart from each other.
Further, the first heat sink portion 111 is located on the carrier body 131 of the first electrical carrier 11, and the second heat sink portion 121 is located on the carrier body 131 of the second electrical carrier 12.
The semiconductor device 20 is disposed between the two carrier bodies 131, the two carrier bodies 131 can protect the semiconductor device 20, the first electrode 21 is connected to the electrical connection portion 133 of the first electrical carrier 11, and the second electrode 22 is electrically connected to the carrier body 131 of the second electrical carrier 12.
Specifically, as shown in fig. 7, in the present embodiment, the first electrical carrier 11 includes a carrier body 131 and an electrical connection portion 133 that are connected, the second electrical carrier 12 includes a carrier body 131 and an electrical connection portion 133 that are connected, the carrier body 131 of the first electrical carrier 11 and the carrier body 131 of the second electrical carrier 12 are disposed opposite to each other in the vertical direction, the electrical connection portion 133 of the first electrical carrier 11 is disposed on one side of the carrier body 131 of the first electrical carrier 11, and the electrical connection portion 133 of the second electrical carrier 12 is disposed on the other side of the carrier body 131 of the second electrical carrier 12, that is, the electrical connection portion 133 of the first electrical carrier 11 and the electrical connection portion 133 of the second electrical carrier 12 are disposed on different sides of the corresponding carrier bodies 131, so that the electrical connection portions 133 can be led out from different directions, and the mounting reliability of the semiconductor assembly 100 is ensured.
The semiconductor device 20 is disposed between the carrier body 131 of the first electrical carrier 11 and the carrier body 131 of the second electrical carrier 12, the active surface of the semiconductor device 20 faces the carrier body 131 of the second electrical carrier 12, and the surface of the semiconductor device 20 opposite to the active surface faces the carrier body 131 of the first electrical carrier 11.
In some examples, one side surfaces of the two carrier body 131 opposite to each other are exposed out of the package body 30 to form a first heat sink portion 111 and a second heat sink portion 121, respectively.
That is to say, the first heat sink portion 111 faces the first electrode 21 and the second electrode 21 of the semiconductor device 20, heat generated by the semiconductor device 20, particularly heat generated by the first electrode 21 and the second electrode 22, can be directly conducted to the first heat sink portion 111, the second heat sink portion 121 faces the first electrode 21 and the second electrode 21 of the semiconductor device 20, heat generated by the second electrode 21 can be conducted to the second heat sink portion 121 through the second connecting member 42, and finally, heat is dissipated, so that the requirement of double-side heat dissipation of the semiconductor device is met, the internal temperature of the semiconductor device 20 can be limited not to exceed a certain value, and the use reliability of the semiconductor assembly 100 is improved.
In some examples, the electrical connection portions 133 include pins, one ends of the two pins are connected to the outer periphery of the corresponding carrier body 131 through the connection sections 132, and the other ends of the two pins extend out of two opposite sides of the package body 30, so as to facilitate connection with an external circuit.
Specifically, as shown in fig. 8, each of the first and second electrical carriers 11 and 12 includes a carrier body 131, a connection section 132 and a pin, the connection section 132 is connected between the carrier body 131 and one end of the pin, and after the first and second electrical carriers 11 and 12 and the semiconductor device 10 are packaged, the package 30 is formed to wrap the semiconductor device 20, the first and second connectors 41 and 42 and the connection section 132, a portion of the carrier body 131 and one end of the pin of each of the first and second electrical carriers 11 and 12, thereby forming protection and ensuring the reliability of the structure and electrical performance of the semiconductor assembly 100.
In some specific examples, the two connecting segments 132 extend obliquely in a direction away from each other and in a direction away from the carrier body 131, so that the pins can be led out from different directions, and the mounting requirements of the semiconductor assembly 100 can be met.
As shown in fig. 1, in some specific examples, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 are bent toward the second heat sink member 121 through a trimming and bending process, so that one side of the second heat sink member 121 can be mounted on the substrate, and the pins of the first electrical carrier 11 and the pins of the second electrical carrier 12 can be connected to pads on the substrate, thereby realizing the mounting of the semiconductor assembly 100 on the substrate and the connection of the semiconductor device 20 to an external circuit.
In some specific examples, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 are flush with the second heat sink portion 121, so that the second heat sink portion 121 does not interfere with the substrate when the pins of the first electrical carrier 11 and the pins of the second electrical carrier 12 are connected to the substrate.
As shown in fig. 2, in other specific examples, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 are bent toward the first heat sink member 111 through a trimming and bending process, so that one side of the first heat sink member 111 can be mounted on the substrate, and the pins of the first electrical carrier 11 and the pins of the second electrical carrier 12 can be connected to pads on the substrate, thereby realizing the mounting of the semiconductor assembly 100 on the substrate and the connection of the semiconductor device 20 to an external circuit.
In some specific examples, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 are flush with the first heat sink portion 111, so that when the pins of the first electrical carrier 11 and the pins of the second electrical carrier 12 are connected to the substrate, the first heat sink portion 111 does not interfere with the substrate.
It should be noted that, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 may be bent through a rib-cutting bending process, so as to implement different planar designs, and meet the requirements of the packages 30 with different thicknesses by designing different bending depths.
In addition, the pins of the first electrical carrier 11 and the second electrical carrier 12 may be bent in different directions through a rib cutting and bending process according to the heat dissipation requirement and the difference of the heat dissipation paths, for example, the pins of the first electrical carrier 11 and the second electrical carrier 12 may be bent toward the first heat dissipation portion 111 or the second heat dissipation portion 121 through the rib cutting and bending process, so that the top or the bottom is exposed.
According to some embodiments of the present invention, the number of semiconductor devices 20 may be two.
Specifically, one of the semiconductor devices 20 is attached to the upper surface of the first electrical carrier 11, the first electrode 21 of the semiconductor device 20 is electrically connected to the first electrical carrier 11, and the second electrode 22 of the semiconductor device 20 is electrically connected to the second electrical carrier 12. And another semiconductor device 20 is attached to the lower surface of the second electrical carrier 12, the first electrode 21 of the semiconductor device 20 is electrically connected with the second electrical carrier 12, the second electrode 22 of the semiconductor device 20 is electrically connected with the first electrical carrier 11, and after packaging, sealing of the two semiconductor devices 20 is realized, and each semiconductor device 20 can realize double-sided heat dissipation, so that the heat dissipation efficiency is high.
Of course, the number of the semiconductor devices 20 may include only one or two or more. The selection and arrangement can be specifically carried out according to actual requirements. For embodiments in which the semiconductor device 20 includes more than two, the arrangement of the plurality of semiconductor devices 20 may be similar to embodiments in which the semiconductor device 20 includes two, and will not be described again.
According to some embodiments of the present invention, the first electrical carrier plate 11 and the second electrical carrier plate 12 are metal frames. The first and second electrical carriers 11, 12 are, for example, copper frames.
The first electrical carrier 11 serves as a carrier of the semiconductor device 20, and not only can support the semiconductor device 20, but also can conduct heat and electricity, and by configuring the first electrical carrier 11 as a metal frame, the structural strength of the first electrical carrier 11 can be ensured while the above effects are ensured.
Similarly, by providing the second electrical carrier 12 as a metal frame, the semiconductor device 20 can be protected and can also perform the functions of heat conduction and electricity conduction.
In addition, the semiconductor device 20 is disposed between the first electrical carrier 11 and the second electrical carrier 12, and the first electrical carrier 11 and the second electrical carrier 12 are encapsulated in the same package 30, so that the semiconductor assembly 100 has the advantage of low package cost.
A semiconductor device according to an embodiment of the present invention is described below with reference to the drawings.
The semiconductor device according to an embodiment of the present invention includes the semiconductor assembly 100 according to the above-described embodiment and a heat sink (not shown in the figure) provided to the first heat sink member 111 or the second heat sink member 121.
Since the semiconductor assembly according to the embodiment of the present invention has the above technical effects, the semiconductor device according to the embodiment of the present invention also has the above technical effects, that is, by using the semiconductor assembly 100 and the heat sink, heat can be dissipated through the first heat dissipation portion 111 and the second heat dissipation portion 121, and the heat sink can dissipate heat of the first heat dissipation portion 111 or the second heat dissipation portion 121, that is, two heat dissipation paths are formed, so that the heat conduction area of the semiconductor device 20 is increased, the heat dissipation efficiency of the semiconductor device 20 is further improved, the internal temperature of the semiconductor device 20 can be limited not to exceed a certain value, and the use reliability of the semiconductor assembly 100 is improved.
In some embodiments, the heat sink is connected to the first heat sink portion 111, and the side of the second heat sink portion 121 can be mounted on the substrate, so that the heat of the first heat sink portion 111 can be further dissipated by the heat sink, and the heat of the second heat sink portion 121 can be further dissipated by the substrate.
In other embodiments, the heat sink is connected to the second heat sink portion 121, and the side of the first heat sink portion 111 may be mounted on the substrate, so that heat on the second heat sink portion 121 may be further dissipated by the heat sink, and heat on the first heat sink portion 111 may be further dissipated by the substrate.
According to some embodiments of the present invention, the heat sink includes a heat dissipation plate and a plurality of heat dissipation fins, the plurality of heat dissipation fins are disposed at intervals on one side surface of the heat dissipation plate, and the other side surface of the heat dissipation plate is connected to the first heat dissipation part 111 or the second heat dissipation part 121. The structure of the heat sink is not limited in the present invention, and any structure that can realize heat conduction and heat dissipation is within the protection scope of the present invention.
A method of manufacturing a semiconductor assembly 100 according to an embodiment of the present invention is described below with reference to fig. 1 to 9.
As shown in fig. 1-8, a semiconductor assembly 100 according to an embodiment of the invention includes a first electrical carrier 11, a second electrical carrier 12, and a semiconductor device 20, wherein the semiconductor device 20 is mounted on the first electrical carrier 11, the second electrical carrier 12 covers the semiconductor device 20, such that the semiconductor device 20 is located between the first electrical carrier 11 and the second electrical carrier 12, a first electrode 21 of the semiconductor device 20 is electrically connected to the first electrical carrier 11, and a second electrode 22 of the semiconductor device 20 is electrically connected to the second electrical carrier 12.
As shown in fig. 9, the method for manufacturing a semiconductor device includes the steps of:
s1, providing a semiconductor device, a first electric carrier plate and a second electric carrier plate;
s2, mounting the semiconductor device on the first electric carrier plate, and electrically connecting a first electrode of the semiconductor device with the first electric carrier plate;
in particular, the semiconductor device 20 may be attached to the first electrical-carrier plate 11 by a thermally conductive connection layer 51. By providing the heat-conducting connecting layer 51, not only the connection reliability between the first electrical carrier 11 and the semiconductor device 20 is ensured, but also a part of heat generated by the semiconductor device 20 can be conducted to the first electrical carrier 11 through the heat-conducting connecting layer 51 and finally dissipated from the first heat dissipation portion 111, thereby improving the heat dissipation efficiency of the semiconductor device 20.
A thermally conductive connection layer 51 is provided between the semiconductor device 20 and the first electrical carrier plate 11 by means of a printing process. Specifically, before the semiconductor device 20 is mounted on the first electrical-carrier plate 11, the heat-conducting connection layer 51 may be printed on a predetermined position of the first electrical-carrier plate 11, and then the semiconductor device 20 is placed on the heat-conducting connection layer 51, so as to achieve the positioning and mounting of the semiconductor device 20. The printing process is simple to operate and easy to implement, and the heat-conducting connecting layer 51 formed by the printing process is better in quality and higher in production efficiency. Of course, a thermally conductive connection layer 51 is also provided between the semiconductor device 20 and the first electrical carrier plate 11 by means of a coating process. The heat-conducting connecting layer 51 formed by the coating process has high material utilization rate, avoids material waste and has high production efficiency.
The material of the heat conductive connection layer 51 is tin or silver. Specifically, the heat conductive connection layer 51 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the heat conductive connection layer can serve to connect the semiconductor device 20 and the first electrical carrier 11, and also can serve to conduct heat generated by the semiconductor device 20 to the first electrical carrier 11.
S3, arranging a second electric carrier plate on one side of the semiconductor device, which is back to the first electric carrier plate, and electrically connecting a second electrode of the semiconductor device with the second electric carrier plate to obtain a pre-assembly structure;
s4, packaging the pre-assembly structure to form a packaging body outside the pre-assembly structure;
specifically, before the package is performed, a package mold corresponding to the pre-assembly structure may be manufactured, and then the pre-assembly structure and an Epoxy Molding Compound (EMC) are placed in the package mold and sealed, so that the epoxy molding compound covers the semiconductor device 20, the peripheral wall of the first electrical carrier 11 and the side facing the semiconductor device 20, the peripheral wall of the second electrical carrier 12 and the side facing the semiconductor device 20, that is, in the structure of the first electrical carrier 11 and the second electrical carrier 12, only the pins, the first heat dissipation part 111 and the second heat dissipation part 121 are exposed, thereby obtaining the semiconductor assembly 100 shown in fig. 8.
After packaging, the formed package 30 serves as a housing of the semiconductor assembly 100, and can protect the semiconductor device 20, the joint between the first electrode 21 and the first electrical carrier 11, and the joint between the second electrode 22 and the second electrical carrier 12, so that on one hand, the semiconductor device 20 can be isolated from the outside, and the impurities in the air can be prevented from corroding the semiconductor device 20 to cause the electrical performance to be degraded, and on the other hand, the package can play a role in mounting and fixing, so that the packaged semiconductor device 20 is more convenient to mount and transport.
The first electrical carrier 11 has a first heat sink portion 111 and an electrical connection portion 133, the electrical connection portion 133 is used for connecting an external circuit, the second electrical carrier 12 has a second heat sink portion 121 and an electrical connection portion 133, the electrical connection portion 133 is used for connecting an external circuit, and the first heat sink portion 111, the two electrical connection portions 133, and the second heat sink portion 121 are exposed out of the package 30.
According to the method for manufacturing the semiconductor assembly 100 of the embodiment of the invention, the first electrical carrier plate 11 and the second electrical carrier plate 12 electrically connected to the semiconductor device 20 are arranged, at least a part of the first electrical carrier plate 11 is exposed out of the package 30 to form the first heat dissipation part 111, and at least a part of the second electrical carrier plate 12 is exposed out of the package 30 to form the second heat dissipation part 121, so that heat dissipation can be performed through the first heat dissipation part 111 and the second heat dissipation part 121, that is, two heat dissipation paths are formed, the heat conduction area of the semiconductor device 20 is increased, the heat dissipation efficiency of the semiconductor device 20 is further improved, the internal temperature of the semiconductor device 20 is limited not to exceed a certain value, and the use reliability of the semiconductor assembly 100 is improved.
As shown in fig. 5 and 8, according to some embodiments of the present invention, electrically connecting the first electrode 21 of the semiconductor device 20 with the first electrical carrier plate 11 includes: the first electrode 21 is connected to the electrical connection 133 of the first electrical carrier 11 by a first connection 41.
After packaging, the package 30 may wrap the semiconductor device 20, the connection between the first electrode 21 of the semiconductor device 20 and one end of the first connecting element 41, and the connection between the other end of the first connecting element 41 and the first electrical carrier 11, so as to prevent the connection between the first electrode 21 and one end of the first connecting element 41, and the connection between the first connecting element 41, the other end of the first connecting element 41 and the first electrical carrier 11 from being broken, and ensure the connection reliability between the first connecting element 41 and the first electrical carrier 11, and between the first connecting element 41 and the first electrode 21 of the semiconductor device 20.
In some embodiments, the first connectors 41 form metal connecting wires.
Specifically, a wire bonding process may be adopted to electrically connect the first electrode 21 of the semiconductor device 20 and the electrical connection portion 133 of the first electrical carrier 11, so as to form the first connection member 41 between the first electrode 21 and the electrical connection portion 133 of the first electrical carrier 11.
It should be noted that the wire bonding refers to using a metal wire and utilizing a thermal pressing or an ultrasonic energy to complete the connection of the interconnection wires inside the solid circuit in the microelectronic device, so that the first electrode 21 and the electrical connection portion 133 of the first electrical carrier 11 are connected together by a wire bonding process, and a metal connection wire can be formed therebetween.
In other embodiments, the first connector 41 forms a metal tab. The metal connecting sheet has higher structural strength, which is beneficial to ensuring the connection reliability between the first connecting piece 41 and the first electrode 21 and between the first connecting piece 41 and the first electrical carrier 11.
As shown in fig. 5, in some examples, a first connection layer 52 is disposed between one end of the first connection element 41 and the first electrode 21, the first connection layer 52 may electrically connect one end of the first connection element 41 with the first electrode 21, the first connection layer 52 is disposed between the other end of the first connection element 41 and the first electrical carrier 11, and the first connection layer 52 may electrically connect the other end of the first connection element 41 with the first electrical carrier 11, so that the first electrode 21 of the semiconductor device 20 is electrically connected with the first electrical carrier 11.
Wherein, the material of the first connection layer 52 is tin or silver.
Specifically, the first connection layer 52 may be curable liquid tin, liquid silver, or the like, after the liquid tin or the liquid silver is cured, the first connection layer 52 located between the first connecting member 41 and the first electrode 21 may not only serve to connect one end of the first connecting member 41 to the first electrode 21, but also serve to conduct heat, and the first connection layer 52 located between the first connecting member 41 and the first electrical carrier 11 may serve to connect the other end of the first connecting member 41 to the first electrical carrier 11, and also serve to conduct heat.
As shown in fig. 6-8, electrically connecting the second electrode 22 of the semiconductor device 20 with the second electrical carrier 12, according to some embodiments of the present invention, includes: the second electrode 22 is connected to the second electrical carrier 12 by a second connection 42.
After packaging, the package 30 may wrap the semiconductor device 20, the joint between the second electrode 22 of the semiconductor device 20 and one end of the second connecting element 42, the joint between the second connecting element 42 and the other end of the second connecting element 42 and the second electrical carrier 12, so as to prevent the joint between the second electrode 22 of the semiconductor device 20 and one end of the second connecting element 42, and the joint between the second connecting element 42 and the other end of the second connecting element 42 and the second electrical carrier 12 from being broken, thereby ensuring the connection reliability between the second connecting element 42 and the second electrical carrier 12, and between the second connecting element 42 and the second electrode 22 of the semiconductor device 20.
In some embodiments, the second heat dissipation part 121 forms a second heat dissipation surface, and a projection of the other end of the second connection part 42 on a plane of the second heat dissipation surface at least partially coincides with the second heat dissipation surface.
In this way, the heat generated by the semiconductor device 20 can be conducted to the second electrical carrier 12, and particularly, the heat generated by the second electrode 22 can be conducted to the position of the second electrical carrier 12 opposite to the second connecting member 42 through the second connecting member 42, and since the second heat dissipation surface is exposed out of the package 30, the heat conducted to the second electrical carrier 12 can be dissipated from the second heat dissipation surface, so that another heat dissipation path is added, thereby achieving double-sided heat dissipation and facilitating improvement of heat dissipation efficiency.
In some examples, the projection of the other end of the second connection member 42 on the plane of the second heat dissipation surface is located in the second heat dissipation surface, so that the heat dissipation area exposed out of the package body 30 is increased. The heat generated by the second electrode 22 can be conducted to the second heat dissipation surface through the second connection member 42, thereby further improving the heat dissipation efficiency of the semiconductor device 20 and improving the reliability of the semiconductor assembly 100.
Specifically, the other end of the second connecting member 42 is disposed opposite to the second heat dissipating surface, a projection of the other end of the second connecting member 42 on a plane where the second heat dissipating surface is located is smaller than or equal to an area of the second heat dissipating surface, and the shape of the second heat dissipating surface may be circular, square, or the like, and may be selected according to actual situations.
In some examples, the second heat dissipation surface is flush with an outer surface of the package body 30. That is, the exposed portion of the second electrical carrier 12 is flush with the outer surface of the package 30, so as to prevent the exposed portion of the second electrical carrier 12 outside the package 30 from interfering with other structures, thereby ensuring that the semiconductor device 100 can be normally mounted.
As shown in fig. 6-8, in some embodiments, the second connector 42 forms a metal connection post. The metal connection posts are disposed between the first electrical carrier 11 and the second electrical carrier 12, so that the first electrical carrier 11 and the second electrical carrier 12 can be separated to provide a mounting space for the semiconductor device 20.
Specifically, as shown in fig. 7 and 8, in the present embodiment, the first electrical carrier 11 and the second electrical carrier 12 are arranged at intervals in the up-down direction, the second connecting members 42 form metal connecting posts extending in the up-down direction, the lower ends of the second connecting members 42 are electrically connected to the second electrodes 22 of the first electrical carrier 11, and the upper ends of the second connecting members 42 are electrically connected to the second electrical carrier 12, so that the second electrodes 22 are electrically connected to the second electrical carrier 12 by the second connecting members 42.
In some examples, the cross-sectional dimension of the other end (the upper end as shown in fig. 7 and 8) of the second connector 42 is larger than the cross-sectional dimension of the middle portion of the second connector 42, so as to improve the structural strength of the second connector 42 and ensure the supporting reliability of the second connector 42 on the second electrical carrier 12.
For example, the cross-sectional area of the second connection member 42 gradually increases from the first electrical carrier 11 to the second electrical carrier 12; for another example, the second connecting element 42 is divided into a plurality of connecting posts along the axial direction thereof, and the cross-sectional dimension of one connecting post close to the second electrical carrier 12 is larger than that of one connecting post close to the first electrical carrier 11.
As shown in fig. 7, in some embodiments, a second connection layer 53 is disposed between one end of the second connection element 42 and the second electrode 22, the second connection layer 53 may electrically connect one end of the second connection element 42 with the second electrode 22, a second connection layer 53 is disposed between the other end of the second connection element 42 and the second electrical carrier 12, and the second connection layer 53 may electrically connect the other end of the second connection element 42 with the second electrical carrier 12, so as to electrically connect the second electrode 22 of the semiconductor device 20 with the second electrical carrier 12.
Wherein, the material of the second connection layer 53 is tin or silver.
Specifically, the second connection layer 53 may be curable liquid tin, liquid silver, or the like, and after the liquid tin or the liquid silver is cured, the second connection layer 53 located between the second connection member 42 and the second electrode 22 may serve to connect one end of the second connection member 42 to the second electrode 22 and also serve to conduct heat. The second connection layer 53 located between the second connection element 42 and the second electrical carrier 12 can play a role in connecting the other end of the second connection element 42 with the second electrical carrier 12, and can play a role in heat conduction.
According to a further embodiment of the present invention, the electrical connections 133 each include a pin, and after the pre-assembly structure is packaged by a packaging process, the method further includes:
the pins of each of the first electrical carrier 11 and the second electrical carrier 12 are bent toward the first heat sink 111 or the second heat sink 121 by a rib-cutting bending process.
Specifically, as shown in fig. 1, in the present embodiment, after the pre-assembly structure is packaged, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 are bent toward the second heat sink portion 121 through a trimming and bending process, so that when the semiconductor assembly 100 needs to be mounted on a substrate, the side where the second heat sink portion 121 is located can be mounted on the substrate, and the pins of the first electrical carrier 11 and the pins of the second electrical carrier 12 are connected to pads on the substrate, so as to mount the semiconductor assembly 100 on the substrate and connect the semiconductor device 20 to an external circuit.
The pins of each of the first electrical carrier 11 and the second electrical carrier 12 are flush with the second heat sink portion 121, so that when the pins of the first electrical carrier 11 and the pins of the second electrical carrier 12 are connected to the substrate, the second heat sink portion 121 does not interfere with the substrate, and after the semiconductor assembly 100 is mounted on the substrate, the substrate can contact with or be separated from the second heat sink portion 121, and the substrate can also conduct heat, thereby ensuring the heat dissipation efficiency.
As shown in fig. 2, in the present embodiment, after the pre-assembly structure is packaged, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 are bent toward the first heat sink portion 111 through a trimming and bending process, so that when the semiconductor assembly 100 needs to be mounted on a substrate, the side where the first heat sink portion 111 is located can be mounted on the substrate, and the pins of the first electrical carrier 11 and the pins of the second electrical carrier 12 are connected to the pads on the substrate, thereby realizing the mounting of the semiconductor assembly 100 on the substrate and the connection of the semiconductor device 20 to an external circuit.
The pins of each of the first electrical carrier 11 and the second electrical carrier 12 are flush with the first heat dissipation portion 111, so that when the pins of the first electrical carrier 11 and the pins of the second electrical carrier 12 are connected to the substrate, the first heat dissipation portion 111 does not interfere with the substrate, and after the semiconductor assembly 100 is mounted on the substrate, the substrate can contact with or be separated from the first heat dissipation portion 111, and the substrate can also conduct heat, thereby ensuring the heat dissipation efficiency.
Therefore, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 can be bent through the rib-cutting bending process, so that different planar designs can be realized, and the requirements of the packages 30 with different thicknesses can be met by designing different bending depths.
In addition, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 may be bent in different directions through a rib-cutting bending process according to heat dissipation requirements and differences of heat dissipation paths, for example, the pins of each of the first electrical carrier 11 and the second electrical carrier 12 may be bent toward the first heat dissipation portion 111 or the second heat dissipation portion 121 through a rib-cutting bending process, so as to achieve the top or bottom exposure.
One embodiment of a semiconductor assembly 100 according to the present invention is described below with reference to the accompanying drawings.
As shown in fig. 1, 3-8, in the present embodiment, when the semiconductor assembly 100 is manufactured, the first electrical carrier 11, the second electrical carrier 12, the semiconductor device 20, the first connecting member 41, and the second connecting member 42 are provided first.
The first electrical carrier 11 and the second electrical carrier 12 are both metal frames, and the first electrical carrier 11 and the second electrical carrier 12 have the same structure, the first electrical carrier 11 and the second electrical carrier 12 both include a carrier body 131, a connection section 132 and an electrical connection section 133, the electrical connection section 133 and the carrier body 131 extend along the horizontal direction, the electrical connection section 133 is located on one side of the horizontal direction of the carrier body 131, the electrical connection section 133 and the carrier body 131 are arranged in a staggered manner in the up-down direction, the connection section 132 extends obliquely relative to the horizontal direction, and two ends of the connection section 132 are connected with the carrier body 131 and the electrical connection section 133 respectively. One side of the semiconductor device 20 has an active region on which a first electrode 21 and a second electrode 22 are disposed at an interval.
As shown in fig. 4, a heat conductive connection layer 51 with a certain thickness is printed or coated on the upper surface of the carrier body 131 of the first electrical carrier plate 11, and the side of the semiconductor device 20 facing away from the active area is attached on the heat conductive connection layer 51, so that the semiconductor device 20 is fixed on the carrier body 131 of the first electrical carrier plate 11 through the heat conductive connection layer 51.
As shown in fig. 5, a first connection layer 52 with a certain thickness is printed or coated on the first electrode 21 on the active region of the semiconductor device 20 and the electrical connection portion 133 of the first electrical carrier 11, then the first electrode 21 of the semiconductor device 20 is led out to the electrical connection portion 133 of the first electrical carrier 11 through the first connection member 41, one end of the first connection member 41 is connected to the first connection layer 52 on the first electrode 21, and the other end of the first connection member 41 is connected to the electrical connection portion 133 of the first electrical carrier 11, so as to electrically connect the first electrode 21 of the semiconductor device 20 and the electrical connection portion 133 of the first electrical carrier 11.
As shown in fig. 6, a second connection layer 53 is printed or coated on the second electrode 22 on the active region of the semiconductor device 20 in a certain thickness, one end of the second connection member 42 is attached on the second connection layer 53, the end face of one end of the second connection member 42 is connected to the second electrode 22, and then the second connection layer 53 is printed or coated on the end face of the other end of the second connection member 42.
As shown in fig. 7, the structure shown in fig. 6 is flip-chip mounted on the carrier body 131 of the second electrical carrier 12, and the other end of the second connecting element 42 is connected to the carrier body 131 of the second electrical carrier 12 through the second connecting layer 53, so as to obtain the pre-assembly structure shown in fig. 7.
As shown in fig. 8, the pre-package structure is packaged by a packaging process, such that a portion of the formed package 30 is filled between the first electrical carrier 11 and the second electrical carrier 12, and thus the package 30 can wrap the semiconductor device 20, the first connecting member 41, a connection between the first electrode 21 and one end of the first connecting member 41, a connection between the electrical connection portion 133 of the first electrical carrier 11 and the other end of the first connecting member 41, a connection between the second connecting member 42, the second electrode 22 and one end of the second connecting member 42, a connection between the electrical connection portion 133 of the second electrical carrier 12 and the other end of the second connecting member 42, and the other end of the electrical connection portion 133 of the first electrical carrier 11 and the other end of the electrical connection portion 133 of the second electrical carrier 12 all extend out of the package 30.
As shown in fig. 1, the electrical connection portion 133 of the first electrical carrier 11 and the electrical connection portion 133 of the second electrical carrier 12 are bent toward the side where the second heat sink portion 121 is located by using a rib cutting and bending process, and the electrical connection portion 133 of the first electrical carrier 11 and the electrical connection portion 133 of the second electrical carrier 12 are flush with the second heat sink portion 121, so as to obtain the semiconductor assembly 100 shown in fig. 1.
Another embodiment of a semiconductor assembly 100 according to the present invention is described below with reference to the accompanying drawings.
As shown in fig. 2 to 8, in the preparation of the semiconductor assembly 100, first, the first electrical carrier 11, the second electrical carrier 12, the semiconductor device 20, the first connecting member 41, and the second connecting member 42 are provided.
The first electrical carrier 11 and the second electrical carrier 12 are both metal frames, and the first electrical carrier 11 and the second electrical carrier 12 have the same structure, the first electrical carrier 11 and the second electrical carrier 12 both include a carrier body 131, a connection section 132 and an electrical connection section 133, the electrical connection section 133 and the carrier body 131 extend along the horizontal direction, the electrical connection section 133 is located on one side of the horizontal direction of the carrier body 131, the electrical connection section 133 and the carrier body 131 are arranged in a staggered manner in the up-down direction, the connection section 132 extends obliquely relative to the horizontal direction, and two ends of the connection section 132 are connected with the carrier body 131 and the electrical connection section 133 respectively. One side of the semiconductor device 20 has an active region on which a first electrode 21 and a second electrode 22 are provided in a spaced arrangement.
As shown in fig. 4, a heat conductive connection layer 51 with a certain thickness is printed or coated on the upper surface of the carrier body 131 of the first electrical carrier plate 11, and the side of the semiconductor device 20 facing away from the active area is attached on the heat conductive connection layer 51, so that the semiconductor device 20 is fixed on the carrier body 131 of the first electrical carrier plate 11 through the heat conductive connection layer 51.
As shown in fig. 5, a first connecting layer 52 with a certain thickness is printed or coated on the first electrode 21 on the active region of the semiconductor device 20 and the electrical connection portion 133 of the first electrical carrier plate 11, then the first electrode 21 of the semiconductor device 20 is led out to the electrical connection portion 133 of the first electrical carrier plate 11 through the first connecting member 41, one end of the first connecting member 41 is connected to the first connecting layer 52 on the first electrode 21, and the other end of the first connecting member 41 is connected to the electrical connection portion 133 of the first electrical carrier plate 11, thereby achieving the electrical connection between the first electrode 21 of the semiconductor device 20 and the electrical connection portion 133 of the first electrical carrier plate 11.
As shown in fig. 6, a second connection layer 53 is printed or coated on the second electrode 22 on the active region of the semiconductor device 20 in a certain thickness, one end of the second connection member 42 is attached on the second connection layer 53, the end face of one end of the second connection member 42 is connected to the second electrode 22, and then the second connection layer 53 is printed or coated on the end face of the other end of the second connection member 42.
As shown in fig. 7, the structure shown in fig. 6 is flip-chip mounted on the carrier body 131 of the second electrical carrier 12, and the other end of the second connecting element 42 is connected to the carrier body 131 of the second electrical carrier 12 through the second connecting layer 53, so as to obtain the pre-assembly structure shown in fig. 7.
As shown in fig. 8, the pre-assembly structure is packaged by a packaging process, such that a portion of the formed package 30 is filled between the first electrical carrier 11 and the second electrical carrier 12, and thus the package 30 can wrap the semiconductor device 20, the first connecting member 41, a connection between the first electrode 21 and one end of the first connecting member 41, a connection between the electrical connection portion 133 of the first electrical carrier 11 and the other end of the first connecting member 41, the second connecting member 42, a connection between the second electrode 22 and one end of the second connecting member 42, a connection between the electrical connection portion 133 of the second electrical carrier 12 and the other end of the second connecting member 42, and the other ends of the electrical connection portions 133 of the first electrical carrier 11 and the second electrical carrier 12 all extend out of the package 30.
As shown in fig. 2, the electrical connection portion 133 of the first electrical carrier 11 and the electrical connection portion 133 of the second electrical carrier 12 are bent toward the side where the first heat sink portion 111 is located by using a rib cutting and bending process, and the electrical connection portion 133 of the first electrical carrier 11 and the electrical connection portion 133 of the second electrical carrier 12 are flush with the first heat sink portion 111, so as to obtain the semiconductor assembly 100 shown in fig. 2.
Here, the first electrical carrier 11 and the second electrical carrier 12 have the same structure, and after packaging, the electrical connection portion 133 is bent and cut by using a trimming and bending process, so as to be separated into individual units.
After packaging, the electrical connection portion 133 of the first electrical carrier 11 exposes the package 30, the electrical connection portion 133 of the second electrical carrier 12 exposes the package 30, so as to facilitate connection with an external circuit, the surface of the carrier body 131 of the first electrical carrier 11, which faces away from the semiconductor device 20, exposes the package 30 to form the first heat dissipation portion 111, the surface of the carrier body 131 of the second electrical carrier 12, which faces away from the semiconductor device 20, exposes the package 30 to form the second heat dissipation portion 121, and heat dissipation is performed through the first heat dissipation portion 111 and the second heat dissipation portion 121, i.e., two heat dissipation paths are formed, so that the heat conduction area of the semiconductor device 20 is increased, the heat dissipation efficiency of the semiconductor device 20 is further improved, thereby the internal temperature of the semiconductor device 20 is limited not to exceed a certain value, and the use reliability of the semiconductor assembly 100 is improved.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Other constructions and operations of the semiconductor assembly 100 according to embodiments of the present invention are known to those of ordinary skill in the art and will not be described in detail herein.
In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims (28)

1. A semiconductor assembly, comprising:
the first electric carrier plate and the second electric carrier plate are respectively provided with an electric connection part connected with an external circuit;
the semiconductor device is arranged between the first electric carrier plate and the second electric carrier plate, a first electrode of the semiconductor device is electrically connected with the first electric carrier plate, and a second electrode of the semiconductor device is electrically connected with the second electric carrier plate;
the packaging body wraps the semiconductor device, the connection position of the first electrode and the first electric carrier plate and the connection position of the second electrode and the second electric carrier plate;
the first electrical carrier has a first heat dissipation portion, the second electrical carrier has a second heat dissipation portion, and at least a portion of the electrical connection portion, the first heat dissipation portion and the second heat dissipation portion are exposed out of the package body.
2. The semiconductor assembly of claim 1, wherein the semiconductor device is mounted on the first electrical carrier, the first heat sink portion forms a first heat sink surface, and a projection of the first electrode on a plane of the first heat sink surface at least partially coincides with the first heat sink surface.
3. The semiconductor assembly of claim 2, wherein a projection of the first electrode onto a plane of the first heat dissipation surface is located within the first heat dissipation surface.
4. The semiconductor assembly of claim 2, wherein the first heat dissipation surface is flush with an outer surface of the package body.
5. The semiconductor assembly of claim 2, wherein a projection of the second electrode onto the plane of the first heat dissipation surface at least partially coincides with the first heat dissipation surface.
6. The semiconductor assembly of claim 5, wherein a projection of the second electrode onto a plane of the first heat dissipation surface is located within the first heat dissipation surface.
7. The semiconductor assembly of claim 1, further comprising:
and one end of the first connecting piece is electrically connected with the first electrode, the other end of the first connecting piece is electrically connected with the first electric carrier plate, and the packaging body wraps the first connecting piece.
8. The semiconductor assembly of claim 7, wherein a first connection layer is disposed between the one end of the first connection and the first electrode, and between the other end of the first connection and the first electrical carrier.
9. The semiconductor assembly of claim 1, further comprising:
and one end of the second connecting piece is electrically connected with the second electrode, the other end of the second connecting piece is electrically connected with the second electric carrier plate, and the packaging body wraps the second connecting piece.
10. The semiconductor assembly of claim 9, wherein the second heat sink portion forms a second heat sink surface, and a projection of the other end of the second connection onto a plane of the second heat sink surface at least partially coincides with the second heat sink surface.
11. The semiconductor assembly of claim 10, wherein a projection of the other end of the second connection member onto a plane of the second heat dissipation surface is located within the second heat dissipation surface.
12. The semiconductor assembly of claim 10, wherein the second heat dissipation surface is flush with an outer surface of the package body.
13. The semiconductor assembly of claim 9, wherein the second connector forms a metal connection post.
14. The semiconductor assembly of claim 13, wherein the other end of the second connection member has a cross-sectional dimension greater than a cross-sectional dimension of a middle portion of the second connection member.
15. The semiconductor assembly of any one of claims 1-14, wherein each of the first and second electrical carrier plates comprises:
the carrier plate body of the first electrical carrier plate is opposite to the carrier plate body of the second electrical carrier plate and arranged at intervals, and the first heat dissipation part/the second heat dissipation part are positioned on the carrier plate body;
the semiconductor device is arranged between the two carrier plate bodies, the first electrode is connected with the electric connection part of the first electric carrier plate, and the second electrode is electrically connected with the carrier plate body of the second electric carrier plate.
16. The semiconductor assembly according to claim 15, wherein the package body is exposed at surfaces of two opposite sides of the carrier body to form the first heat sink portion and the second heat sink portion respectively.
17. The semiconductor assembly according to claim 15, wherein the electrical connection portions comprise pins, one end of each of the two pins is connected to the corresponding outer edge of the carrier body through a connection section, and the other end of each of the two pins extends out of the opposite sides of the package body.
18. The semiconductor package according to claim 17, wherein the two connecting sections extend obliquely away from each other and from the carrier body.
19. The semiconductor assembly of claim 17, wherein the pins of each of the first and second electrical carrier plates are bent toward the first or second heat sink portions by a bar-cutting bending process.
20. The semiconductor assembly of claim 19, wherein the pins of each of the first and second electrical carrier plates are flush with the first or second heat sink portion.
21. The semiconductor assembly of any one of claims 1-14, wherein the first electrical carrier plate and the second electrical carrier plate are metal frames.
22. A semiconductor device, comprising:
the semiconductor assembly of any one of claims 1-21;
and the radiator is arranged on the first radiating part or the second radiating part.
23. A method of fabricating a semiconductor assembly, comprising the steps of:
providing a semiconductor device, a first electric carrier plate and a second electric carrier plate;
mounting the semiconductor device on the first electric carrier plate, and electrically connecting a first electrode of the semiconductor device with the first electric carrier plate;
arranging the second electrical carrier plate on one side of the semiconductor device, which is opposite to the first electrical carrier plate, and electrically connecting a second electrode of the semiconductor device with the second electrical carrier plate to obtain a pre-assembly structure;
encapsulating the pre-assembly structure to form an encapsulation outside the pre-assembly structure;
the first electric carrier plate is provided with a first heat dissipation part, the second electric carrier plate is provided with a second heat dissipation part, the first electric carrier plate and the second electric carrier plate are respectively provided with an electric connection part, and the first heat dissipation part, the second heat dissipation part and the electric connection part are exposed out of the packaging body.
24. The method of manufacturing a semiconductor assembly according to claim 23, wherein electrically connecting the first electrode of the semiconductor device with the first electrical carrier comprises:
and connecting the first electrode with the electric connection part of the first electric carrier plate by adopting a first connecting piece.
25. The method of manufacturing a semiconductor assembly according to claim 24, wherein the first connection member forms a metal connection wire or a metal connection piece.
26. The method of manufacturing a semiconductor assembly according to claim 23, wherein electrically connecting the second electrode of the semiconductor device with the second electrical carrier comprises:
and connecting the second electrode and the second electric carrier plate by adopting a second connecting piece.
27. The method of claim 26, wherein the second connector forms a metal connection post.
28. The method of manufacturing a semiconductor assembly according to any one of claims 23 to 27, wherein the electrical connection comprises a pin,
after the pre-mounting structure is packaged by adopting a packaging process, the method further comprises the following steps:
and bending the pins of each of the first electric carrier plate and the second electric carrier plate towards the first heat dissipation part or the second heat dissipation part by adopting a rib cutting and bending process.
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CN1430268A (en) * 2001-12-27 2003-07-16 株式会社电装 Semiconductor power device
CN107039289A (en) * 2015-10-26 2017-08-11 英飞凌科技奥地利有限公司 The thermobond materials of heat with restriction, mechanically and electrically characteristic
CN211578743U (en) * 2019-12-10 2020-09-25 杰群电子科技（东莞）有限公司 Semiconductor packaging structure and electronic product
CN113632214A (en) * 2019-03-19 2021-11-09 株式会社电装 Semiconductor module and semiconductor device used for the same
CN217507316U (en) * 2022-03-07 2022-09-27 绍兴中芯集成电路制造股份有限公司 Chip packaging structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1430268A (en) * 2001-12-27 2003-07-16 株式会社电装 Semiconductor power device
CN107039289A (en) * 2015-10-26 2017-08-11 英飞凌科技奥地利有限公司 The thermobond materials of heat with restriction, mechanically and electrically characteristic
CN113632214A (en) * 2019-03-19 2021-11-09 株式会社电装 Semiconductor module and semiconductor device used for the same
CN211578743U (en) * 2019-12-10 2020-09-25 杰群电子科技（东莞）有限公司 Semiconductor packaging structure and electronic product
CN217507316U (en) * 2022-03-07 2022-09-27 绍兴中芯集成电路制造股份有限公司 Chip packaging structure

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