JP5009956B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve heat radiation without changing the entire size of a transfer mold-type semiconductor apparatus for electric power. <P>SOLUTION: The semiconductor apparatus includes: a metal block 4 provided with a first main surface 16 and a second main surface 18; recessed parts (20, 22, 24) formed on the first main surface 16; a semiconductor device 6 fixed to the metal block 4 inside the recessed part; a first insulation layer 38 which is in contact with the first main surface 16 and covers the first main surface 16; and a second insulation layer 38 which is in contact with the second main surface 18 and covers the second main surface 18. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that can be suitably used as a transfer mold type power semiconductor device.

  In a conventional transfer mold type power semiconductor device, a power semiconductor element is connected and fixed to one surface of a metal block by solder, and a signal terminal and a main electrode terminal are electrically connected to the power semiconductor element using a metal thin wire. These power semiconductor elements, main electrode terminals, and signal terminals are molded with resin together with the metal block surface on which these members are mounted.

  Some semiconductor devices have an insulating layer on the surface (rear surface) of the opposite metal block on which no power semiconductor element or the like is mounted. The insulating layer includes a resin layer in contact with the metal block surface and a metal layer disposed on the resin layer, and a radiator (radiation fin) is attached in contact with the metal layer. As another power semiconductor device, there is a device in which a heat radiator is provided directly on the rear surface of a metal block without an insulating layer interposed. According to the conventional power semiconductor device configured as described above, the heat generated in the power semiconductor element diffuses in the metal block, and passes through the insulating layer or directly from the metal block. ) And is dissipated.

  By the way, the heat transfer performance from the power semiconductor device to the radiator is proportional to the contact area (opposite area) between the metal block and the radiator and the temperature difference between the metal block and the radiator. Therefore, in order to improve the heat dissipation performance, a method of increasing the temperature difference and a method of increasing the contact area between the metal block and the radiator by enlarging them can be considered.

  However, if the outside air temperature (specifically, the ambient temperature of the radiator) is constant, increasing the temperature difference means increasing the operating temperature of the semiconductor element. This causes the problem of reduced reliability. On the other hand, increasing the contact area means increasing the size of the semiconductor device, which is against the demand for miniaturization. Even if the metal block is made larger, the temperature inside the metal block decreases as the distance from the power semiconductor element increases, so the heat dissipation efficiency does not always improve.

  The semiconductor devices described in Patent Literature 1, Patent Literature 2, Patent Literature 3 and Patent Literature 4 are all configured to dissipate heat from both sides by providing a heat radiation member on both sides of the semiconductor chip.

JP 2001-156225 A JP 2003-046036 A JP 2002-329804 A Japanese Patent Laid-Open No. 10-098140

  An object of the present invention is to improve heat dissipation in a semiconductor device, for example, a transfer mold type power semiconductor device, without changing the size of the entire device.

The present invention has been made to achieve the above object. A semiconductor device according to the present invention includes:
A metal block having a first main surface and a second main surface;
A groove formed in the first main surface;
A semiconductor element housed in the groove and fixed to the metal block at the bottom of the groove;
A main electrode terminal housed in the groove and electrically connected to the semiconductor element;
A signal terminal housed in the groove and electrically connected to the semiconductor element;
A first insulating layer in contact with the first main surface and covering the first main surface;
A second insulating layer in contact with the second main surface and covering the second main surface;
And a mold resin molded around the metal block so as to expose the first and second insulating layers and hold the signal terminal.

  By utilizing the present invention, in the power semiconductor device, when the size of the metal block and the heat generation amount of the semiconductor element are given, the operating temperature of the semiconductor element can be lowered. Conversely, if the operating temperature of the semiconductor element is fixed, a large current can be passed through the semiconductor element. Furthermore, if the current and the operating temperature of the semiconductor element are fixed, the entire apparatus can be downsized.

1 is a cross-sectional view [FIG. 1A], a longitudinal cross-sectional view [FIG. 1B], and a plan view [FIG. 1C] of a power semiconductor device according to a first embodiment of the present invention. The cross-sectional view [FIG. 1 (A)] is a cross-sectional view along the chain line AA of the plan view [FIG. 1 (C)]. The longitudinal sectional view [FIG. 1B] is a longitudinal sectional view taken along the chain line BB in the plan view [FIG. 1C]. In the plan view [FIG. 1C], some members are removed in order to clearly show the positional relationship between the members. It is a cross-sectional view of the power semiconductor device according to the first embodiment, in which heat radiating fins are joined. It is a top view of the modification of the power semiconductor device which concerns on Embodiment 1 of this invention. FIG. 4 is a transverse sectional view [FIG. 4A], a longitudinal sectional view [FIG. 4B], and a plan view [FIG. 4C] of a power semiconductor device according to a second embodiment of the present invention. The cross-sectional view [FIG. 4A] is a cross-sectional view along the chain line AA in the plan view [FIG. 4C]. The longitudinal sectional view [FIG. 4B] is a longitudinal sectional view along the chain line BB in the plan view [FIG. 4C]. In the plan view [FIG. 4C], some members are removed in order to clearly show the positional relationship between the members. It is the longitudinal cross-sectional view [FIG.5 (A)] and top view [FIG.5 (B)] of the power semiconductor device which concerns on Embodiment 3 of this invention. The longitudinal sectional view [FIG. 5A] is a longitudinal sectional view along the chain line AA in the plan view [FIG. 5B]. In the plan view [FIG. 5B], some members are removed in order to clearly show the positional relationship between the members. Cross-sectional view of the power semiconductor device according to the fourth embodiment of the present invention before resin sealing [FIG. 6A] and cross-sectional view after resin sealing [FIG. 6B] It is. FIG. 7 is a transverse sectional view [FIG. 7A], a longitudinal sectional view [FIG. 7B], and a plan view [FIG. 7C] of a power semiconductor device according to a fifth embodiment of the present invention. The cross-sectional view [FIG. 7A] is a cross-sectional view along the chain line AA in the plan view [FIG. 7C]. The longitudinal sectional view [FIG. 7B] is a longitudinal sectional view taken along the chain line BB in the plan view [FIG. 7C]. In the plan view [FIG. 7C], some members are removed to clearly show the positional relationship between the members. It is a cross-sectional view of the power semiconductor device which concerns on Embodiment 5 which joined the radiation fin. It is a top view of the modification of the power semiconductor device which concerns on Embodiment 5 of this invention. FIG. 10 is a plan view [FIG. 10A] and a longitudinal sectional view [FIG. 10B] of a power semiconductor device according to a sixth embodiment of the present invention. In the plan view [FIG. 10A], some members are removed in order to clearly show the positional relationship between the members. The longitudinal sectional view [FIG. 10B] is a longitudinal sectional view taken along the chain line BB in the plan view [FIG. 10A].

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, terms “upper”, “lower”, “right”, “left” indicating a specific direction and other terms including those terms (for example, “upper surface”, “lower surface”, “right side”) , “Left side”) is used as appropriate, but the use thereof is intended to facilitate understanding of the invention with reference to the drawings, and the technical scope of the invention is not limited by these terms. Accordingly, embodiments of the specific invention described below are upside down or rotated 90 ° in any direction (for example, clockwise direction or counterclockwise direction) as a matter of course. It is included.

[Embodiment 1]
1 is a cross-sectional view (FIG. 1A), a vertical cross-section [FIG. 1B] of a power semiconductor device for electric power according to Embodiment 1 of the present invention, and a plan view with a part thereof cut away (FIG. 1). (C)], and the power semiconductor device shown in the figure schematically shows the metal block 4, the power semiconductor element 6, the first main electrode terminal 8, the second main electrode terminal 10, the signal terminal 12, and the mold resin. (Coating member) 14.

  The metal block 4 is a quadrangular plate or lump made of a conductive metal material such as copper or aluminum, and has a first main surface 16 positioned upward in FIGS. 1A and 1B and a lower side in FIG. The second main surface 18 is located on the surface. Hereinafter, the first main surface is referred to as “metal block upper surface”, and the second main surface is referred to as “metal block lower surface”.

  The metal block upper surface 16 has a groove 19. As shown in FIG. 1C, the groove 19 crosses the substantially central portion of the metal block upper surface 16 in the vertical direction of the drawing. Further, as shown in FIGS. 1A and 1B, the groove 19 has a rectangular cross section. The groove 19 formed in this way has a plurality of accommodating portions corresponding to the plurality of members disposed in the groove 19. In the embodiment, the plurality of accommodating portions include a first recess 20 for connecting and fixing the power semiconductor element 6 to the metal block 4, a second recess 22 for arranging the signal terminal 12, The second recess 22 and the third recess 24 are arranged on both sides of the first recess 20. The third recess 24 is for arranging one main power supply terminal 8. As best shown in FIG. 1C, the metal block upper surface 16 is formed with a fourth recess 26 having a predetermined depth by cutting away a corner region appearing in the upper right of the drawing. The recess 26 is used as a housing portion for the second main electrode terminal 10.

  In the present embodiment, the bottom surfaces of the first recess 20, the second recess 22, and the third recess 24 are arranged at the same height by forming the groove 19 having a certain depth. However, the heights of the bottom surfaces of the recesses 20, 22, and 24 may be different. In addition, as shown in FIG. 1C, the second recess 22 is narrower than the first recess 20 and the third recess 24, but the width of each recess is there. What is necessary is just to determine suitably according to the magnitude | size of the member arrange | positioned in this. The width and depth of the fourth recess 26 may be appropriately determined according to the size of the second main electrode terminal 10 accommodated therein.

  An electrode terminal (not shown) provided on the back surface of the power semiconductor element 6 is joined to the bottom surface of the first recess 20 by the solder 28 with respect to the metal block 4 thus configured. A conductive adhesive may be used instead of solder. Note that, not only in this embodiment, but also in the description of other embodiments described below, a conductive adhesive can be used instead of a portion where solder is used.

  As shown in FIGS. 1B and 1C, the first main electrode terminal 8 is formed by bending one metal plate, and includes a first flat portion 30 on one end side and a first flat portion 30 on the other end side. A second flat portion 32 is provided, and both the flat portions 30 and 32 are connected by a connection portion (folded portion) 34, and the first flat portion 30 and the second flat portion 32 are parallel to each other. The first main electrode terminal 8 configured as described above is accommodated in the first recess 20 and the third recess 24, and the first flat portion is in a state where the second flat portion 32 protrudes outward. 30 is placed on the semiconductor element 6 and joined to the main electrode portion (not shown) of the semiconductor element 6 by the solder 28. In this state, as shown in FIG. 1 (A), the upper surface of the first flat portion 30 is located at the same height as the metal block upper surface 16, and such a height relationship (that is, flush) The groove 19 (the depth of the first recess 20) is determined so that

  The signal terminal 12 is made of a long and thin plate-like conductive metal plate, and is disposed so that the other end protrudes to the outside in a state where one end is positioned in the second recess 22, and is disposed in the second recess 22. One end side thus formed is electrically connected to a corresponding signal electrode (not shown) of the power semiconductor element 6 by a conductive wire 36 made of aluminum or the like. As shown in FIGS. 1A and 1B, the signal terminal 12 is embedded and held in the molding resin 14 when resin is molded into the metal block 4.

  The second main electrode terminal 10 is made of an elongated conductive metal plate. The second main electrode terminal 10 has one end and its vicinity joined to the fourth recess 26, and the other end is external. It is arranged to protrude. As shown in FIG. 1A, the upper surface of the second main electrode terminal 10 is at a position lower than the upper surface 16 of the metal block, and the depth of the fourth recess 26 is larger than the thickness of the second main electrode terminal. large. Therefore, when the metal block 4 is resin-molded, the upper surface of the second main electrode terminal is covered with the resin. Moreover, in joining to the bottom face of the 2nd main electrode arrangement | positioning recessed part 26 of the 2nd main electrode terminal 10, the technique of ultrasonic joining can be used other than a solder and a conductive adhesive material.

  First and second insulating layers 38 are disposed on the metal block upper surface 16 and the metal block lower surface 18. Specifically, the first insulating layer 38 covering the metal block upper surface 16 extends on the groove 19 (first to third recesses) and the fourth recess 26 along the metal block upper surface 16 to form a metal. The main electrode terminal portion and the signal terminal portion arranged on the block are also covered and protruded from the entire periphery of the metal block upper surface 16 by a predetermined length. Further, the upper surface portion of the first main electrode terminal 8 disposed at the same height as the metal block upper surface 16 is in contact with the insulating layer 38. The second insulating layer 38 covering the metal block lower surface 18 covers the entire metal block lower surface 18, and the peripheral edge protrudes from the metal block lower surface 18 by a predetermined length.

  The insulating layer 38 includes an electrically insulating resin layer 40 and a conductive metal layer 42. An epoxy resin is used as a material constituting the resin layer 40. The resin layer 40 is a ceramic with high thermal conductivity such as alumina, aluminum nitride, silicon nitride or boron nitride in order to give the resin layer 40 and the insulating layer 38 including the resin layer 40 higher thermal conductivity than the mold resin 14. One or more of the powders are mixed appropriately. Copper or aluminum is used as the material constituting the metal layer 42. In the insulating layer 38 having such a configuration, the resin layer 40 is disposed on the inner side (metal block side) and the metal layer 42 is disposed on the outer side.

  The mold resin 14 is made of an electrically insulating resin material, and is molded around the metal block 4 with the upper and lower insulating layers 38 exposed and the main electrode terminals 8 and 10 and the signal terminals 12 protruding. The At this time, the main electrode terminals 8 and 10 and the signal terminal 12 projecting to the outside are held by upper and lower molds (not shown).

  For the power semiconductor device 2 configured as described above, as shown in FIG. 2, radiators (radiating fins) 44 are set on the upper and lower insulating layers 38. Thereby, a part of the heat generated in the power semiconductor element 6 is absorbed by the metal block 4. The heat absorbed by the metal block 4 travels through the metal block 4 and is released into the atmosphere from the lower radiator 44 through the lower insulating layer 38 and is also released from the upper radiator 44 through the upper insulating layer 38 to the atmosphere. To be released. Further, the remaining part of the heat generated in the power semiconductor element 6 is released from the first radiator 44 from the first main electrode terminal 8 supported by the power semiconductor element 6 to the atmosphere through the upper insulating layer 38. . At this time, since the resin layer 40 constituting the upper and lower insulating layers 38 has high thermal conductivity, other members (metal block 4, main electrode terminals 8, 10 and metal layer forming the heat dissipation path) As in the case of 42), the heat is transferred satisfactorily, so that the heat flow generated in the power semiconductor element 6 is not hindered.

  Therefore, according to the power semiconductor device 2 according to the first embodiment, the heat generated in the power semiconductor element 6 can be efficiently released from the upper and lower heat radiating surfaces to the atmosphere. As a result, a highly reliable power semiconductor device is obtained. be able to. Further, a large current can flow through the power semiconductor element 6. Further, since the heat dissipation efficiency is high, the metal block 4 can be downsized, and further the semiconductor device can be downsized.

  In the power semiconductor device 2 described above, the first main electrode terminal 8 and the power semiconductor element 6 are connected by the solder 28, but they may be electrically connected by a wire similar to the wire 36. Further, the semiconductor device 2 according to the first embodiment shown in FIG. 1 has only one semiconductor element 6, but the present invention can also be applied to a semiconductor device provided with a plurality of semiconductor elements. In this case, the plurality of semiconductor elements may be respectively disposed in the plurality of recesses formed on the upper surface of the metal block, or may be respectively disposed in the plurality of recesses formed on the lower surface of the metal block. You may arrange | position in the recessed part formed in the lower surface, respectively.

  Further, as shown in FIG. 3, the plurality of metal blocks 4a and 4b are molded and integrated with one resin, and the main electrode terminal 8a drawn from one metal block 4a and the other metal block 4b are drawn. Another main electrode terminal 8b thus formed may be electrically connected by a connection terminal 46 disposed in the mold resin 14.

[Embodiment 2]
FIG. 4 is a cross-sectional view (FIG. 4A), a vertical cross-section [FIG. 4B] of a power semiconductor device for electric power according to Embodiment 2 of the present invention, and a plan view with a part thereof cut away (FIG. 4). (C)], and the power semiconductor device shown in the figure schematically shows the metal block 4, the power semiconductor element 6, the first main electrode terminal 8, the second main electrode terminal 10, the signal terminal 12, and the mold resin. (Coating member) 14.

  The power semiconductor device 2 according to the second embodiment is substantially the same as the power semiconductor device 2 according to the first embodiment. Accordingly, the same portions are denoted by the same reference numerals and description thereof is omitted.

  In the metal block 4 of the semiconductor device 2 according to the first embodiment described with reference to FIG. 1, the second recess 22 and the third recess 24 are disposed on both sides of the first recess 20. In the metal block 4 constituting the semiconductor device 2 according to the second embodiment shown in FIG. 4, the third recess 24 is formed so as to also serve as the second recess, and the second recess is formed alone. Absent. Further, the third recess 24 is made deeper than the first recess 20 (see FIG. 4B).

  The first main electrode terminal 8 includes a first flat portion 30, a second flat portion 32, and a continuous portion (bent portion) 34. As shown in FIG. The flat portion 30 and the second flat portion 32 are parallel to each other, and a continuous portion (bending portion) 34 is orthogonal to each flat portion and connects the two flat portions. The first main electrode terminal 8 is bent at the boundary between the first flat portion 30 and the continuous portion 34 and the boundary between the continuous portion 34 and the second flat portion 32, and the second flat portion 32 is the first flat portion 32. 1 flat part 30 is made lower.

  In the third recess 24, the first flat portion 30 of the first main electrode terminal 8, the signal terminal 12, and the conductive wire 36 are arranged vertically as shown in FIG. 4B. The first main electrode terminal 8 and the semiconductor element 6 are joined via the solder 28 as in the first embodiment. The second flat portion 32 of the first main electrode terminal 8 protrudes outwardly at a position different from that of the semiconductor device of the first embodiment. The upper surface portion of the first main electrode terminal 8 is in contact with the insulating layer 38 as in the first embodiment.

  The signal terminal 12 is disposed so that the other end side protrudes outward with one end side positioned in the third recess 24, and the one end side disposed in the third recess 24 is the power semiconductor element 6. A corresponding signal electrode (not shown) is connected by a conductive wire 36.

  By accommodating the first main power supply terminal 8 and the signal terminal 12 in the third recess 24, as shown in FIG. 4C, a recess (first recess) is formed from the first main surface 16 of the metal block 4. 20, the surface excluding the third recess 24) can be further enlarged. Accordingly, the amount of heat released from the first main surface 16 side can be further increased.

  In the power semiconductor device 2 according to the second embodiment shown in FIG. 4, the first flat portion 30 of the first main electrode terminal 8 is used for the wire bonding wiring work for connecting the signal terminal 12 to the power semiconductor element 6. It is preferable that a through hole is formed in the surface. In this way, it becomes easy to use a fixing jig or a wire bond tool.

[Embodiment 3]
FIG. 5 shows a longitudinal section [FIG. 5A] of a power semiconductor device for electric power according to Embodiment 3 of the present invention and a plane [FIG. 5B] with a part thereof cut away. The power semiconductor device generally includes a metal block 4, a power semiconductor element 6, a first main electrode terminal 8, a second main electrode terminal 10, a signal terminal 12, a control circuit board 48, and a mold resin (covering member) 14. It is composed of

  The power semiconductor device 2 according to the third embodiment is substantially the same as the power semiconductor device according to the first embodiment. Accordingly, the same portions are denoted by the same reference numerals and description thereof is omitted.

  In the power semiconductor device 2 shown in FIG. 5, a groove 19 is formed on one main surface of the metal block 4 as in the power semiconductor device according to the first embodiment. A control circuit board 48 is mounted on a part of the second recess 22 of the metal block 4.

  The back surface of the control circuit board 48 is bonded to the bottom surface of the second recess 22 of the metal block 4 by an adhesive (not shown). Conductive wires 36 are connected between the control circuit board 48 and the signal electrodes of the semiconductor element 6 and between the signal terminals 12 and the control circuit board 48. The material of the metal fine wire for connection is not limited to aluminum, but may be other conductive metal (for example, gold).

  By mounting the control circuit board 48, a control function is incorporated in the power semiconductor device 2, and the power semiconductor device 2 can be enhanced in function.

[Embodiment 4]
FIG. 6 is a cross section of a power semiconductor device for electric power according to Embodiment 4 of the present invention before resin sealing [FIG. 6A] and a cross section after resin sealing [FIG. 6 (B)], and the power semiconductor device shown in the figure schematically shows the metal block 4, the power semiconductor element 6, the first main electrode terminal 8, the second main electrode terminal 10, the signal terminal 12, and the mold. It is composed of a resin (covering member) 14.

  The power semiconductor device 2 according to the fourth embodiment is substantially the same as the power semiconductor device according to the first to third embodiments. Accordingly, the same portions are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 6A, in the semiconductor device 2 according to the fourth embodiment, the first main electrode terminal 8 is formed of two rolls of thin plates (thin metal plates) instead of the first flat portions. It is comprised by the 1st winding board part 50 formed by bending to 1 side. Part of the two rolls of the first winding plate portion 50 is joined to the semiconductor element 6 by the solder 28. The first winding plate part 50 may be composed of one roll.

  At the time when the first winding plate portion 50 is bonded to the semiconductor element 6, the flat upper surface portion of the first winding plate portion 50 is slightly more than the first main surface 16 of the metal block 4 (FIG. ), Only “h” is set to go upward. Thereafter, during sealing with the mold resin 14, the first winding plate portion 50 is pressed with a mold through the insulating layer 38. If it does so, the winding board part of the roll structure originally provided with a flexibility will bend suitably, and the flat outer surface (upper surface) part of the 1st winding board part 50 will contact, providing the insulating layer 38 with pressing force. Thereafter, when the mold resin 14 is cured, the flat portion of the first winding plate portion 50 is kept flush with the first main surface 16. Therefore, the flat portion of the first winding plate portion 50 is in contact with the insulating layer 38 with a pressing force and is held, whereby the high heat radiation characteristics can be made more stable.

[Embodiment 5]
7 is a cross-sectional view (FIG. 7A), a vertical cross-section [FIG. 7B] of a power semiconductor device for electric power according to Embodiment 5 of the present invention, and a plan view with a part thereof cut away (FIG. 7). (C)], and the power semiconductor device shown in the figure schematically shows the metal block 4, the power semiconductor element 6, the first main electrode terminal 8, the second main electrode terminal 10, the signal terminal 12, and the mold resin. (Coating member) 14.

  The power semiconductor device 2 according to the fifth embodiment is substantially the same as the power semiconductor device according to the first embodiment. Accordingly, the same portions are denoted by the same reference numerals, and the description thereof is omitted.

  Similarly to the first embodiment, the semiconductor device 2 according to the fifth embodiment also includes the groove 19 including the first recess 20, the second recess 22, and the third recess 24, and the fourth recess 26. And the power semiconductor element 6, the signal terminal 12, the first main electrode terminal 8, and the second main electrode terminal 10 are joined. Here, the first flat portion 30 of the first main electrode terminal 8 is joined to the main electrode portion (not shown) of the semiconductor element 6 as in the first embodiment. The upper surface is located at a lower height than the first main surface 16 of the metal block 4, and the depth of the groove 19 (first recess 20) is determined so as to obtain such a relationship. When the mold resin 14 is sealed in the first recess 20, the second recess 22, and the third recess 24, the upper surface of the first main electrode terminal 8 is completely covered with the mold resin 14.

  The power semiconductor device 2 according to the fifth embodiment is not provided with an insulating layer as shown in FIG. Therefore, as shown in FIG. 8, when attaching the radiator (radiating fin) 44, the layered insulating material 52 is sandwiched between the radiator 44 and the power semiconductor device 2. The first insulating material 52 disposed in contact with the metal block upper surface 16 protrudes from the entire periphery of the metal block upper surface 16 by a predetermined length. The peripheral edge of the second insulating material 52 disposed in contact with the metal block lower surface 18 protrudes from the metal block lower surface 18 by a predetermined length. The material constituting the insulating material 52 may be ceramic or silicon resin mixed with high thermal conductive ceramic powder as appropriate.

  The power semiconductor device according to the fifth embodiment corresponds to a standard product that does not include an insulating layer (see FIG. 1). Therefore, when the insulator 52 is sandwiched and the radiator (radiation fin) 44 is set, the power semiconductor device according to the fifth embodiment similarly realizes the effects provided by the power semiconductor device according to the first embodiment.

  The radiator (radiating fin) 44 is set up and down with respect to the power semiconductor device 2 as shown in FIG. Thereby, a part of the heat generated in the power semiconductor element 6 is absorbed by the metal block 4. The heat absorbed by the metal block 4 is transmitted through the metal block 4, is released into the atmosphere from the lower radiator 44 through the lower insulating material 52, and is released from the upper radiator 44 through the upper insulating material 52 into the atmosphere. To be released. At this time, since the upper and lower insulating materials 52 have high thermal conductivity, heat is satisfactorily the same as other members (metal block 4, main electrode terminals 8, 10 and metal layer 42) forming the heat dissipation path. Therefore, the flow of heat generated in the power semiconductor element 6 is not hindered.

  Therefore, according to the power semiconductor device 2 according to the fifth embodiment, heat generated in the power semiconductor element 6 can be efficiently released from the upper and lower heat dissipation surfaces to the atmosphere, and as a result, a highly reliable power semiconductor device is obtained. be able to. Further, a large current can flow through the power semiconductor element 6. Further, since the heat dissipation efficiency is high, the metal block 4 can be downsized, and further the semiconductor device can be downsized.

  Further, the semiconductor device 2 according to the fifth embodiment shown in FIG. 7 has only one semiconductor element 6, but the present invention can also be applied to a semiconductor device provided with a plurality of semiconductor elements. In this case, the plurality of semiconductor elements may be respectively disposed in the plurality of recesses formed on the upper surface of the metal block, or may be respectively disposed in the plurality of recesses formed on the lower surface of the metal block. You may arrange | position in the recessed part formed in the lower surface, respectively.

  Furthermore, as shown in FIG. 9, a plurality of metal blocks 4a and 4b are molded and integrated with one resin, and the main electrode terminal 10a drawn from one metal block 4a and another metal block 4b are drawn. Another main electrode terminal 8b thus formed may be electrically connected by a connection terminal 46 disposed in the mold resin 14.

[Embodiment 6]
FIG. 10 shows a plan view (FIG. 10A) and a longitudinal section [FIG. 10B] in which a part of a power semiconductor device for electric power according to a sixth embodiment of the present invention is cut away. The power semiconductor device generally includes a metal block 4, a power semiconductor element 6, a first main electrode terminal 8, a second main electrode terminal 10, a signal terminal 12, and a mold resin (covering member) 14.

  The power semiconductor device 2 according to the sixth embodiment is substantially the same as the power semiconductor device according to the fifth embodiment. Accordingly, the same portions are denoted by the same reference numerals and description thereof is omitted.

  In the metal block 4 of the semiconductor device 2 according to the fifth embodiment described with reference to FIG. 7, the second recess 22 and the third recess 24 are disposed on both sides of the first recess 20. In the metal block 4 included in the semiconductor device according to the sixth embodiment shown in FIG. 10, the third recess 24 is formed so as to also serve as the second recess, and the second recess is not formed alone. Further, the third recess 24 is made deeper than the first recess 20 (see FIG. 10B).

  The first main electrode terminal 8 includes a first flat portion 30, a second flat portion 32, and a continuous portion (bent portion) 34. As shown in FIG. The flat portion 30 and the second flat portion 32 are parallel to each other, and the continuous portion (bending portion) 34 is orthogonal to each flat portion and connects the two flat portions. The first main electrode terminal 8 is bent at the boundary between the first flat portion 30 and the continuous portion 34 and the boundary between the continuous portion 34 and the second flat portion 32, and the second flat portion 32 is the first flat portion 32. 1 flat part 30 is made lower.

  In the third recess 24, the first flat portion 30, the signal terminal 12, and the conductive wire 36 of the first main electrode terminal 8 are arranged vertically as shown in FIG. The first main electrode terminal 8 and the semiconductor element 6 are joined via the solder 28 as in the fifth embodiment. The second flat portion 32 of the first main electrode terminal 8 protrudes outwardly at a position different from that of the semiconductor device according to the fifth embodiment.

  The signal terminal 12 is disposed so that the other end side protrudes outward with one end side positioned in the third recess 24, and the one end side disposed in the third recess 24 is the power semiconductor element 6. A corresponding signal electrode (not shown) is connected by a conductive wire 36.

  By accommodating the first main electrode terminal 8 and the signal terminal 12 in the third recess 24, as shown in FIG. 10 (A), the recess (first step) from the first main surface 16 of the metal block 4 is performed. The surface excluding the recess 20 and the third recess 24) can be further enlarged. Accordingly, the amount of heat released from the first main surface 16 side can be further increased.

  In the semiconductor device according to the sixth embodiment shown in FIG. 10, the first flat portion 30 of the first main electrode terminal 8 is penetrated for the wire bonding wiring work for connecting the signal terminal 12 to the power semiconductor element 6. It is preferred that the holes be perforated. In this way, it becomes easy to use a fixing jig or a wire bond tool.

  2 power semiconductor device, 4 metal block, 6 power semiconductor element, 8 first main electrode terminal, 10 second main electrode terminal, 12 signal terminal, 14 mold resin, 19 groove, 20 first recess, 22 second Recess, 24 third recess, 26 fourth recess, 28 solder, 36 conductive wire, 38 insulating layer, 44 external radiator (radiating fin), 48 control circuit board, 50 first winding plate portion, 52 insulation Wood.

Claims (3)

A metal block having a first main surface and a second main surface;
A groove formed in the first main surface;
A semiconductor element housed in the groove and fixed to the metal block at the bottom of the groove;
A main electrode terminal housed in the groove and electrically connected to the semiconductor element;
A signal terminal housed in the groove and electrically connected to the semiconductor element;
A first insulating layer in contact with the first main surface and covering the first main surface;
A second insulating layer in contact with the second main surface and covering the second main surface;
A semiconductor device comprising: a mold resin molded around the metal block so as to expose the first and second insulating layers and hold the signal terminal.   The semiconductor device according to claim 1, wherein an upper surface of the main electrode terminal is located at the same height as the first main surface of the metal block.   3. The semiconductor device according to claim 1, wherein a heat radiator is bonded to cover the exposed surfaces of the first insulating layer and the second insulating layer.

Images