JP4901669B2 - Semiconductor package and semiconductor package manufacturing method - Google Patents

Semiconductor package and semiconductor package manufacturing method Download PDF

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JP4901669B2
JP4901669B2 JP2007250134A JP2007250134A JP4901669B2 JP 4901669 B2 JP4901669 B2 JP 4901669B2 JP 2007250134 A JP2007250134 A JP 2007250134A JP 2007250134 A JP2007250134 A JP 2007250134A JP 4901669 B2 JP4901669 B2 JP 4901669B2
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protrusion
opening
electrode plate
electrode
openings
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JP2009081308A (en
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心平 吉岡
尚威 渡邉
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Toshiba Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Connection Of Batteries Or Terminals (AREA)

Description

本発明は、半導体パッケージ及び半導体パッケージの製造方法に関し、特に、組立工程の簡易化及び容易化が可能なものに関する。   The present invention relates to a semiconductor package and a method for manufacturing the semiconductor package, and more particularly, to an apparatus capable of simplifying and facilitating an assembly process.

現在、電力用半導体素子として、IGBT(Insulated Gate Bipolar Transistor)、IEGT(Injection Enhanced Gate Transistor)、MOSFET(Metal Oxide Semiconductor Field Effect Transistor)等の半導体素子が多用されている。これら半導体素子は、板状に形成されており、半導体素子の表面に表面側電力端子及び制御端子を備えている。また、半導体素子の裏面には、裏面側電力端子を備えている。   Currently, semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), IEGTs (Injection Enhanced Gate Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as power semiconductor elements. These semiconductor elements are formed in a plate shape, and include a surface-side power terminal and a control terminal on the surface of the semiconductor element. Moreover, the back surface side power terminal is provided in the back surface of the semiconductor element.

なお、半導体素子がIGBT素子である場合には、表面側電力端子はエミッタ電極、裏面側電力端子はコレクタ電極、制御端子はゲート電極となる。   When the semiconductor element is an IGBT element, the front-side power terminal is an emitter electrode, the back-side power terminal is a collector electrode, and the control terminal is a gate electrode.

このような半導体素子を基板に実装して半導体パッケージとするには、半導体素子の裏面側電力端子は、半田接合により基板表面側の電極と接続される。また、半導体素子の表面側電力端子及び制御端子は、アルミニウムワイヤを用いたワイヤボンディングにより基板表面側の電極に接続される(例えば、特許文献1、2参照)。   In order to mount such a semiconductor element on a substrate to form a semiconductor package, the power terminal on the back surface side of the semiconductor element is connected to the electrode on the surface side of the substrate by solder bonding. Moreover, the surface side power terminal and the control terminal of the semiconductor element are connected to the electrode on the substrate surface side by wire bonding using an aluminum wire (see, for example, Patent Documents 1 and 2).

しかし、ワイヤボンディングを用いた場合、ワイヤを一本ずつボンディングするため、ボンディング工程に時間がかかり、製造コストが増大する虞がある。また、ワイヤがループするため、ワイヤ長が長くなり、配線インダクタンスが大きくなることや、外形状が大きくなる。さらに、半導体素子に振動が印加された場合に、ワイヤの断線や隣接するワイヤ等に接触することで短絡する虞等がある。   However, when wire bonding is used, since the wires are bonded one by one, the bonding process takes time, and the manufacturing cost may increase. Further, since the wire is looped, the wire length is increased, the wiring inductance is increased, and the outer shape is increased. Further, when vibration is applied to the semiconductor element, there is a possibility that the wire breaks or a short circuit occurs due to contact with an adjacent wire.

このため、半導体素子の表面側電力端子にワイヤボンディング法を用いずに、アルミニウム薄板等をボンディングする方法や、平板やリードを半田接合し電極として引き出す方法等も用いられている。   For this reason, a method of bonding an aluminum thin plate or the like without using a wire bonding method on the surface-side power terminal of the semiconductor element, a method of soldering a flat plate or a lead, and pulling it out as an electrode are used.

このような半導体パッケージを複数個備える半導体モジュールでは、複数の半導体パッケージが、放熱板であるベース基板上に一列に並べて設けられている。このとき、半導体パッケージの基板裏面がベース基板上に接合される。この半導体モジュールがインバータやコンバータ等の電力制御機器に搭載される。
特開2002−164485号公報 特開2003−110064号公報
In a semiconductor module including a plurality of such semiconductor packages, the plurality of semiconductor packages are arranged in a line on a base substrate which is a heat sink. At this time, the back surface of the substrate of the semiconductor package is bonded onto the base substrate. This semiconductor module is mounted on a power control device such as an inverter or a converter.
JP 2002-164485 A JP 2003-110064 A

上述した半導体モジュールでは、各半導体パッケージの片面だけがベース基板に接触しているため、放熱を充分行なうことができない。また、各半導体パッケージの基板裏面がベース基板上に接合されて設けられる構成となるため、ベース基板に対する半導体パッケージの設置面積が大きくなる。即ち、半導体モジュールの大型化を招く虞がある。   In the above-described semiconductor module, since only one surface of each semiconductor package is in contact with the base substrate, heat radiation cannot be sufficiently performed. In addition, since the back surface of each semiconductor package is bonded to the base substrate, the installation area of the semiconductor package with respect to the base substrate is increased. That is, there is a risk of increasing the size of the semiconductor module.

これらのことを防止するために、各半導体パッケージを一列に並べて設け、これら半導体パッケージを表裏面からバスバーなどの一対の導電部材により狭持し、ベース基板上に設けるようにしたものも知られている。   In order to prevent these problems, it is also known that each semiconductor package is arranged in a line, and these semiconductor packages are sandwiched between a pair of conductive members such as bus bars from the front and back surfaces and provided on a base substrate. Yes.

しかし、一対の導電部材は、熱伝導性を有しており、放熱部材としても機能するため、電流の供給に応じて熱膨張及び収縮する。加えて、導電部材のベース基板側の端部が固定端であり、その反対側の端部が自由端である。このため、導電部材の熱膨張及び収縮の挙動は自由端と固定端とで異なり、この挙動は自由端で比較的大きくなる。この挙動により、半導体パッケージには外力が加わり、半導体パッケージが破損してしまう虞もある。   However, the pair of conductive members has thermal conductivity and functions as a heat radiating member, so that it expands and contracts in response to current supply. In addition, the end of the conductive member on the base substrate side is a fixed end, and the opposite end is a free end. For this reason, the behavior of the thermal expansion and contraction of the conductive member differs between the free end and the fixed end, and this behavior becomes relatively large at the free end. Due to this behavior, an external force is applied to the semiconductor package, and the semiconductor package may be damaged.

また、半導体パッケージの小型化を図った場合、半導体素子の各端子の接続部分も小さくなる。そのため、半導体パッケージの製造方法において、十分な接合をすることができないことがあり、これが原因により、接合部が破損し易くなる虞もある。   Further, when the semiconductor package is miniaturized, the connection portion of each terminal of the semiconductor element is also reduced. Therefore, in the semiconductor package manufacturing method, sufficient bonding may not be possible, and this may cause damage to the bonded portion.

このような破損を防止するために、接合面積を広く取る方法や、一面だけを接合するのではなく、側面をも半田(又は接着剤等)で連続させて接合する方法を用いることで十分な接合とする方法もある。しかし、これらの方法では、半田の溶接箇所が多くなるとともに、半田の設置やスペーサ等の設置工程や溶接工程等、組立工程が増大する虞がある。このような組立工程の増大は、量産コストの増大にもつながる。   In order to prevent such breakage, it is sufficient to use a method in which the bonding area is widened or a method in which only the one surface is joined, but the side surfaces are continuously joined with solder (or adhesive, etc.). There is also a method of joining. However, in these methods, the number of solder welds increases, and the assembly process such as solder installation, spacer installation process, and welding process may increase. Such an increase in assembly process leads to an increase in mass production costs.

そこで本発明は、接合強度を減少することなく機械的に接合する場合であっても製造工程を低減することが可能な半導体パッケージ及び半導体パッケージの製造方法を提供することを目的としている。   Accordingly, an object of the present invention is to provide a semiconductor package and a method for manufacturing a semiconductor package that can reduce the manufacturing process even when mechanically bonding without reducing the bonding strength.

前記課題を解決し目的を達成するために、本発明の半導体パッケージ、及び、半導体パッケージの製造方法は次のように構成されている。   In order to solve the problems and achieve the object, a semiconductor package and a method for manufacturing the semiconductor package of the present invention are configured as follows.

本発明の一態様として、板状に形成され、第1の主面の中心部に設けられたゲート電極、第1の主面の前記ゲート電極の周囲に設けられたエミッタ電極、及び、第2の主面に設けられたコレクタ電極を有する半導体素子と、板状に形成され、前記第1の主面に対向する一方の面に設けられ前記エミッタ電極の少なくとも一部と当接する突起部、この突起部の中心に設けられた貫通孔、この貫通孔の内周面の一部であって他方の面側に設けられた台座部、前記突起部に設けられ前記貫通孔から前記突起部の外側面まで形成された連通路、及び、前記突起部の外側面に設けられた複数の開口部を有する第1電極板と、前記半導体素子と前記第1電極板との間に積層されるとともに狭持可能な板状に形成され、前記突起部が貫入される貫入口、その基端が前記貫入口の内周面に設けられ、その先端が前記貫通孔内部に位置するとともに前記台座部に保持され、前記連通路を介して延出する突出部、この突出部の先端に設けられ前記ゲート電極に電気的に接続される制御電極、及び、前記貫入口の内周面に複数設けられるとともに前記複数の開口部にそれぞれ係合し、その先端が前記突起部の外側面の内側に位置する係合部を有する配線基板と、板状に形成され、その一方の主面が前記コレクタ電極と電気的に接続される第2電極板と、を備えることを特徴とする。 As one aspect of the present invention, a gate electrode formed in a plate shape and provided at the center of the first main surface, an emitter electrode provided around the gate electrode on the first main surface, and a second A semiconductor element having a collector electrode provided on the main surface, and a protrusion formed in a plate shape and provided on one surface facing the first main surface and contacting at least a part of the emitter electrode, A through hole provided in the center of the protrusion, a pedestal part provided on the other surface side of the inner peripheral surface of the through hole, and provided outside the protrusion from the through hole provided in the protrusion. The communication path formed up to the side surface and the first electrode plate having a plurality of openings provided on the outer surface of the protrusion, and the semiconductor element and the first electrode plate are stacked and narrowed. A penetrating port that is formed in a plate shape that can be held and into which the protrusion is inserted, An end is provided on the inner peripheral surface of the penetrating inlet, and a tip thereof is located inside the through hole and is held by the pedestal portion, and extends through the communication path, provided at the tip of the projection. A plurality of control electrodes electrically connected to the gate electrode, and a plurality of control electrodes provided on the inner peripheral surface of the penetrating opening and engaging with the plurality of openings, respectively, and tips of the control electrodes are located inside the outer surface of the protrusion a wiring board having an engagement portion positioned, is formed in a plate shape, characterized in that it comprises a second electrode plate having a main surface of one of which is connected before SL to the collector electrode electrically, the.

本発明の一態様として、板状に形成され、第1の主面の中心側に設けられたゲート電極、第1の主面のゲート電極の周囲に設けられたエミッタ電極、及び、第2の主面に設けられたコレクタ電極を有する半導体素子と、板状に形成され、前記第1の主面に対向する対向面に前記エミッタ電極の少なくとも一部と当接する突起部、この突起部の中心に設けられた貫通孔、この貫通孔の内周面の一部であって前記対向面と相対する面側に設けられた台座部、前記突起部に設けられ前記貫通孔から前記突起部の外側面まで形成された連通路、前記突起部の外側面に設けられ、前記突起部の外側面に一部開口する少なくとも1つ有する開口部、及び、前記突起部の外側面であって前記対向面に設けられ突出する引掛部を有する第1電極板と、前記半導体素子と前記第1電極板との間に積層されるとともに狭持可能な板状に形成され、前記突起部及び前記引掛部が貫入される貫入口、その基端が前記貫入口のうち周面の一部に設けられ、その先端が前記貫通孔内部に位置するとともに前記台座部に保持され、前記連通路を介して延出する突出部、この突出部の先端に設けられ前記ゲート電極に電気的に接続される制御電極、及び、前記貫入口の内周面に設けられるとともに前記開口部に係合し、その先端が前記突起部の外側面の内側に位置する係合部を有する配線基板と、板状に形成され、その一方の主面が前記コレクタ電極と電気的に接続される第2電極板と、を備えることを特徴とする。 As one embodiment of the present invention, a gate electrode formed in the shape of a plate and provided on the center side of the first main surface, an emitter electrode provided around the gate electrode of the first main surface, and a second A semiconductor element having a collector electrode provided on a main surface; a protrusion formed in a plate shape and in contact with at least a portion of the emitter electrode on an opposing surface facing the first main surface; and a center of the protrusion A through hole provided in the base, a pedestal part provided on a side of the inner peripheral surface of the through hole opposite to the opposing surface, and provided on the protrusion and outside the protrusion from the through hole. A communication path formed up to a side surface; an opening provided on an outer surface of the protrusion; and at least one opening partially opening on the outer surface of the protrusion; and an outer surface of the protrusion and the opposing surface A first electrode plate having a hooking portion provided on and projecting, and the semiconductor While being laminated between the the element first electrode plate is formed sandwiched possible plate, the protrusions and the penetration opening the hook portion is penetrated, the peripheral surface of the base end thereof the penetration opening A protrusion that is located inside the through-hole and that is held by the pedestal portion and extends through the communication path, and is provided at the tip of the protrusion and is electrically connected to the gate electrode. Connected to the control electrode, and a wiring board that is provided on the inner peripheral surface of the penetrating opening and engages with the opening, and has an engaging portion positioned on the inner side of the outer surface of the protrusion. When formed in a plate shape, characterized in that it comprises a second electrode plate main surface of one of which is connected before SL to the collector electrode electrically, the.

本発明の一態様として、方形に形成され、一方の主面に設けられた突起部を有し、この突起部の側面に複数の開口部を有する第1電極板と、前記突起部が貫入される貫入口、及び、この貫入口の内側面に設けられ前記複数の開口部と係合し、その先端が前記突起部の外側面の内側に位置する係合部を有する配線基板とを、前記開口部及び前記係合部が係合可能な位置に配置させる工程と、前記配線基板の前記複数の係合部を前記第1電極板の前記複数の開口部にそれぞれ係合させることで、前記配線基板と前記第1電極板とを組み付ける工程と、組み付けた前記配線基板及び前記第1電極板と電極を有する半導体素子と導通部材で接合する工程と、を備えることを特徴とする。   As one aspect of the present invention, a first electrode plate that is formed in a square shape and has a protrusion provided on one main surface, and a plurality of openings on the side surface of the protrusion, and the protrusion penetrates. And a wiring board having an engaging portion that is provided on an inner surface of the penetrating hole and that engages with the plurality of openings and has a distal end positioned on the inner side of the outer surface of the protrusion. The step of disposing the opening and the engagement portion at positions where the engagement portion can be engaged, and engaging the plurality of engagement portions of the wiring board with the plurality of openings of the first electrode plate, respectively. A step of assembling the wiring substrate and the first electrode plate; and a step of joining the assembled wiring substrate and the first electrode plate and a semiconductor element having an electrode with a conductive member.

本発明の一態様として、方形に形成され、一方の主面に設けられた突起部を有し、この突起部の少なくとも1つの側面に複数の開口部、及び、この開口部が設けられた前記突起部の側面と相対する側面に設けられた引掛部を有する第1電極板と、前記突起部及び前記引掛部が貫入される貫入口、及び、この貫入口の内側面の前記複数の開口部と係合し、その先端が前記突起部の外側面の内側に位置する係合部を有する配線基板とを、前記開口部及び前記係合部が係合可能な位置に配置させる工程と、前記突起部の側面を前記貫入口の内側面で覆うとともに、前記複数の開口部と前記複数の係合部とをそれぞれ対向させる工程と、対向する前記複数の開口部と前記複数の係合部とを、前記開口部と前記係合部とが係合する方向に移動させることで、前記開口部及び前記係合部を係合させる工程と、前記引掛部及び前記突起部の側面を前記貫入口の内側面で覆うことで、前記配線基板と前記第1電極板とを組み付ける工程と、組み付けた前記配線基板及び前記第1電極板と電極を有する半導体素子と導通部材で接合する工程と、を備えることを特徴とする。   As one aspect of the present invention, the projection is formed in a square shape and provided on one main surface, and a plurality of openings are provided on at least one side surface of the projection, and the openings are provided. A first electrode plate having a hooking portion provided on a side surface opposite to the side surface of the protrusion, a penetrating opening through which the protrusion and the hooking part penetrate, and the plurality of openings on the inner side surface of the penetrating hole; A wiring board having an engaging portion whose front end is positioned on the inner side of the outer surface of the protruding portion, at a position where the opening and the engaging portion can be engaged, and A step of covering a side surface of the projecting portion with an inner side surface of the penetrating opening, and causing the plurality of openings and the plurality of engaging portions to face each other; and the plurality of opening portions and the plurality of engaging portions facing each other. Is moved in a direction in which the opening and the engagement portion engage with each other. A step of engaging the opening and the engaging portion, and a step of assembling the wiring board and the first electrode plate by covering side surfaces of the hooking portion and the protruding portion with an inner side surface of the penetrating opening. And a step of joining the semiconductor substrate having the wiring board and the first electrode plate and electrodes assembled together with a conductive member.

本発明の一態様として、方形に形成され、一方の主面に設けられた突起部を有し、この突起部の少なくとも1つの側面に複数の開口部、この開口部が設けられた前記突起部の側面と相対する側面に設けられた引掛部、及び、前記引掛部の側面に設けられた開口部を有する第1電極板と、前記突起部及び前記引掛部が貫入される貫入口、及び、この貫入口の内側面の前記複数の開口部にそれぞれ係合し、その先端が前記突起部及び前記引掛部の外側面の内側に位置する係合部を有する配線基板とを、前記開口部及び前記係合部が係合可能な位置に配置させる工程と、前記突起部の側面を前記貫入口の内側面で覆うとともに、前記複数の開口部と前記複数の係合部とをそれぞれ対向させる工程と、対向する前記突起部に設けられた複数の開口部と前記複数の係合部とを、前記突起部の開口部と前記係合部とが係合する方向に移動させることで、前記突起部の開口部及び前記係合部をそれぞれ係合させる工程と、前記引掛部及び前記突起部の側面を前記貫入口の内側面で覆うとともに、前記係合部を前記引掛部の開口部に係合させることで、前記配線基板と前記第1電極板とを組み付ける工程と、組み付けた前記配線基板及び前記第1電極板と電極を有する半導体素子と導通部材で接合する工程と、を備えることを特徴とする。   As one aspect of the present invention, the protrusion has a protrusion formed on one main surface and having a plurality of openings on at least one side surface of the protrusion, and the protrusion having the openings. A hook portion provided on a side surface of the hook portion, a first electrode plate having an opening provided on a side surface of the hook portion, a penetrating opening through which the protrusion and the hook portion are inserted, and A wiring board that engages with each of the plurality of openings on the inner side surface of the penetrating opening and has an engaging portion whose tip is located inside the outer side surface of the protrusion and the hooking portion. A step of disposing the engaging portion at a position where the engaging portion can be engaged; and a step of covering the side surface of the protrusion with the inner side surface of the penetrating opening and causing the plurality of openings and the plurality of engaging portions to face each other. And a plurality of openings provided in the opposing protrusions Moving the plurality of engaging portions in a direction in which the opening of the protruding portion and the engaging portion engage with each other, thereby engaging the opening of the protruding portion and the engaging portion, respectively. The side surfaces of the hooking portion and the protrusion portion are covered with the inner side surface of the penetrating entrance, and the engaging portion is engaged with the opening portion of the hooking portion, whereby the wiring board and the first electrode plate are connected. A step of assembling, and a step of joining the semiconductor substrate having the assembled wiring board, the first electrode plate, and the electrode with a conductive member.

本発明によれば、接合強度を減少することなく機械的に接合する場合であっても製造工程を低減することが可能となる。   According to the present invention, it is possible to reduce the manufacturing process even when mechanically joining without reducing the joining strength.

本発明の第1の実施の形態に係る半導体パッケージ1を図1〜3を用いて説明する。図1は本発明の第1の実施の形態に係る半導体パッケージ1を示す斜視図、図2は同半導体パッケージ1の構成を示す分解斜視図、図3は同半導体パッケージ1の構成を示す分解斜視図である。なお、図1〜3中、Fは配線を示す。   A semiconductor package 1 according to a first embodiment of the present invention will be described with reference to FIGS. 1 is a perspective view showing a semiconductor package 1 according to a first embodiment of the present invention, FIG. 2 is an exploded perspective view showing the configuration of the semiconductor package 1, and FIG. 3 is an exploded perspective view showing the configuration of the semiconductor package 1. FIG. In FIGS. 1 to 3, F represents a wiring.

図1〜3に示すように、半導体パッケージ1は、第1主面11及び第2主面12を有する方形板状に形成された半導体素子10と、第1主面11側に設けられた第1電極板20と、第2主面12側に設けられた第2電極板30と、半導体素子10及び第1電極板20の間に設けられた配線基板40とを積層して構成されている。   As shown in FIGS. 1 to 3, the semiconductor package 1 includes a semiconductor element 10 formed in a rectangular plate shape having a first main surface 11 and a second main surface 12, and a first main surface 11 provided on the first main surface 11 side. The first electrode plate 20, the second electrode plate 30 provided on the second main surface 12 side, and the wiring substrate 40 provided between the semiconductor element 10 and the first electrode plate 20 are laminated. .

半導体素子10は、方形板状の小片の半導体チップ、例えばIGBT素子により形成されている。また、半導体素子10の外周縁は、第1電極板20、第2電極板30及び配線基板40それぞれの外周縁よりも内側に位置する形状に形成されている。   The semiconductor element 10 is formed of a rectangular plate-shaped small semiconductor chip, for example, an IGBT element. In addition, the outer peripheral edge of the semiconductor element 10 is formed in a shape that is located inside the outer peripheral edges of the first electrode plate 20, the second electrode plate 30, and the wiring substrate 40.

半導体素子10の第1主面11は、外周縁側から中心側周辺までの範囲に形成されたエミッタ電極13と、エミッタ電極13の内側(第1主面11の中心側)に設けられたゲート電極14とを備えている。このエミッタ電極13の内周縁であって、ゲート電極14の外周縁には、エミッタ電極13とゲート電極14との間での半田流れ(短絡)が防止可能に形成された半田抵抗膜15が印刷されている。また、エミッタ電極13の外周部には半田抵抗膜16が形成されている。また、第2主面12は、コレクタ電極17が形成されている(図3参照)。   The first main surface 11 of the semiconductor element 10 includes an emitter electrode 13 formed in a range from the outer peripheral edge side to the center side periphery, and a gate electrode provided inside the emitter electrode 13 (center side of the first main surface 11). 14. A solder resistance film 15 formed so as to prevent solder flow (short circuit) between the emitter electrode 13 and the gate electrode 14 is printed on the inner peripheral edge of the emitter electrode 13 and the outer peripheral edge of the gate electrode 14. Has been. A solder resistance film 16 is formed on the outer periphery of the emitter electrode 13. Moreover, the collector electrode 17 is formed in the 2nd main surface 12 (refer FIG. 3).

第1電極板20は、銅等の導電性材料により方形板状に形成された第1基板本体21と、この第1基板本体21の一方の面21aに設けられ、エミッタ電極13に接合される接合面22aを有する突起部22とを備えている。   The first electrode plate 20 is provided on a first substrate body 21 formed in a rectangular plate shape with a conductive material such as copper, and one surface 21 a of the first substrate body 21, and is joined to the emitter electrode 13. And a protrusion 22 having a joint surface 22a.

突起部22は、略中央位置に略方形の貫通孔23と、この貫通孔23内周部であって他方の面21b側に設けられた台座部24と、突起部22に設けられ貫通孔23から突起部22の外側面まで形成された連通路25と、この突起部22の側面に設けられた複数の開口部26と、を有している。なお、突起部22は、貫通孔23及び連通路25により、そのエミッタ電極13に接合する接合面22aは凹部形状に形成されることとなる。また、台座部24は、貫通孔23の、連通路25が設けられた内面と対向する内面に設けられている。   The protruding portion 22 has a substantially rectangular through hole 23 at a substantially central position, a pedestal portion 24 provided on the inner surface of the through hole 23 on the other surface 21 b side, and a through hole 23 provided on the protruding portion 22. To the outer surface of the protrusion 22 and a plurality of openings 26 provided on the side of the protrusion 22. Note that the protrusion 22 has a through hole 23 and a communication path 25, and the bonding surface 22 a bonded to the emitter electrode 13 is formed in a concave shape. The pedestal portion 24 is provided on the inner surface of the through hole 23 that faces the inner surface where the communication path 25 is provided.

開口部26は、例えば、第1基板本体21であって、第1基板本体21の他方の面21b側から円筒状に穴部27が例えば型による押圧加工等により成形されることで形成されている。なお、この穴部27は、突起部22を貫通しないように形成されているとともに、穴部27の中心が、突起部22の側面に位置するように設けられている。さらに、開口部26は、例えば突起部22の連通路25が設けられた外側面及び貫通孔23を介して対向する外側面にそれぞれ複数(本実施例ではそれぞれ2つ)設けられている。   The opening 26 is, for example, the first substrate body 21 and is formed by forming a hole 27 in a cylindrical shape from the other surface 21b side of the first substrate body 21 by, for example, pressing with a mold or the like. Yes. The hole 27 is formed so as not to penetrate the protrusion 22, and is provided so that the center of the hole 27 is located on the side surface of the protrusion 22. Further, a plurality of openings 26 are provided on the outer surface where the communication passage 25 of the protrusion 22 is provided and the outer surface facing each other through the through-hole 23 (two in the present embodiment).

第2電極板30は、銅等の導電性材料により方形板状に形成された第2基板本体31により形成されている。この第2基板本体31には、第2主面12に対向するとともに、コレクタ電極17に接続される接続面32と、この接続面32の外周側に印刷され、半田流れ(短絡)を防止可能に形成された半田抵抗膜33と、を備えている。   The second electrode plate 30 is formed by a second substrate body 31 formed in a square plate shape with a conductive material such as copper. The second substrate body 31 is printed on the connection surface 32 facing the second main surface 12 and connected to the collector electrode 17 and on the outer peripheral side of the connection surface 32 to prevent solder flow (short circuit). And a solder resistance film 33 formed thereon.

配線基板40は、ガラスエポキシ樹脂やポリイミド樹脂等により略方形板状に形成された絶縁基板41により形成されている。絶縁基板41は、この絶縁基板41の外周の一部に設けられた凸部42と、突起部22が貫入される貫入口43と、凸部42と連続するように貫入口43の内周面から突出して設けられた突出部44と、貫入口43の内周面であって開口部26に対応する位置に設けられた複数の係合部45と、を備えている。   The wiring substrate 40 is formed of an insulating substrate 41 formed in a substantially square plate shape using glass epoxy resin, polyimide resin, or the like. The insulating substrate 41 includes a convex portion 42 provided on a part of the outer periphery of the insulating substrate 41, an inlet 43 through which the protruding portion 22 penetrates, and an inner peripheral surface of the inlet 43 so as to be continuous with the convex portion 42. And a plurality of engaging portions 45 provided at positions corresponding to the opening 26 on the inner peripheral surface of the through-hole 43.

また、絶縁基板41は、凸部42が設けられている外周部以外であって、貫入口43の係合部45を有する内周面に対応する外周に切欠部46を有している。
凸部42は、凸部42の半導体素子10側に外部接続端子47を有している。
Further, the insulating substrate 41 has a notch 46 on the outer periphery corresponding to the inner peripheral surface having the engaging portion 45 of the penetrating port 43 other than the outer peripheral portion where the convex portion 42 is provided.
The convex part 42 has an external connection terminal 47 on the semiconductor element 10 side of the convex part 42.

突出部44には、その先端側に円形状の先端部48を有しており、この先端部48は、第1電極板20と配線基板40とを係合させたときに、突起部22に設けられた貫通孔23内に位置する形状に形成されている。また、先端部48の半導体素子10に対向する面には、ゲート電極14と半田等の導通部材(以下「半田部材」)Bにより電気的に接合される制御電極49が設けられている。なお、この制御電極49は、外部接続端子47と絶縁基板41上に例えば印刷により形成された配線Fにより接続されている。   The protrusion 44 has a circular tip 48 on the tip side, and the tip 48 is formed on the protrusion 22 when the first electrode plate 20 and the wiring board 40 are engaged. It is formed in a shape located in the provided through hole 23. A control electrode 49 that is electrically joined to the gate electrode 14 by a conductive member such as solder (hereinafter referred to as “solder member”) B is provided on the surface of the tip 48 that faces the semiconductor element 10. The control electrode 49 is connected to the external connection terminal 47 and a wiring F formed on the insulating substrate 41 by printing, for example.

係合部45は、半円状であって、弾性変形可能に形成されており、係合部45が弾性変形することにより開口部26に係合可能に形成されている。また、係合部45の少なくとも先端は、突起部22の外側面よりも内側に位置する形状に形成されている。   The engaging portion 45 is semicircular and is formed so as to be elastically deformable. The engaging portion 45 is formed so as to be engageable with the opening 26 by elastically deforming. Further, at least the tip of the engaging portion 45 is formed in a shape that is located inside the outer surface of the protrusion 22.

なお、第1電極板20、第2電極板30及び配線基板40の絶縁基板41は、例えばプレス加工により一つの金型(順送型)で成型される。   The first electrode plate 20, the second electrode plate 30, and the insulating substrate 41 of the wiring substrate 40 are molded with a single mold (sequential feeding mold) by, for example, pressing.

次に、このような半導体パッケージ1の製造工程を図4〜6を用いて説明する。
なお、図4は同半導体パッケージ1に用いられる第1電極板20及び配線基板40の組立の一例を示す斜視図、図5は同半導体パッケージ1に用いられる第1電極板20及び配線基板40の組立の一例を示す斜視図、図6は同半導体パッケージ1の構成を示す断面図である。
Next, the manufacturing process of such a semiconductor package 1 will be described with reference to FIGS.
4 is a perspective view showing an example of the assembly of the first electrode plate 20 and the wiring board 40 used in the semiconductor package 1, and FIG. 5 is a diagram of the first electrode plate 20 and the wiring board 40 used in the semiconductor package 1. FIG. 6 is a cross-sectional view showing a configuration of the semiconductor package 1.

先ず、図4、5に示すように、第1電極板20と配線基板40との組立を行なう。配線基板40の制御電極49に半田部材Bを溶着させる。なお、ここでは、半田部材Bを溶着させずに、接着や配置により半田部材Bを設けても良い。また、現段階で半田部材Bを設けるのではなく、後述する制御電極49及びゲート電極14との接合時に設けるようにしても良い。   First, as shown in FIGS. 4 and 5, the first electrode plate 20 and the wiring substrate 40 are assembled. The solder member B is welded to the control electrode 49 of the wiring board 40. Here, the solder member B may be provided by adhesion or arrangement without welding the solder member B. Further, instead of providing the solder member B at the present stage, it may be provided at the time of joining a control electrode 49 and a gate electrode 14 described later.

次に、第1電極板20と配線基板40との向きを、連通路25及び貫通孔23と、突出部44及び先端部48とがそれぞれ対応する位置となるように配置させる。この状態で、例えば連通路25が設けられている側(一方)の開口部26と、突出部44が設けられている側(一方)の係合部45とを係合させる。この係合により、図4に示すように、係合させていない(他方の)開口部26の上方(突起部22の接合面22a)に他方の係合部45が積載されることとなる。   Next, the first electrode plate 20 and the wiring substrate 40 are arranged so that the communication passage 25 and the through hole 23, the protruding portion 44, and the distal end portion 48 are in corresponding positions. In this state, for example, the opening 26 on the side where the communication path 25 is provided (one side) and the engaging portion 45 on the side where the protrusion 44 is provided (one side) are engaged. As a result of this engagement, as shown in FIG. 4, the other engagement portion 45 is stacked above the other (other) opening 26 (joining surface 22 a of the protrusion 22).

この状態で、他方の係合部45周辺を押圧、又は、他方の係合部45の周辺(配線基板40)を第1基板本体21に係合部45が対向するように湾曲させる。これにより、他方の係合部45又は係合部45の周辺が弾性変形し、他方の係合部45は、対応する他方の開口部26にそれぞれが係合することとなる。なお、全ての係合部45周辺に同時に押圧を加えることで、弾性変形させ、開口部26に係合部45を係合させてもよい。   In this state, the periphery of the other engaging portion 45 is pressed, or the periphery (wiring board 40) of the other engaging portion 45 is bent so that the engaging portion 45 faces the first substrate body 21. Thereby, the other engaging part 45 or the periphery of the engaging part 45 is elastically deformed, and the other engaging part 45 is engaged with the corresponding other opening part 26, respectively. Note that it is also possible to cause the engaging portion 45 to engage with the opening 26 by elastically deforming by simultaneously pressing the periphery of all the engaging portions 45.

係合部45周辺に押圧を印加すると、第1基板本体21の一方の面21aに略平行であって近接方向に配線基板40が移動しようとする。しかし、係合部45の第1基板本体21に対向する面は、突起部22の接合面22aに当接している。このため、係合部45は接合面22aに押圧される状態となり、この押圧(干渉)により係合部45は湾曲する。   When pressure is applied to the periphery of the engaging portion 45, the wiring board 40 tends to move in the proximity direction substantially parallel to the one surface 21 a of the first board body 21. However, the surface of the engaging portion 45 that faces the first substrate body 21 is in contact with the joint surface 22 a of the protrusion 22. For this reason, the engaging part 45 will be in the state pressed by the joint surface 22a, and the engaging part 45 will curve by this press (interference).

この状態でさらに配線基板40が一方の面21aに近接する方向に押圧されると、湾曲した状態で係合部45は突起部22の側面を摺動する。この摺動は、係合部45が開口部26に位置するまで行なわれる、即ち、一方の面21aに配線基板40が略当接するまで配線基板40が移動する。配線基板40が一方の面21aに当接すると、係合部45は開口部26に位置するため、係合部45は開口部26内部に進入することで係合部45は干渉されなくなり、係合部45は形状が復元される。このようにして係合部45が開口部26に係合することとなる。   In this state, when the wiring board 40 is further pressed in the direction approaching the one surface 21a, the engaging portion 45 slides on the side surface of the protruding portion 22 in a curved state. This sliding is performed until the engaging portion 45 is positioned at the opening 26, that is, the wiring substrate 40 moves until the wiring substrate 40 substantially contacts the one surface 21a. When the wiring board 40 comes into contact with the one surface 21a, the engaging portion 45 is positioned in the opening portion 26. Therefore, when the engaging portion 45 enters the inside of the opening portion 26, the engaging portion 45 is not interfered. The shape of the joint portion 45 is restored. In this way, the engaging portion 45 is engaged with the opening portion 26.

なお、係合部45の周辺を第1基板本体21に係合部45が対向するように湾曲させた場合には、係合部45が突起部22に干渉せずに、係合部45が一方の面21aに当接する。この状態で、係合部45の周辺の湾曲を解除すると、係合部45は一方の面21aに対して略平行に復元され、復元された係合部45が開口部26内に進入することで係合されることとなる。   When the periphery of the engaging portion 45 is curved so that the engaging portion 45 faces the first substrate body 21, the engaging portion 45 does not interfere with the protruding portion 22 and the engaging portion 45 It abuts against one surface 21a. In this state, when the curve around the engaging portion 45 is released, the engaging portion 45 is restored substantially parallel to the one surface 21a, and the restored engaging portion 45 enters the opening 26. Will be engaged.

このように、係合部45と開口部26とが係合すると、係合部45の外面は開口部26に覆われる。このため、第1電極板20と配線基板40とが離間する方向に移動しようとした際には、各係合部45外面と各開口部26内面、及び、突起部22外側面と貫入口43内側面とのすくなくともいずれかで一箇所で互いに干渉する。この干渉により、例えば接合面22aに対して水平方向には各側面により、接合面22a対して直交方向には係合部45と開口部26とによりそれぞれ係止されることとなり、配線基板40が第1電極板20から離脱することがない。   Thus, when the engaging part 45 and the opening part 26 are engaged, the outer surface of the engaging part 45 is covered with the opening part 26. Therefore, when the first electrode plate 20 and the wiring board 40 are about to move away from each other, the outer surfaces of the engaging portions 45 and the inner surfaces of the openings 26, the outer surfaces of the protrusions 22, and the entrance 43. Interfere with each other at one location at least at any point with the inner surface. Due to this interference, for example, the horizontal direction with respect to the bonding surface 22a is locked by the side surfaces, and the engagement portion 45 and the opening portion 26 are locked in the direction orthogonal to the bonding surface 22a. There is no separation from the first electrode plate 20.

このように、第1電極板20と配線基板40とを係合(組み付け)後、図6に示すように、突起部22の接合面22a及び側面に半田部材Bを配置させる。この半田部材Bは、例えば突起部22の接合面22a及び側面を覆うような皿状の部材形状であっても、ペースト状であってもよい。   Thus, after engaging (assembling) the first electrode plate 20 and the wiring board 40, the solder member B is disposed on the joint surface 22a and the side surface of the protrusion 22 as shown in FIG. For example, the solder member B may have a dish-like member shape that covers the joint surface 22a and the side surface of the protrusion 22 or may be a paste.

これら組み付けた第1電極板20及び配線基板40と半導体素子10とを、半田部材Bが配置された突起部22及び制御電極49を、エミッタ電極13及びゲート電極14にそれぞれ対向させて配置させる。対向させた第1電極板20及び配線基板40と半導体素子10とを、所定の圧力を印加させながら、半田部材Bを溶融させることで電気的に接合させる。   The assembled first electrode plate 20 and wiring substrate 40 and the semiconductor element 10 are arranged so that the protrusion 22 and the control electrode 49 on which the solder member B is arranged are opposed to the emitter electrode 13 and the gate electrode 14, respectively. The first electrode plate 20 and the wiring substrate 40 opposed to each other and the semiconductor element 10 are electrically joined by melting the solder member B while applying a predetermined pressure.

次に、半導体素子10と第2電極板30とを、コレクタ電極17と接続面32とが対向するように配置する。この状態で半田部材Bを半田抵抗膜33内に配置し、所定の圧力を半導体素子10及び第2電極板30に印加させながら半田部材Bを融解させることで電気的に接合する。   Next, the semiconductor element 10 and the second electrode plate 30 are arranged so that the collector electrode 17 and the connection surface 32 face each other. In this state, the solder member B is disposed in the solder resistance film 33 and is electrically joined by melting the solder member B while applying a predetermined pressure to the semiconductor element 10 and the second electrode plate 30.

このように半導体素子10、第1電極板20、第2電極板30及び配線基板40を、半田部材Bにより電気的に接合、及び、係合部45及び開口部26により機械的に係合することにより、図6に示すように半導体パッケージ1が形成される。   As described above, the semiconductor element 10, the first electrode plate 20, the second electrode plate 30, and the wiring board 40 are electrically joined by the solder member B and mechanically engaged by the engaging portion 45 and the opening portion 26. As a result, the semiconductor package 1 is formed as shown in FIG.

このように構成された半導体パッケージ1によれば、配線基板40に他構成品の外側より突出する凸部42を備え、凸部42上に制御電極49と配線Fにより接続された外部接続端子47を設けることで、ワイヤボンディングを用いることなく、制御電極49の配線をパッケージ外に引き出すことができる。即ち、その外形状が小型であるとともに、配線を外部に引き出すことが可能となる半導体パッケージ1とすることができる。   According to the semiconductor package 1 configured as described above, the wiring substrate 40 includes the protruding portion 42 protruding from the outside of the other components, and the external connection terminal 47 connected to the control electrode 49 and the wiring F on the protruding portion 42. By providing the wiring, the wiring of the control electrode 49 can be drawn out of the package without using wire bonding. That is, it is possible to obtain a semiconductor package 1 whose outer shape is small and in which wiring can be drawn to the outside.

また、第1電極板20と配線基板40とを、開口部26に係合部45を係合させることで、開口部26と係合部45、及び、貫入口43と突起部22の側面とがそれぞれ干渉し、第1電極板20及び配線基板40がそれぞれ離間する方向に移動しても、各位置で係止される。これにより、第1電極板20及び配線基板40が脱離することがなく、確実に、係合される(組み付く)こととなる。   Further, by engaging the first electrode plate 20 and the wiring board 40 with the engaging portion 45 in the opening 26, the opening 26 and the engaging portion 45, and the penetrating port 43 and the side surface of the protruding portion 22. Even if the first electrode plate 20 and the wiring substrate 40 move in the direction of separating from each other, they are locked at each position. Thus, the first electrode plate 20 and the wiring board 40 are surely engaged (assembled) without being detached.

また、配線基板40(絶縁基板41)に切欠部46を設けることで、切欠部46を設けた箇所が容易に弾性変形させることが可能となる。これにより、係合部45を開口部26に係合させる際に、切欠部46が設けられている側の係合部45を最後に係合させることで、係合部45周辺が容易に変形する。このため、第1電極板20及び配線基板40を容易に組み付けることが可能となる。   In addition, by providing the cutout portion 46 in the wiring board 40 (insulating substrate 41), the location where the cutout portion 46 is provided can be easily elastically deformed. As a result, when the engaging portion 45 is engaged with the opening portion 26, the periphery of the engaging portion 45 is easily deformed by finally engaging the engaging portion 45 on the side where the notch portion 46 is provided. To do. For this reason, the first electrode plate 20 and the wiring board 40 can be easily assembled.

さらに、第1電極板20及び配線基板40の係合は、溶接を行なうことなく、係合部45を開口部26に係合させるだけでよいため、例えば溶接や接着等を行なう必要が無く、容易に組み立てることができる。これは例えば、溶接により第1電極板20及び配線基板40を組み付ける場合には、まず、第1電極板20と配線基板40とを位置合わせ等を行ったあと組み立て、その後溶接を行なう、というような少なくとも2工程必要となる。しかし、半導体パッケージ1では、組立時に係合部45と開口部26とを係合させるだけでよい、即ち、組立のみの1工程で第1電極板20及び配線基板40を組み付けることが可能となる。このため、製造(組立)工程の低減となり、半導体パッケージ1の製造コストの低減にもなる。   Furthermore, the first electrode plate 20 and the wiring board 40 can be engaged with each other only by engaging the engaging portion 45 with the opening portion 26 without performing welding. For example, there is no need to perform welding or bonding. Can be easily assembled. For example, when the first electrode plate 20 and the wiring substrate 40 are assembled by welding, the first electrode plate 20 and the wiring substrate 40 are first assembled after being aligned, and then welded. At least two steps are required. However, in the semiconductor package 1, it is only necessary to engage the engaging portion 45 and the opening 26 at the time of assembly, that is, the first electrode plate 20 and the wiring substrate 40 can be assembled in one process only of assembly. . For this reason, the manufacturing (assembly) process is reduced, and the manufacturing cost of the semiconductor package 1 is also reduced.

また、第1電極板20及び配線基板40は、台座部24及び先端部48や、突起部22及び貫入口43等、各対応する部材形状によりそれぞれが案内されて所定の位置で組み立て可能な構造であり、組立ミスや、位置のずれ等を防止することも可能となる。これにより、突起部22の接合面22a及び制御電極49は、半導体素子10のエミッタ電極13及びゲート電極14と半田部材B等により電気的に確実に接続されることとなる。   Further, the first electrode plate 20 and the wiring board 40 are structured such that each of the first electrode plate 20 and the wiring board 40 can be assembled at a predetermined position by being guided by the corresponding member shapes such as the pedestal portion 24 and the distal end portion 48, the protruding portion 22 and the penetration opening 43. Thus, it is possible to prevent an assembly error or a position shift. As a result, the bonding surface 22a of the protrusion 22 and the control electrode 49 are securely and electrically connected to the emitter electrode 13 and the gate electrode 14 of the semiconductor element 10 by the solder member B or the like.

上述したように、第一の実施の形態に係る半導体パッケージ1によれば、第1電極板20及び配線基板40は、突起部22貫入口43に貫入させ、係合部45を開口部26へそれぞれ係合させることで、互いに離脱することなく確実に組み付けることが可能となる。また、上述したように、係合部45と開口部26とを係合させるだけで係合部45と開口部26とを組み付けることが可能となり、製造(組立)工数の低減にもなる。また、半導体パッケージの製造コストを低減することも可能となる。また、半導体パッケージ1の構成とすることで、小型化にもなる。   As described above, according to the semiconductor package 1 according to the first embodiment, the first electrode plate 20 and the wiring board 40 are inserted into the protrusion 22 penetration port 43, and the engaging portion 45 is connected to the opening 26. By engaging with each other, it is possible to reliably assemble them without detaching from each other. Further, as described above, the engaging portion 45 and the opening portion 26 can be assembled simply by engaging the engaging portion 45 and the opening portion 26, and the manufacturing (assembly) man-hours can be reduced. In addition, the manufacturing cost of the semiconductor package can be reduced. Further, the configuration of the semiconductor package 1 can reduce the size.

さらに、台座部24により、先端部48が確実に保持されるとともに、半田部材Bによりゲート電極14に固定されるため、所定の位置で確実に保持可能となり、信頼性の向上にもなる。   Furthermore, since the front end portion 48 is securely held by the pedestal portion 24 and is fixed to the gate electrode 14 by the solder member B, it can be reliably held at a predetermined position, and reliability is improved.

次に、本発明の第2の実施の形態に係る半導体パッケージ1Aを図7〜12を用いて説明する。
図7は本発明の第2の実施の形態に係る半導体パッケージ1Aを示す斜視図、図8は同半導体パッケージ1Aの構成を示す分解斜視図、図9は同半導体パッケージ1Aの構成を示す分解斜視図である。なお、図7〜12において図1〜6と同一機能部分には同一符号を付し、その詳細な説明は省略する。
Next, a semiconductor package 1A according to a second embodiment of the present invention will be described with reference to FIGS.
7 is a perspective view showing a semiconductor package 1A according to a second embodiment of the present invention, FIG. 8 is an exploded perspective view showing the configuration of the semiconductor package 1A, and FIG. 9 is an exploded perspective view showing the configuration of the semiconductor package 1A. FIG. 7 to 12, the same functional parts as those in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof is omitted.

半導体パッケージ1Aは、半導体素子10と、第1主面11側に設けられた第1電極板50と、第2主面12側に設けられた第2電極板30と、半導体素子10及び第1電極板50の間に設けられた配線基板60とを備えている。   The semiconductor package 1A includes a semiconductor element 10, a first electrode plate 50 provided on the first main surface 11 side, a second electrode plate 30 provided on the second main surface 12 side, the semiconductor element 10 and the first And a wiring board 60 provided between the electrode plates 50.

第1電極板50は、銅等の導電性材料により方形板状に形成された第1基板本体51と、この第1基板本体51の一方の面51aに設けられ、接合面52aを有する突起部52とを備えている。   The first electrode plate 50 includes a first substrate body 51 formed in a square plate shape with a conductive material such as copper, and a protrusion having a bonding surface 52a provided on one surface 51a of the first substrate body 51. 52.

突起部52は、略中央位置に略方形の貫通孔23と、この貫通孔23内周部であって他方の面51b側に設けられた互いに向き合う2つの台座部53と、突起部52に設けられ貫通孔23から突起部52の外側面まで形成され、台座部53と台座部53に挟まれて設けられた連通路25と、この連通路25が設けられた突起部52の側面に設けられた複数(図中2つ)の開口部26と、突起部52の、連通路25と対向する外側面に設けられた引掛部54と、を有している。   The projecting portion 52 is provided in the projecting portion 52, a substantially rectangular through hole 23 at a substantially central position, two pedestal portions 53 provided on the inner surface of the through hole 23 on the other surface 51 b side, and facing each other. The communication passage 25 is formed from the through hole 23 to the outer surface of the projection 52, and is provided between the pedestal 53 and the pedestal 53, and provided on the side surface of the projection 52 where the communication passage 25 is provided. In addition, a plurality of (two in the figure) openings 26 and a hooking portion 54 provided on the outer surface of the protrusion 52 facing the communication path 25 are provided.

引掛部54は、その高さが突起部52よりも低く形成されており、引掛部54の突起部52側面から端面までの距離は、引掛部54と突起部52との長さが、後述する貫入口62の対応する内面間の長さと同等になるよう形成されている。   The hook portion 54 is formed so that its height is lower than that of the protrusion portion 52. The distance from the side surface of the protrusion portion 52 to the end surface of the hook portion 54 is the length of the hook portion 54 and the protrusion portion 52, which will be described later. It is formed so as to be equivalent to the length between corresponding inner surfaces of the penetrating inlet 62.

配線基板60は、絶縁基板61に設けられ、その内面の対向する内面間が引掛部54及び突起部52の対応する外面間とが同等になるように形成された貫入口62と、先端に凸字形状の先端部64を有する突出部63と、突出部63が設けられた貫入口62の内側面に、開口部26の対応位置に設けられた2つの係合部45と、を備えている。なお、先端部64は制御電極49を有している。   The wiring substrate 60 is provided on the insulating substrate 61, and has a through-hole 62 formed so that the inner surfaces of the inner surfaces facing each other are equal to the corresponding outer surfaces of the hooking portion 54 and the protruding portion 52, and a protrusion at the tip. The protrusion part 63 which has the character-shaped front-end | tip part 64, and the two engaging parts 45 provided in the corresponding position of the opening part 26 are provided in the inner surface of the penetration port 62 in which the protrusion part 63 was provided. . The tip 64 has a control electrode 49.

次に、このような半導体パッケージ1Aの製造方法を図10〜12を用いて説明する。
なお、図10は同半導体パッケージ1Aに用いられる第1電極板50及び配線基板600の組立の一例を示す斜視図、図11は同半導体パッケージ1Aに用いられる第1電極板50及び配線基板60の組立の一例を示す斜視図、図12は同半導体パッケージ1Aの構成を示す断面図である。
Next, a method for manufacturing such a semiconductor package 1A will be described with reference to FIGS.
10 is a perspective view showing an example of the assembly of the first electrode plate 50 and the wiring board 600 used in the semiconductor package 1A, and FIG. 11 shows the first electrode plate 50 and the wiring board 60 used in the semiconductor package 1A. FIG. 12 is a cross-sectional view showing a configuration of the semiconductor package 1A.

図10に示すように、第1電極板50と配線基板60との組み立て(組み付け)を行なう。まず、第1電極板50と配線基板60との向きを、連通路25及び貫通孔23と、突出部63及び先端部64とがそれぞれ対応する位置となるよう配置させる。次に、この状態で、突起部52の引掛部54が設けられている外側面と、貫入口62の対応する内側面とを近接させるとともに、第1電極板50上に配線基板60を積載させる。貫入口62は、突起部52よりも引掛部54方向の長さが長いため、第1基板本体51の一方の面51a上に、係合部45が載置されることとなる。   As shown in FIG. 10, the first electrode plate 50 and the wiring board 60 are assembled (assembled). First, the orientation of the first electrode plate 50 and the wiring board 60 is arranged such that the communication path 25 and the through hole 23, the protruding portion 63, and the distal end portion 64 are in corresponding positions. Next, in this state, the outer surface on which the hook portion 54 of the protrusion 52 is provided and the corresponding inner surface of the through-hole 62 are brought close to each other, and the wiring substrate 60 is loaded on the first electrode plate 50. . Since the penetrating port 62 has a longer length in the hooking portion 54 direction than the protruding portion 52, the engaging portion 45 is placed on the one surface 51 a of the first substrate body 51.

この状態で配線基板60を突起部52の引掛部54が設けられている外側面から離間させる方向、即ち、係合部45と開口部26とが係合する方向にスライドさせる。このスライドさせるとき、配線基板60(絶縁基板61)は、引掛部54の厚み分、湾曲(弾性変形)している。また、貫入口62のスライド方向の長さと突起部52及び引掛部54との長さは略同一に形成されており、係合部45と開口部26とが係合すると、引掛部54から貫入口62の内側面が外れる。このため、図11に示すように、湾曲していた配線基板60は復元力により、配線基板60下面が第1電極板50の一方の面51aに当接することとなる。   In this state, the wiring board 60 is slid in a direction in which the wiring board 60 is separated from the outer surface on which the hook portion 54 of the protrusion 52 is provided, that is, in a direction in which the engaging portion 45 and the opening portion 26 are engaged. When this sliding is performed, the wiring substrate 60 (insulating substrate 61) is curved (elastically deformed) by the thickness of the hook portion 54. Further, the length of the penetrating port 62 in the sliding direction is substantially the same as the length of the protrusion 52 and the hooking portion 54, and when the engaging portion 45 and the opening 26 are engaged, the penetrating portion 54 penetrates from the hooking portion 54. The inner surface of the inlet 62 is removed. For this reason, as shown in FIG. 11, the curved wiring board 60 comes into contact with the one surface 51 a of the first electrode plate 50 by the restoring force.

係合部45と開口部26とが係合し、配線基板60の下面が第1電極板50の上面に当接すると、係合部45の外面は開口部26に覆われるとともに、突起部52側面及び引掛部54の側面は貫入口62内周面に覆われる。このため、第1電極板50と配線基板60とが離間する方向に移動した際には、各係合部45と各開口部26、及び、突起部52の外側面又は引掛部54と貫入口62の内側面とのいずれかで互いに干渉する。この干渉により、接合面52aの水平方向には各側面により、接合面52aに対して直交方向には係合部45と開口部26とによりそれぞれ係止されることとなり、配線基板60が第1電極板50から離脱することがない。   When the engaging portion 45 and the opening portion 26 are engaged and the lower surface of the wiring board 60 is in contact with the upper surface of the first electrode plate 50, the outer surface of the engaging portion 45 is covered with the opening portion 26 and the protruding portion 52. The side surface and the side surface of the hook portion 54 are covered with the inner peripheral surface of the through-hole 62. For this reason, when the first electrode plate 50 and the wiring board 60 move in a direction away from each other, each engaging portion 45 and each opening portion 26 and the outer surface of the projection portion 52 or the hooking portion 54 and the penetration port Interfere with each other on either of the inner surfaces of 62. Due to this interference, the joint surface 52a is locked by the side surfaces in the horizontal direction and by the engaging portion 45 and the opening portion 26 in the direction orthogonal to the joint surface 52a. There is no detachment from the electrode plate 50.

なお、半導体素子10、第1電極板50、第2電極板30及び配線基板60を、上述した第1の実施の形態に係る半導体パッケージ1と同様に、半田部材Bによる接合、及び、係合部45及び開口部26による係合することで、図12に示すように半導体パッケージ1Aが形成される。   The semiconductor element 10, the first electrode plate 50, the second electrode plate 30, and the wiring board 60 are joined and engaged by the solder member B, similarly to the semiconductor package 1 according to the first embodiment described above. By engaging with the portion 45 and the opening 26, the semiconductor package 1A is formed as shown in FIG.

このような半導体パッケージ1Aにおいて、第1電極板50に配線基板60の組み付けは、特に押圧を加える必要が無く、配線基板60をスライドさせることで、係合部45と開口部26とが係合し、さらに弾性変形した配線基板60の復元力により、自動的に組み付くこととなる。このため、容易に第1電極板50と配線基板60とを組み付けることが可能となる。   In such a semiconductor package 1A, the assembly of the wiring substrate 60 to the first electrode plate 50 does not require any particular pressing, and the engagement portion 45 and the opening 26 are engaged by sliding the wiring substrate 60. In addition, it is automatically assembled by the restoring force of the wiring board 60 that is further elastically deformed. For this reason, the first electrode plate 50 and the wiring substrate 60 can be easily assembled.

また、台座部53は、スライド方向と直交する方向に複数設けたため、配線基板60をスライドした場合であっても、常に突出部63の先端部64が確実に台座部53に積載されることとなる。即ち、配線基板60のスライド方向に台座部を設けると、スライド前に、先端部64が台座部に積載されず、自重により下方に撓む虞がある。この状態で配線基板60をスライドさせると、先端部64の先端面と台座部の側面とが当接する虞がある。   In addition, since a plurality of pedestal portions 53 are provided in a direction orthogonal to the sliding direction, even when the wiring board 60 is slid, the distal end portion 64 of the protruding portion 63 is always reliably loaded on the pedestal portion 53. Become. That is, when the pedestal is provided in the sliding direction of the wiring board 60, the tip 64 is not stacked on the pedestal before the slide, and may be bent downward by its own weight. If the wiring board 60 is slid in this state, the tip surface of the tip portion 64 may come into contact with the side surface of the pedestal portion.

この状態で、さらに配線基板60をスライドさせることで、突出部63にスライド方向の負荷がかかり、突出部63が弾性変形又は塑性変形するとともに、所定の位置に制御電極49が位置しない虞がある。この制御電極49の位置ズレは、半導体パッケージ1Aの組立時に、接合不良や接触不良等の原因になる。このため、半導体パッケージ1Aは、台座部53をスライド方向と直交方向に複数設けることで、確実に先端部64を常時保持・案内し、接合不良を防止することが可能となる。   If the wiring board 60 is further slid in this state, a load in the sliding direction is applied to the protruding portion 63, the protruding portion 63 is elastically deformed or plastically deformed, and the control electrode 49 may not be positioned at a predetermined position. . This misalignment of the control electrode 49 causes a bonding failure or a contact failure during the assembly of the semiconductor package 1A. For this reason, in the semiconductor package 1A, by providing a plurality of the pedestal portions 53 in the direction orthogonal to the sliding direction, it is possible to reliably hold and guide the distal end portion 64 at all times and to prevent poor bonding.

上述したように、第2の実施の形態に係る半導体パッケージ1Aによれば、半導体パッケージ1と同様の効果を有し、さらに、配線基板60をスライドするだけで、より容易に第1電極板50と配線基板60とを組み付けることが可能となり、製造(組立)工程及び製造コストの低減とすることが可能となる。   As described above, the semiconductor package 1A according to the second embodiment has the same effect as that of the semiconductor package 1. Furthermore, the first electrode plate 50 can be more easily obtained by simply sliding the wiring board 60. And the wiring board 60 can be assembled, and the manufacturing (assembly) process and the manufacturing cost can be reduced.

次に、本発明の変形例に係る半導体パッケージ1Bを図13を用いて説明する。
図13は本発明の変形例に係る半導体パッケージ1Bの第1電極板50A及び配線基板60Aの組立の一例を示す斜視図である。なお、図13において図1〜12と同一機能部分には同一符号を付し、その詳細な説明は省略する。
Next, a semiconductor package 1B according to a modification of the present invention will be described with reference to FIG.
FIG. 13 is a perspective view showing an example of assembly of the first electrode plate 50A and the wiring board 60A of the semiconductor package 1B according to the modification of the present invention. In FIG. 13, the same functional parts as those in FIGS. 1 to 12 are denoted by the same reference numerals, and detailed description thereof is omitted.

半導体パッケージ1Bは、半導体素子10と、第1主面11側に設けられた第1電極板50Aと、第2主面12側に設けられた第2電極板30と、半導体素子10及び第1電極板50Aの間に設けられた配線基板60Aとを備えている。   The semiconductor package 1B includes the semiconductor element 10, the first electrode plate 50A provided on the first main surface 11 side, the second electrode plate 30 provided on the second main surface 12 side, the semiconductor element 10 and the first element. And a wiring board 60A provided between the electrode plates 50A.

引掛部54は、貫入口62に覆われる側面に少なくとも1つの開口部55を備えている。また、貫入口62は、開口部55に係合される係合部65を備えている。   The hook portion 54 includes at least one opening 55 on a side surface covered with the penetrating opening 62. Further, the penetrating inlet 62 includes an engaging portion 65 that is engaged with the opening 55.

次に、このような半導体パッケージ1Bの製造方法を図13を用いて説明する。
図13に示すように、まず、上述した半導体パッケージ1Aと同様に、配線基板60Aの貫入口62の内側面を突起部52の引掛部54が設けられている外側面から離間させる方向、即ち、係合部45と開口部26とが係合する方向にスライドさせ、係合部45と開口部26とを係合させる。
Next, a method for manufacturing such a semiconductor package 1B will be described with reference to FIG.
As shown in FIG. 13, first, similarly to the semiconductor package 1A described above, the direction in which the inner side surface of the through-hole 62 of the wiring board 60A is separated from the outer side surface where the hooking portion 54 of the protruding portion 52 is provided, that is, The engaging portion 45 and the opening 26 are slid in the engaging direction, and the engaging portion 45 and the opening 26 are engaged.

このスライドさせたとき、係合部65の下面は引掛部54上面に当接しており、配線基板60A(絶縁基板61)は、引掛部54の厚み分、湾曲(弾性変形)することとなる。   When this sliding is performed, the lower surface of the engaging portion 65 is in contact with the upper surface of the hook portion 54, and the wiring board 60 </ b> A (insulating substrate 61) is curved (elastically deformed) by the thickness of the hook portion 54.

この状態で係合部65の周辺の配線基板60Aを押圧させ、係合部65を弾性変形させる、又は、係合部65の周辺を第1基板本体51に係合部65が対向するように湾曲させる。即ち、係合部65又は係合部65の周辺を弾性変形させることで、係合部65を、開口部55に係合させる。   In this state, the wiring board 60A around the engaging portion 65 is pressed to elastically deform the engaging portion 65, or the engaging portion 65 faces the first substrate body 51 around the engaging portion 65. Curve. That is, the engaging portion 65 is engaged with the opening 55 by elastically deforming the engaging portion 65 or the periphery of the engaging portion 65.

また、貫入口62のスライド方向の長さと突起部52及び引掛部54との長さは略同一に形成されており、係合部45、65と開口部26,55とが係合すると、引掛部54の側面と貫入口62の内側面が当接する。また、配線基板60A下面が第1電極板50Aの一方の面51aに当接することとなる。   The length of the through-hole 62 in the sliding direction is substantially the same as the length of the protrusion 52 and the hooking portion 54. When the engaging portions 45 and 65 are engaged with the openings 26 and 55, the hooking portion 52 is hooked. The side surface of the portion 54 and the inner side surface of the penetrating entrance 62 abut. In addition, the lower surface of the wiring board 60A comes into contact with one surface 51a of the first electrode plate 50A.

係合部45,65と開口部26,55とが係合し、配線基板60Aの下面が第1電極板50Aの上面に当接すると、係合部45,65の外面は開口部26,55にそれぞれ覆われるとともに、突起部52側面及び引掛部54の側面は貫入口62内周面に覆われる。このため、第1電極板50と配線基板60とが離間する方向に移動した際には、各係合部45,65と各開口部26,55、及び、突起部52の外側面又は引掛部54と貫入口62の内側面とのいずれかで互いに干渉する。この干渉により、接合面52aの水平方向には各側面により、接合面52aに対して直交方向には係合部45,65と開口部26,55とによりそれぞれ係止されることとなり、配線基板60Aが第1電極板50Aから離脱することがない。   When the engaging portions 45 and 65 are engaged with the openings 26 and 55 and the lower surface of the wiring board 60A is in contact with the upper surface of the first electrode plate 50A, the outer surfaces of the engaging portions 45 and 65 are the openings 26 and 55. And the side surface of the protrusion 52 and the side surface of the hook portion 54 are covered by the inner peripheral surface of the penetrating entrance 62. For this reason, when the first electrode plate 50 and the wiring board 60 move in a direction away from each other, the engagement portions 45 and 65, the openings 26 and 55, and the outer surface or hooking portion of the projection 52 54 and the inner surface of the penetration 62 interfere with each other. Due to this interference, the joint surface 52a is locked by the side surfaces in the horizontal direction and by the engaging portions 45, 65 and the openings 26, 55 in the direction orthogonal to the joint surface 52a. 60A does not leave the first electrode plate 50A.

なお、半導体素子10、第1電極板50、第2電極板30及び配線基板60を、上述した第1の実施の形態に係る半導体パッケージ1と同様に、半田部材Bによる接合、及び、係合部45及び開口部26による係合することで、図12に示すように半導体パッケージ1Aが形成される。   The semiconductor element 10, the first electrode plate 50, the second electrode plate 30, and the wiring board 60 are joined and engaged by the solder member B, similarly to the semiconductor package 1 according to the first embodiment described above. By engaging with the portion 45 and the opening 26, the semiconductor package 1A is formed as shown in FIG.

このような半導体パッケージ1Bにおいて、第1電極板50Aに配線基板60Aの組み付けは、配線基板60をスライドさせることで、係合部45と開口部26とが係合し、さらに弾性変形した係合部65又は係合部65周辺により開口部55に組み付くこととなる。このため、容易に第1電極板50Aと配線基板60Aとを組み付けることが可能であるとともに、係合部45,65及び開口部26,55の対向する2箇所で係合させることが可能となるため、第1電極板50Aと配線基板60Aとが離間することがない。   In such a semiconductor package 1B, the wiring board 60A is assembled to the first electrode plate 50A by sliding the wiring board 60 so that the engaging portion 45 and the opening 26 are engaged, and further elastically deformed. It will be assembled to the opening 55 around the part 65 or the engaging part 65. Therefore, the first electrode plate 50A and the wiring board 60A can be easily assembled and can be engaged at the two opposing positions of the engaging portions 45 and 65 and the openings 26 and 55. Therefore, the first electrode plate 50A and the wiring board 60A are not separated from each other.

また、貫入口62内側面により、突起部52及び引掛部54の側面を覆い、さらに係合部45,65及び開口部26,55で係合されるため、各方向に第1電極板50Aと配線基板60Aが干渉する。このため、確実に第1電極板50Aと配線基板60Aとを組み付けることが可能となる。   Further, the inner side surface of the penetrating port 62 covers the side surfaces of the protrusion 52 and the hooking portion 54, and is further engaged by the engaging portions 45, 65 and the openings 26, 55. The wiring board 60A interferes. Therefore, the first electrode plate 50A and the wiring board 60A can be reliably assembled.

上述したように、変形例に係る半導体パッケージ1Bによれば、半導体パッケージ1、半導体パッケージ2Aと略同等の効果を有し、さらに、第1電極板50A及び配線基板60Aとが各方向で確実に干渉する構成とすることで、第1電極板50Aと配線基板60Aとを確実に組み付けることが可能となる。   As described above, according to the semiconductor package 1B according to the modification, the semiconductor package 1 and the semiconductor package 2A have substantially the same effects, and the first electrode plate 50A and the wiring board 60A are reliably provided in each direction. By setting it as the structure which interferes, it becomes possible to assemble | attach the 1st electrode board 50A and the wiring board 60A reliably.

なお、上述した発明の形態以外の変形例について説明する。上述した例では、例えば半導体パッケージ1、1Aでは、第1電極板20,50及び第2電極板30の材質は銅材としているが、導電性材料であれば、例えばアルミニウム、モリブデン、銅モリブデン合金及び銅タングステン合金等でも適用できる。また、第1電極板20,50及び第2電極板30の材質と異なる各種材料のクラッド又は鍍金により、必要な箇所に導電性を有する構成としてもよい。   Modifications other than the above-described embodiments will be described. In the above-described example, for example, in the semiconductor packages 1 and 1A, the material of the first electrode plates 20 and 50 and the second electrode plate 30 is a copper material. However, if the material is a conductive material, for example, aluminum, molybdenum, copper-molybdenum alloy Also applicable to copper tungsten alloy and the like. Moreover, it is good also as a structure which has electroconductivity in a required location by the clad or plating of various materials different from the material of the 1st electrode plates 20 and 50, and the 2nd electrode plate 30. FIG.

また、半田部材Bは、Sn−Pb共晶半田、鉛フリー半田、又は、Pb立地高温半田等、どのような半田部材であってもよい。さらに、第2電極板30と絶縁基板40,60との間であって、半導体素子10の外周縁よりも外側に、スペーサを設けてもよい。スペーサを設けることで、第2電極板30と絶縁基板40,60との距離を一定に保持することが可能となり、外力による半導体素子10の破損を防止することが可能となる。   Also, the solder member B may be any solder member such as Sn—Pb eutectic solder, lead-free solder, or Pb location high temperature solder. Furthermore, a spacer may be provided between the second electrode plate 30 and the insulating substrates 40 and 60 and outside the outer peripheral edge of the semiconductor element 10. By providing the spacer, the distance between the second electrode plate 30 and the insulating substrates 40 and 60 can be kept constant, and damage to the semiconductor element 10 due to external force can be prevented.

また、突起部22,52には、貫通孔23を設け、貫通孔23の内面であって、第1電極板20,50の他方の面21b、51b側に1つ、又は複数の台座部24,53を設けるとしたが、これは、台座部24,53でなくてもよい。また、貫通孔23を設けなくとも良い。即ち、突起部22,52に、突出部44,63及び先端部48,64が配置可能な連通路及び窪みを設けることでも適用できる。さらに、突出部44,63の長さや各種電極13,14の位置(配置)等も、適宜設定可能である。   In addition, the protrusions 22 and 52 are provided with a through hole 23, which is the inner surface of the through hole 23, and one or a plurality of pedestal parts 24 on the other surfaces 21 b and 51 b side of the first electrode plates 20 and 50. , 53 are provided, but this may not be the pedestals 24, 53. Further, the through hole 23 may not be provided. That is, the present invention can also be applied by providing the protrusions 22 and 52 with communication paths and depressions in which the protrusions 44 and 63 and the tip portions 48 and 64 can be arranged. Furthermore, the lengths of the protrusions 44 and 63 and the positions (arrangements) of the various electrodes 13 and 14 can be set as appropriate.

さらに、上述した半導体パッケージ1,1Aの開口部26及び係合部45は、突起部22,52の各側面に対して2つ設けるとしたが、これは2つに限定されるものではない。また、開口部26及び係合部45の形状も半円状でなくとも係合可能であれば適用できる。   Furthermore, although the two opening portions 26 and the engaging portions 45 of the semiconductor packages 1 and 1A described above are provided on each side surface of the protruding portions 22 and 52, the number is not limited to two. Further, the shape of the opening 26 and the engaging portion 45 is not limited to a semicircular shape, but can be applied as long as it can be engaged.

また、上述した半導体パッケージ1では、突起部22の貫通孔23を介して相対する外側面に開口部26を設けるとしたが、他の側面にも設けてもよいし、他の側面に設けるように形成してもよい。同様に、半導体パッケージ1Aでも、突起部52の他の外側面に開口部26を設けてもよいし、他の側面に設けるように形成してもよい。なお、このとき、各開口部26に対応する貫入口43,62の内面に係合部45を設けることとする。   Further, in the semiconductor package 1 described above, the opening 26 is provided on the outer surface facing the through hole 23 of the protrusion 22, but it may be provided on the other side surface or on the other side surface. You may form in. Similarly, in the semiconductor package 1 </ b> A, the opening 26 may be provided on the other outer surface of the protrusion 52, or may be formed on the other side surface. At this time, the engaging portions 45 are provided on the inner surfaces of the through holes 43 and 62 corresponding to the respective openings 26.

なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。例えば、実施形態に示される全構成要素から幾つかの構成要素を削除してもよい。さらに、異なる実施形態にわたる構成要素を適宜組み合わせてもよい。   Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

本発明の第1の実施の形態に係る半導体パッケージを示す斜視図。1 is a perspective view showing a semiconductor package according to a first embodiment of the present invention. 同半導体パッケージの構成を示す分解斜視図。The disassembled perspective view which shows the structure of the semiconductor package. 同半導体パッケージの構成を示す分解斜視図。The disassembled perspective view which shows the structure of the semiconductor package. 同半導体パッケージに用いられる第1電極板及び配線基板の組立の一例を示す斜視図。The perspective view which shows an example of the assembly of the 1st electrode board and wiring board which are used for the same semiconductor package. 同半導体パッケージに用いられる第1電極板及び配線基板の組立の一例を示す斜視図。The perspective view which shows an example of the assembly of the 1st electrode board and wiring board which are used for the same semiconductor package. 同半導体パッケージの構成を示す断面図。Sectional drawing which shows the structure of the semiconductor package. 本発明の第2の実施の形態に係る半導体パッケージを示す斜視図。The perspective view which shows the semiconductor package which concerns on the 2nd Embodiment of this invention. 同半導体パッケージの構成を示す分解斜視図。The disassembled perspective view which shows the structure of the semiconductor package. 同半導体パッケージの構成を示す分解斜視図。The disassembled perspective view which shows the structure of the semiconductor package. 同半導体パッケージに用いられる第1電極板及び配線基板の組立の一例を示す斜視図。The perspective view which shows an example of the assembly of the 1st electrode board and wiring board which are used for the same semiconductor package. 同半導体パッケージに用いられる第1電極板及び配線基板の組立の一例を示す斜視図。The perspective view which shows an example of the assembly of the 1st electrode board and wiring board which are used for the same semiconductor package. 同半導体パッケージの構成を示す断面図。Sectional drawing which shows the structure of the semiconductor package. 本発明の変形例に係る半導体パッケージの第1電極板及び配線基板の組立の一例を示す斜視図。The perspective view which shows an example of the assembly of the 1st electrode board and wiring board of the semiconductor package which concern on the modification of this invention.

符号の説明Explanation of symbols

1…半導体パッケージ、10…半導体素子、11…第1の主面、12…第2の主面、13…エミッタ電極、14…ゲート電極、15,16…半田抵抗膜、17…コレクタ電極、20…第1電極板、21…第1基板本体、22…突起部、22a…接合面、23…貫通孔、24…台座部、25…連通路、26…開口部、27…穴部、30…第2電極板、31…第2基板本体、32…接続面、33…半田抵抗膜、40…配線基板、41…絶縁基板、42…凸部、43…貫入口、44…突出部、45…係合部、46…切欠部、47…外部接続端子、48…先端部、49…制御電極、B…導通部材(半田部材)、F…配線。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor package, 10 ... Semiconductor element, 11 ... 1st main surface, 12 ... 2nd main surface, 13 ... Emitter electrode, 14 ... Gate electrode, 15, 16 ... Solder resistance film, 17 ... Collector electrode, 20 DESCRIPTION OF SYMBOLS 1st electrode plate, 21 ... 1st board | substrate body, 22 ... Protrusion part, 22a ... Joining surface, 23 ... Through-hole, 24 ... Base part, 25 ... Communication path, 26 ... Opening part, 27 ... Hole part, 30 ... 2nd electrode plate 31 ... 2nd board | substrate body, 32 ... Connection surface, 33 ... Solder resistance film, 40 ... Wiring board, 41 ... Insulating substrate, 42 ... Projection, 43 ... Penetrating entrance, 44 ... Projection, 45 ... Engagement part 46 ... notch part 47 ... external connection terminal 48 ... tip part 49 ... control electrode B ... conduction member (solder member), F ... wiring.

Claims (8)

板状に形成され、第1の主面の中心部に設けられたゲート電極、第1の主面の前記ゲート電極の周囲に設けられたエミッタ電極、及び、第2の主面に設けられたコレクタ電極を有する半導体素子と、
板状に形成され、前記第1の主面に対向する一方の面に設けられ前記エミッタ電極の少なくとも一部と当接する突起部、この突起部の中心に設けられた貫通孔、この貫通孔の内周面の一部であって他方の面側に設けられた台座部、前記突起部に設けられ前記貫通孔から前記突起部の外側面まで形成された連通路、及び、前記突起部の外側面に設けられた複数の開口部を有する第1電極板と、
前記半導体素子と前記第1電極板との間に積層されるとともに狭持可能な板状に形成され、前記突起部が貫入される貫入口、その基端が前記貫入口の内周面に設けられ、その先端が前記貫通孔内部に位置するとともに前記台座部に保持され、前記連通路を介して延出する突出部、この突出部の先端に設けられ前記ゲート電極に電気的に接続される制御電極、及び、前記貫入口の内周面に複数設けられるとともに前記複数の開口部にそれぞれ係合し、その先端が前記突起部の外側面の内側に位置する係合部を有する配線基板と、
板状に形成され、その一方の主面が前記コレクタ電極と電気的に接続される第2電極板と、を備えることを特徴とする半導体パッケージ。
A gate electrode provided in the center of the first main surface, an emitter electrode provided around the gate electrode on the first main surface, and a second main surface formed in a plate shape A semiconductor element having a collector electrode;
A protrusion formed on one surface opposite to the first main surface and in contact with at least a part of the emitter electrode, a through hole provided in the center of the protrusion, A pedestal portion that is a part of the inner peripheral surface and is provided on the other surface side, a communication path that is provided in the protrusion and is formed from the through hole to the outer surface of the protrusion, and an outside of the protrusion A first electrode plate having a plurality of openings provided on a side surface;
Stacked between the semiconductor element and the first electrode plate and formed in a sandwichable plate shape, a through-hole through which the protrusion penetrates, and a base end thereof provided on the inner peripheral surface of the through-hole A protrusion that is located inside the through-hole and is held by the pedestal, and extends through the communication path, and is provided at the tip of the protrusion and is electrically connected to the gate electrode. A wiring board provided with a plurality of control electrodes and an inner peripheral surface of the penetrating opening and engaging with the plurality of openings, each of which has an engaging portion positioned on the inner side of the outer surface of the protruding portion; ,
It is formed in a plate shape, a semiconductor package of the second electrode plate main surface of one of which is connected before SL to the collector electrode and the electrically, comprising: a.
前記複数の開口部は、これら開口部の少なくともその一部が前記突起部を挟んで相対する前記外側面に設けられていることを特徴とする請求項1に記載の半導体パッケージ。   2. The semiconductor package according to claim 1, wherein at least a part of the plurality of openings is provided on the outer surface facing each other with the protrusion interposed therebetween. 板状に形成され、第1の主面の中心側に設けられたゲート電極、第1の主面のゲート電極の周囲に設けられたエミッタ電極、及び、第2の主面に設けられたコレクタ電極を有する半導体素子と、
板状に形成され、前記第1の主面に対向する対向面に前記エミッタ電極の少なくとも一部と当接する突起部、この突起部の中心に設けられた貫通孔、この貫通孔の内周面の一部であって前記対向面と相対する面側に設けられた台座部、前記突起部に設けられ前記貫通孔から前記突起部の外側面まで形成された連通路、前記突起部の外側面に設けられ、前記突起部の外側面に一部開口する少なくとも1つ有する開口部、及び、前記突起部の外側面であって前記対向面に設けられ突出する引掛部を有する第1電極板と、
前記半導体素子と前記第1電極板との間に積層されるとともに狭持可能な板状に形成され、前記突起部及び前記引掛部が貫入される貫入口、その基端が前記貫入口のうち周面の一部に設けられ、その先端が前記貫通孔内部に位置するとともに前記台座部に保持され、前記連通路を介して延出する突出部、この突出部の先端に設けられ前記ゲート電極に電気的に接続される制御電極、及び、前記貫入口の内周面に設けられるとともに前記開口部に係合し、その先端が前記突起部の外側面の内側に位置する係合部を有する配線基板と、
板状に形成され、その一方の主面が前記コレクタ電極と電気的に接続される第2電極板と、を備えることを特徴とする半導体パッケージ。
A gate electrode formed on the center side of the first main surface, an emitter electrode provided around the gate electrode of the first main surface, and a collector provided on the second main surface A semiconductor element having an electrode;
A projecting portion that is formed in a plate shape and abuts at least a part of the emitter electrode on an opposing surface that faces the first main surface, a through hole provided in the center of the projecting portion, and an inner peripheral surface of the through hole A pedestal portion provided on a surface side opposite to the facing surface, a communication path formed in the protrusion from the through hole to the outer surface of the protrusion, and an outer surface of the protrusion A first electrode plate having at least one opening partly opened on an outer side surface of the projection part, and a hooking part provided on the outer side surface of the projection part and projecting on the opposing surface; ,
It is laminated between the semiconductor element and the first electrode plate and is formed in a sandwichable plate shape. The through- hole through which the protrusion and the hook are penetrated, and the base end of the through- hole Protruding part provided at a part of the peripheral surface, the tip of which is located inside the through hole and held by the pedestal part and extending through the communication path, the gate electrode provided at the tip of the protruding part A control electrode that is electrically connected to the opening, and an engagement portion that is provided on the inner peripheral surface of the penetrating opening and engages with the opening, the tip of which is located inside the outer surface of the protrusion. A wiring board;
It is formed in a plate shape, a semiconductor package of the second electrode plate main surface of one of which is connected before SL to the collector electrode and the electrically, comprising: a.
前記開口部は、前記引掛部が設けられた前記突起部の外側面と前記突起部を挟んで対向する前記外側面に設けられていることを特徴とする請求項3に記載の半導体パッケージ。   4. The semiconductor package according to claim 3, wherein the opening is provided on the outer surface facing the outer surface of the protrusion provided with the hook portion with the protrusion interposed therebetween. 前記第1電極板は、前記引掛部の側面に設けられた開口部をさらに備え、
前記配線基板は前記貫入口の内側面に前記引掛部に設けられた開口部に係合する係合部をさらに備えることを特徴とする請求項3に記載の半導体パッケージ。
The first electrode plate further includes an opening provided on a side surface of the hook portion,
The semiconductor package according to claim 3, wherein the wiring board further includes an engaging portion that engages with an opening provided in the hook portion on an inner surface of the penetrating opening.
方形に形成され、一方の主面に設けられた突起部を有し、この突起部の側面に複数の開口部を有する第1電極板と、前記突起部が貫入される貫入口、及び、この貫入口の内側面に設けられ前記複数の開口部と係合し、その先端が前記突起部の外側面の内側に位置する係合部を有する配線基板とを、前記開口部及び前記係合部が係合可能な位置に配置させる工程と、
前記配線基板の前記複数の係合部を前記第1電極板の前記複数の開口部にそれぞれ係合させることで、前記配線基板と前記第1電極板とを組み付ける工程と、
組み付けた前記配線基板及び前記第1電極板と電極を有する半導体素子と導通部材で接合する工程と、を備えることを特徴とする半導体パッケージの製造方法。
A first electrode plate which is formed in a square shape and has a protrusion provided on one main surface, and a plurality of openings on a side surface of the protrusion; a penetration opening through which the protrusion penetrates; and A wiring board provided on an inner side surface of the penetrating hole, which engages with the plurality of openings, and has an engagement portion whose tip is located inside the outer side surface of the protrusion; And a step of disposing at a position that can be engaged,
Assembling the wiring board and the first electrode plate by engaging the plurality of engaging portions of the wiring board respectively with the plurality of openings of the first electrode plate;
A step of joining the wiring board, the first electrode plate, and the semiconductor element having electrodes to each other by a conductive member.
方形に形成され、一方の主面に設けられた突起部を有し、この突起部の少なくとも1つの側面に複数の開口部、及び、この開口部が設けられた前記突起部の側面と相対する側面に設けられた引掛部を有する第1電極板と、前記突起部及び前記引掛部が貫入される貫入口、及び、この貫入口の内側面の前記複数の開口部と係合し、その先端が前記突起部の外側面の内側に位置する係合部を有する配線基板とを、前記開口部及び前記係合部が係合可能な位置に配置させる工程と、
前記突起部の側面を前記貫入口の内側面で覆うとともに、前記複数の開口部と前記複数の係合部とをそれぞれ対向させる工程と、
対向する前記複数の開口部と前記複数の係合部とを、前記開口部と前記係合部とが係合する方向に移動させることで、前記開口部及び前記係合部を係合させる工程と、
前記引掛部及び前記突起部の側面を前記貫入口の内側面で覆うことで、前記配線基板と前記第1電極板とを組み付ける工程と、
組み付けた前記配線基板及び前記第1電極板と電極を有する半導体素子と導通部材で接合する工程と、を備えることを特徴とする半導体パッケージの製造方法。
The projection is formed in a square shape and has one main surface, and has a plurality of openings on at least one side of the projection and the side of the projection provided with the opening. A first electrode plate having a hooking portion provided on a side surface; a penetrating opening through which the protrusion and the hooking portion are inserted; and the plurality of openings on the inner side surface of the penetrating hole; Arranging a wiring board having an engaging portion located inside the outer surface of the protruding portion at a position where the opening and the engaging portion can be engaged;
Covering the side surface of the protrusion with the inner surface of the penetrating entrance, and making the plurality of openings and the plurality of engaging portions face each other;
The step of engaging the openings and the engagement portions by moving the plurality of openings and the engagement portions facing each other in a direction in which the openings and the engagement portions are engaged. When,
A step of assembling the wiring board and the first electrode plate by covering side surfaces of the hooking portion and the protrusion portion with an inner side surface of the penetrating port;
A step of joining the wiring board, the first electrode plate, and the semiconductor element having electrodes to each other by a conductive member.
方形に形成され、一方の主面に設けられた突起部を有し、この突起部の少なくとも1つの側面に複数の開口部、この開口部が設けられた前記突起部の側面と相対する側面に設けられた引掛部、及び、前記引掛部の側面に設けられた開口部を有する第1電極板と、前記突起部及び前記引掛部が貫入される貫入口、及び、この貫入口の内側面の前記複数の開口部にそれぞれ係合し、その先端が前記突起部及び前記引掛部の外側面の内側に位置する係合部を有する配線基板とを、前記開口部及び前記係合部が係合可能な位置に配置させる工程と、
前記突起部の側面を前記貫入口の内側面で覆うとともに、前記複数の開口部と前記複数の係合部とをそれぞれ対向させる工程と、
対向する前記突起部に設けられた複数の開口部と前記複数の係合部とを、前記突起部の開口部と前記係合部とが係合する方向に移動させることで、前記突起部の開口部及び前記係合部をそれぞれ係合させる工程と、
前記引掛部及び前記突起部の側面を前記貫入口の内側面で覆うとともに、前記係合部を前記引掛部の開口部に係合させることで、前記配線基板と前記第1電極板とを組み付ける工程と、
組み付けた前記配線基板及び前記第1電極板と電極を有する半導体素子と導通部材で接合する工程と、を備えることを特徴とする半導体パッケージの製造方法。
A protrusion formed on one main surface is formed in a square shape, and a plurality of openings are provided on at least one side of the protrusion, and a side opposite to the side of the protrusion provided with the opening. A hooking portion provided, a first electrode plate having an opening provided on a side surface of the hooking portion, a penetrating opening through which the protrusion and the hooking portion penetrate, and an inner side surface of the penetrating inlet The openings and the engaging portions engage with the plurality of openings, respectively, and the wiring board having an engaging portion whose tip is located inside the outer surface of the protrusion and the hooking portion. A step of arranging in a possible position;
Covering the side surface of the protrusion with the inner surface of the penetrating entrance, and making the plurality of openings and the plurality of engaging portions face each other;
By moving the plurality of openings and the plurality of engaging portions provided in the projecting portions facing each other in a direction in which the openings of the projecting portions and the engaging portions are engaged, Engaging each of the opening and the engaging portion;
The wiring board and the first electrode plate are assembled by covering the side surfaces of the hooking portion and the projection portion with the inner side surface of the penetrating entrance and engaging the engaging portion with the opening portion of the hooking portion. Process,
A step of joining the wiring board, the first electrode plate, and the semiconductor element having electrodes to each other by a conductive member.
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