JP2012238749A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2012238749A
JP2012238749A JP2011107234A JP2011107234A JP2012238749A JP 2012238749 A JP2012238749 A JP 2012238749A JP 2011107234 A JP2011107234 A JP 2011107234A JP 2011107234 A JP2011107234 A JP 2011107234A JP 2012238749 A JP2012238749 A JP 2012238749A
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Prior art keywords
conductor member
free end
semiconductor chip
semiconductor device
conductor
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Japanese (ja)
Inventor
Susumu Kimura
享 木村
Sho Kumada
翔 熊田
Yutaka Yoneda
裕 米田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure where conductor members serving as electrodes are easily exposed on main surfaces of a module.SOLUTION: In a semiconductor device, a semiconductor chip 1 is sealed with a sealing member 9 and a first conductor member 3 and a second conductor member 5 are respectively exposed on main surfaces. The first conductor member has a joining part 31, a free end part 32, and a deformation part 33 positioned between the joining part and the free end part. The deformation part is disposed so as to be bent at an obtuse angle or an acute angle with respect to the joining part and also be bent at an acute angle with respect to the free end part.

Description

本発明は、半導体装置に関し、詳しくは、半導体チップでの対向する両面がそれぞれ導体部材と電気的に接続された構成を有する半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a configuration in which both opposing surfaces of a semiconductor chip are electrically connected to a conductor member.

従来の樹脂モールド型半導体モジュール(以下、モジュールと記す)は、特許文献1及び特許文献2に示されるように、半導体素子を封止した樹脂封止部の2つの主面のいずれか一方から半導体素子で発生する熱を外部に放熱し、また、半導体素子と電気的に接続されかつ外部機器と接続される電極端子が樹脂封止部の側面から外部へ露出する構成を有する。   As shown in Patent Document 1 and Patent Document 2, a conventional resin mold type semiconductor module (hereinafter referred to as a module) is a semiconductor from either one of two main surfaces of a resin sealing portion in which a semiconductor element is sealed. The heat generated in the element is dissipated to the outside, and the electrode terminal that is electrically connected to the semiconductor element and connected to the external device is exposed to the outside from the side surface of the resin sealing portion.

このようなモジュールの複数個を近接して配置して、それぞれを電気的に接続して所望の回路を構成する製品の場合、隣接するモジュールの電極端子同士が接触しないように配置する必要がある。また、半導体素子が高電圧用の素子である場合、隣接するモジュールの電極端子同士が接触しないことはもちろんであるが、隣接する電極端子間の絶縁に必要な空間距離及び絶縁距離を確保する必要があり、製品の小型化を阻害していた。   In the case of a product in which a plurality of such modules are arranged close to each other and electrically connected to each other to form a desired circuit, the electrode terminals of adjacent modules need to be arranged so as not to contact each other. . In addition, when the semiconductor element is an element for high voltage, the electrode terminals of adjacent modules are not in contact with each other, but it is necessary to secure a spatial distance and an insulation distance necessary for insulation between adjacent electrode terminals. There was a hindrance to product miniaturization.

これに対し、特許文献3及び特許文献4に開示されるモジュールでは、半導体素子に電気的に接続された導体部材が、樹脂封止部の主面に露出した構成を有する。特許文献3及び特許文献4では、樹脂封止部の主面に露出した導体部材は、放熱に利用しているのみである。しかしながら、この導体部材を電極端子として活用することで、特許文献1及び特許文献2に示されるモジュールにおける問題点を改善することが可能となる。   In contrast, the modules disclosed in Patent Document 3 and Patent Document 4 have a configuration in which the conductor member electrically connected to the semiconductor element is exposed on the main surface of the resin sealing portion. In Patent Document 3 and Patent Document 4, the conductor member exposed on the main surface of the resin sealing portion is only used for heat dissipation. However, by utilizing this conductor member as an electrode terminal, it is possible to improve the problems in the modules disclosed in Patent Document 1 and Patent Document 2.

特許第4403665号公報Japanese Patent No. 4403665 特開2002−033445号公報Japanese Patent Laid-Open No. 2002-033445 特開2010−109000号公報JP 2010-109000 A 特許第3601432号公報Japanese Patent No. 3601432

特許文献3及び特許文献4に開示されるモジュールのように、半導体素子に電気的に接続された導体部材を樹脂封止部の主面に露出させるためには、モールド金型にて樹脂封止を行う際に、露出面になるべき導体部材の側面とモールド金型内面との間に、モールド樹脂が流れ込むような隙間が発生しないように、導体部材の側面とモールド金型内面とを密着させておく必要がある。   As in the modules disclosed in Patent Document 3 and Patent Document 4, in order to expose the conductor member electrically connected to the semiconductor element to the main surface of the resin sealing portion, resin sealing is performed with a mold. When conducting the process, make sure that the side surface of the conductor member and the inner surface of the mold die are in close contact with each other so that there is no gap between the side surface of the conductor member that should be the exposed surface and the inner surface of the mold die. It is necessary to keep.

しかしながら、導体部材と半導体素子とをはんだを介して積層した構造では、積層方向におけるモジュールの寸法をモールド金型の型締め寸法に一致させる精度にて、モジュールを製造することは非常に困難である、ということは容易に推察できる。   However, in the structure in which the conductor member and the semiconductor element are laminated via the solder, it is very difficult to manufacture the module with the accuracy of matching the module dimension in the lamination direction with the mold clamping dimension of the mold. It can be easily guessed.

また、導体部材及びはんだは、剛性の高い金属部材であり、また、半導体素子も含めて容易に変形できる形状ではない。よって、積層方向におけるモジュールの寸法と型締め寸法との不一致を、いずれかの部材の変形によって吸収させることは、やはり困難であると推察できる。   Further, the conductor member and the solder are highly rigid metal members and are not in a shape that can be easily deformed including the semiconductor element. Therefore, it can be inferred that it is still difficult to absorb the mismatch between the dimension of the module and the clamping dimension in the stacking direction by deformation of any member.

本発明は、このような問題点を解決するためになされたもので、電極となる導体部材がモジュールの主面に容易に露出可能となる構造を有する半導体装置を提供することを目的とする。   The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device having a structure in which a conductor member serving as an electrode can be easily exposed to the main surface of a module.

上記目的を達成するため、本発明は以下のように構成する。
即ち、本発明の一態様における半導体装置は、半導体チップと、この半導体チップの素子形成面に接合された第1導体部材と、上記素子形成面に対向する半導体チップの対向面に接合された第2導体部材と、上記半導体チップ、並びに、上記第1導体部材及び上記第2導体部材の一部を封止する封止部材と、を備え、上記第1導体部材及び上記第2導体部材は、上記半導体チップ、上記第1導体部材、及び上記第2導体部材を積層した積層方向において上記封止部材の各主面に露出する露出面を有する、半導体装置において、上記第1導体部材は、板状の部材であり、互いに屈曲して配置される接合部、変形部、及び自由端部を有し、接合部は、当該第1導体部材の一端側に位置し上記素子形成面と接合する部分であり、自由端部は、当該第1導体部材の他端側に位置し上記露出面を形成する部分であり、変形部は、接合部と自由端部との間に位置し、接合部に対して鈍角又は鋭角な角度で屈曲して配置され、かつ自由端部に対して鋭角な角度で屈曲して配置されることを特徴とする。
In order to achieve the above object, the present invention is configured as follows.
That is, a semiconductor device according to an aspect of the present invention includes a semiconductor chip, a first conductor member bonded to the element formation surface of the semiconductor chip, and a first surface bonded to the facing surface of the semiconductor chip facing the element formation surface. A two-conductor member, the semiconductor chip, and a sealing member that seals a part of the first conductor member and the second conductor member, the first conductor member and the second conductor member, In the semiconductor device having an exposed surface exposed to each main surface of the sealing member in a stacking direction in which the semiconductor chip, the first conductor member, and the second conductor member are stacked, the first conductor member is a plate. A member having a joint portion, a deformable portion, and a free end portion which are arranged to be bent with respect to each other, and the joint portion is located on one end side of the first conductor member and joined to the element formation surface And the free end is It is a part that is located on the other end side of the conductor member and forms the exposed surface, and the deformed part is located between the joined part and the free end part and bent at an obtuse or acute angle with respect to the joined part. It is arrange | positioned and it bends and arrange | positions at an acute angle with respect to a free end part, It is characterized by the above-mentioned.

本発明の一態様における半導体装置によれば、第1導体部材を構成する接合部、変形部、及び自由端部は互いに屈曲して配置され、接合部と自由端部との間に配置される変形部は、接合部に対して鈍角又は鋭角な角度で屈曲して配置され、かつ自由端部に対して鋭角な角度で屈曲して配置した。このように構成したことで、モールド金型にて積層方向に型締めされるとき、固定されている接合部に対して変形部が変位し、これに伴い自由端部は、反半導体チップ側へ移動しようとする。したがって、自由端部は、常にモールド金型に密接した状態を維持することができる。よって、第1導体部材及び第2導体部材の各露出面となる側面は、常にモールド金型に密接することから、半導体装置における封止部材の主面に第1導体部材及び第2導体部材を容易に露出させることが可能となる。   According to the semiconductor device of one aspect of the present invention, the joint portion, the deformable portion, and the free end portion that constitute the first conductor member are arranged to be bent with respect to each other, and are arranged between the joint portion and the free end portion. The deformed portion was bent and arranged at an obtuse or acute angle with respect to the joint portion, and was bent and arranged at an acute angle with respect to the free end portion. With this configuration, when the mold is clamped in the stacking direction, the deformed portion is displaced with respect to the fixed joint portion, and the free end portion moves toward the anti-semiconductor chip side. Try to move. Therefore, the free end can always maintain a close state to the mold. Therefore, since the exposed side surfaces of the first conductor member and the second conductor member are always in close contact with the mold, the first conductor member and the second conductor member are placed on the main surface of the sealing member in the semiconductor device. It can be easily exposed.

本発明の実施の形態1における半導体装置の構造を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention. 図1に示す半導体装置の製造方法を示す工程図である。FIG. 3 is a process diagram illustrating a method for manufacturing the semiconductor device shown in FIG. 1. 図1に示す半導体装置の変形例における構造を示す概略断面図である。FIG. 7 is a schematic cross-sectional view showing a structure in a modified example of the semiconductor device shown in FIG. 1. 図3に示す半導体装置で形成可能な回路構成例を示す回路図である。FIG. 4 is a circuit diagram showing a circuit configuration example that can be formed by the semiconductor device shown in FIG. 3. 図1に示す半導体装置の他の変形例における構造を示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing a structure in another modification of the semiconductor device shown in FIG. 1. 本発明の実施の形態2における半導体装置の構造を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 2 of this invention. 図6に示す第1導体部材による効果を説明するための図である。It is a figure for demonstrating the effect by the 1st conductor member shown in FIG.

本発明の実施形態である半導体装置について、図を参照しながら以下に説明する。尚、各図において、同一又は同様の構成部分については同じ符号を付している。   A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals.

実施の形態1.
図1及び図2を参照して、本発明の実施の形態1における半導体装置100について説明する。図1は、半導体装置100の概略断面図である。半導体装置100は、基本的構成部分として、半導体チップ1、第1導体部材3、第2導体部材5、及び封止部材9を備える。
Embodiment 1 FIG.
A semiconductor device 100 according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view of the semiconductor device 100. The semiconductor device 100 includes a semiconductor chip 1, a first conductor member 3, a second conductor member 5, and a sealing member 9 as basic components.

半導体チップ1は、本実施形態では、主としてSi又はSiCからなる、厚み0.1〜0.2mm程度の半導体チップであり、エミッタ電極が形成された素子形成面1aと、この素子形成面1aに対向する面でコレクタ電極が形成された裏面1bとを有する。   In this embodiment, the semiconductor chip 1 is a semiconductor chip mainly made of Si or SiC and having a thickness of about 0.1 to 0.2 mm. The element formation surface 1a on which the emitter electrode is formed, and the element formation surface 1a And a back surface 1b having a collector electrode formed on the opposing surface.

第1導体部材3は、電極となる帯状の板材にてなる導電性の部材であり、その延在方向において接合部31、変形部33、及び自由端部32から構成され、接合部31、変形部33、及び自由端部32は、以下に説明する角度関係で互いに屈曲して配置される。   The first conductor member 3 is a conductive member made of a strip-shaped plate material that serves as an electrode, and includes a joining portion 31, a deforming portion 33, and a free end portion 32 in the extending direction thereof. The portion 33 and the free end portion 32 are arranged so as to be bent with respect to each other in the angular relationship described below.

即ち、接合部31は、第1導体部材3の一端側に位置し半導体チップ1の素子形成面1aに平行又はほぼ平行に延在する部分であり、電気伝導性を有する接合部材(第1の接合部材)の一例としてのはんだ4で、素子形成面1aのエミッタ電極に接合される部分である。
自由端部32は、第1導体部材3の他端側に位置する部分であり、固定された接合部31に対して自由端となる。また、自由端部32は、露出面3aを形成する。
That is, the joint portion 31 is a portion located on one end side of the first conductor member 3 and extending in parallel or substantially parallel to the element formation surface 1a of the semiconductor chip 1, and is a joint member (first member) having electrical conductivity. The solder 4 as an example of the bonding member) is a portion bonded to the emitter electrode of the element forming surface 1a.
The free end portion 32 is a portion located on the other end side of the first conductor member 3 and is a free end with respect to the fixed joint portion 31. Further, the free end portion 32 forms an exposed surface 3a.

変形部33は、接合部31と自由端部32との間に位置し、接合部31に対して本実施形態では鈍角な角度θ1で屈曲して配置され、かつ自由端部32に対して鋭角な角度θ2で屈曲して配置される。このような変形部33を介して、接合部31と自由端部32とは、ほぼ平行に配置され、第1導体部材3は、図示するように変形したコ字形形状となる。   The deformable portion 33 is located between the joint portion 31 and the free end portion 32, is bent with respect to the joint portion 31 at an obtuse angle θ <b> 1 in the present embodiment, and is acute with respect to the free end portion 32. It is bent at a certain angle θ2. The joint portion 31 and the free end portion 32 are disposed substantially in parallel via the deformable portion 33, and the first conductor member 3 has a U-shape deformed as illustrated.

また、半導体チップ1の素子形成面1aには、ガードリング等の、エミッタ電極と同電位にすると不具合を生じる部位が存在し、この部位が第1導体部材3と接触すると第1導体部材3を介してエミッタ電極と同電位になってしまう。従って、第1導体部材3の接合部31は、半導体チップ1のエミッタ電極のみと接合する構成としている。   Further, the element forming surface 1a of the semiconductor chip 1 has a part such as a guard ring that causes a malfunction when the potential is the same as that of the emitter electrode. When this part comes into contact with the first conductor member 3, the first conductor member 3 is attached. The same potential as the emitter electrode. Therefore, the joint portion 31 of the first conductor member 3 is configured to be joined only to the emitter electrode of the semiconductor chip 1.

第2導体部材5は、電極となるブロック状の導電性部材であり、半導体チップ1の裏面1bにおけるコレクタ電極と、第2の接合部材の一例であるはんだ4を介して電気的に接続される。尚、第2導体部材5において、コレクタ電極と接続された面に対向する面が露出面5aとなる。
また、第1導体部材3及び第2導体部材5として、本実施形態ではCu又はCu合金を用いている。
The second conductor member 5 is a block-like conductive member that serves as an electrode, and is electrically connected to the collector electrode on the back surface 1b of the semiconductor chip 1 via a solder 4 that is an example of a second bonding member. . In the second conductor member 5, the surface facing the surface connected to the collector electrode is the exposed surface 5a.
In the present embodiment, Cu or Cu alloy is used as the first conductor member 3 and the second conductor member 5.

封止部材9は、例えばエポキシ系モールド樹脂を用いることができ、後述のモールド金型内へ注入され、半導体チップ1、露出面3aを除いた第1導体部材3、及び露出面5aを除いた第2導体部材5、さらに、図示を省略しているが、ボンディングワイヤ、制御用端子の一部も含めて、一括してこれらを封止する。半導体チップ1等を封止した封止部材9において、対向する2つの主面9a、9bには、第1導体部材3の露出面3aが、及び第2導体部材5の露出面5aがそれぞれ露出する。   For example, an epoxy mold resin can be used for the sealing member 9. The sealing member 9 is injected into a mold described later, and the semiconductor chip 1, the first conductor member 3 excluding the exposed surface 3 a, and the exposed surface 5 a are excluded. Although not shown, the second conductor member 5 and the bonding wires and part of the control terminals are collectively sealed. In the sealing member 9 that seals the semiconductor chip 1 and the like, the exposed surface 3a of the first conductor member 3 and the exposed surface 5a of the second conductor member 5 are exposed on the two opposing main surfaces 9a and 9b, respectively. To do.

このようにして、本実施形態の半導体装置100が構成される。この半導体装置100では、半導体チップ1からの発熱を熱伝導性にも優れたはんだ4を介して主に第2導体部材5に伝え、第2導体部材5の露出面5aから放熱を行うことができるようになっている。   In this way, the semiconductor device 100 of this embodiment is configured. In this semiconductor device 100, heat generated from the semiconductor chip 1 is mainly transmitted to the second conductor member 5 through the solder 4 having excellent thermal conductivity, and heat is radiated from the exposed surface 5a of the second conductor member 5. It can be done.

また、第2導体部材5の露出面5aに冷却部材等を当接させて、更に放熱を促すようにすることもできる。また、第1及び第2の導体部材3、5は、半導体チップ1との電気的な経路となっている。つまり、第2導体部材5を介して半導体チップ1のコレクタ電極との導通を図り、第1導体部材3を介して半導体チップ1のエミッタ電極との導通を図るようになっている。   In addition, a cooling member or the like may be brought into contact with the exposed surface 5a of the second conductor member 5 to further promote heat dissipation. Further, the first and second conductor members 3 and 5 are electrical paths to the semiconductor chip 1. That is, conduction with the collector electrode of the semiconductor chip 1 is achieved via the second conductor member 5, and conduction with the emitter electrode of the semiconductor chip 1 is achieved via the first conductor member 3.

次に、上述した半導体装置100の製造方法について、図2を参照して説明する。
まず、半導体チップ1の素子形成面1aに平行又はほぼ平行に第1導体部材3の接合部31を配置し、かつ素子形成面1aのエミッタ電極に接合部31を板状のはんだ4を挟んで配置する。さらに、半導体チップ1の裏面1bのコレクタ電極に板状のはんだ4を挟み第2導体部材5を配置する。このように、半導体チップ1、第1導体部材3、及び第2導体部材5を積層して配置した状態で、これらを還元雰囲気中で一括加熱することによりはんだ4を溶融させ、その後、冷却することで、半導体チップ1に第1導体部材3及び第2導体部材5が接合された半製品を作製する。
Next, a method for manufacturing the semiconductor device 100 described above will be described with reference to FIG.
First, the joint portion 31 of the first conductor member 3 is arranged in parallel or substantially parallel to the element formation surface 1a of the semiconductor chip 1, and the joint portion 31 is sandwiched between the plate-like solder 4 and the emitter electrode of the element formation surface 1a. Deploy. Further, the second conductor member 5 is disposed with the plate-like solder 4 sandwiched between the collector electrodes on the back surface 1 b of the semiconductor chip 1. Thus, in a state where the semiconductor chip 1, the first conductor member 3, and the second conductor member 5 are stacked and arranged, the solder 4 is melted by collectively heating them in a reducing atmosphere, and then cooled. Thus, a semi-finished product in which the first conductor member 3 and the second conductor member 5 are joined to the semiconductor chip 1 is manufactured.

次に、上述の半製品を、図2の(a)に示すように、モールド金型11を開いた状態で、下モールド金型11bの内面に第2導体部材5の露出面5aを接した状態で配置する。 次に、型開閉方向12に沿ってモールド金型11を閉じていくと、図2の(b)に示すように、上モールド金型11aの内面が第1導体部材3の自由端部32の露出面3aに接触する。この時点ではモールド金型11は、完全には閉じておらず、わずかに隙間がある状態になっている。   Next, as shown in FIG. 2A, the above-mentioned semi-finished product is brought into contact with the exposed surface 5a of the second conductor member 5 on the inner surface of the lower mold 11b with the mold 11 opened. Arrange in a state. Next, when the mold 11 is closed along the mold opening / closing direction 12, the inner surface of the upper mold 11a is connected to the free end 32 of the first conductor member 3 as shown in FIG. It contacts the exposed surface 3a. At this time, the mold 11 is not completely closed and is slightly in the state of a gap.

さらにモールド金型11を閉じていくと、上モールド金型11aが自由端部32の露出面3aを押圧する。これにより第1導体部材3の変形部33は、片持ち梁のように撓んで変形し、変形部33の上端33aが半導体チップ1へ近づく方向に変位する。この際、変形部33と自由端部32とのなす角度θ2が変化しなければ、自由端部32は、半導体チップ1から離れる例えば矢印Aで示すような方向に変位するはずである。しかし実際には、矢印A方向には上モールド金型11aが存在することから、自由端部32は変位できない。この結果、自由端部32における露出面3aは,その全面にわたって上モールド金型11aの内壁面へ押圧されることになる。   When the mold 11 is further closed, the upper mold 11a presses the exposed surface 3a of the free end 32. As a result, the deformed portion 33 of the first conductor member 3 is bent and deformed like a cantilever, and the upper end 33 a of the deformed portion 33 is displaced in a direction approaching the semiconductor chip 1. At this time, if the angle θ2 formed by the deformed portion 33 and the free end portion 32 does not change, the free end portion 32 should be displaced in the direction as indicated by the arrow A, for example, away from the semiconductor chip 1. However, in practice, since the upper mold 11a exists in the direction of arrow A, the free end 32 cannot be displaced. As a result, the exposed surface 3a in the free end portion 32 is pressed against the inner wall surface of the upper mold 11a over the entire surface.

したがって、図2の(c)に示すように、モールド金型11が完全に閉じたときには、第1導体部材3の変形部33の反発力により、第1導体部材3の露出面3a、及び第2導体部材5の露出面5aは、それぞれ上モールド金型11a及び下モールド金型11bの各内壁面へ押圧され密接する。   Therefore, as shown in FIG. 2C, when the mold 11 is completely closed, the repulsive force of the deformed portion 33 of the first conductor member 3 causes the exposed surface 3a of the first conductor member 3 and the first The exposed surface 5a of the two-conductor member 5 is pressed and brought into close contact with the inner wall surfaces of the upper mold 11a and the lower mold 11b.

このような状態において、モールド金型11内に封止部材9を注入することで、第1導体部材3の露出面3aと上モールド金型11aの内壁面との間に、及び、第2導体部材5の露出面5aと下モールド金型11bの内壁面との間に封止部材9が入り込むことはない。よって、第1導体部材3の露出面3a及び第2導体部材5の露出面5aが露出する状態で、半導体チップ1等の各部材が封止部材9により封止され、半導体装置100が完成する。   In such a state, by injecting the sealing member 9 into the mold die 11, the second conductor is provided between the exposed surface 3a of the first conductor member 3 and the inner wall surface of the upper mold die 11a. The sealing member 9 does not enter between the exposed surface 5a of the member 5 and the inner wall surface of the lower mold die 11b. Therefore, each member such as the semiconductor chip 1 is sealed by the sealing member 9 with the exposed surface 3a of the first conductor member 3 and the exposed surface 5a of the second conductor member 5 exposed, and the semiconductor device 100 is completed. .

このように、本実施の形態1の半導体装置100では、第1導体部材3が、半導体チップ1の素子形成面1aにはんだ4を介して接合される接合部31と、封止部材9の外部に露出する露出面3aを有し固定された接合部31に対して自由端となる自由端部32と、接合部31の一方の端部及び自由端部32の一方の端部を中継するとともに外力によって変形可能な変形部33とを有する。さらに、変形部33の上端33aが半導体チップ1に近づく方向へ変位するときには、自由端部32における他方の端部32aが半導体チップ1から離れる例えば矢印Aで示すような方向に変位するように構成した。つまり変形部33は、接合部31に対して本実施形態では鈍角な角度θ1で屈曲して配置され、かつ自由端部32に対して鋭角な角度θ2で屈曲して配置されるように構成した。   As described above, in the semiconductor device 100 according to the first embodiment, the first conductor member 3 is joined to the element forming surface 1a of the semiconductor chip 1 via the solder 4 and the outside of the sealing member 9. And relaying a free end 32 which is a free end with respect to the fixed joint 31 having the exposed surface 3a exposed to the surface, one end of the joint 31 and one end of the free end 32. And a deformable portion 33 that can be deformed by an external force. Further, when the upper end 33a of the deformable portion 33 is displaced in a direction approaching the semiconductor chip 1, the other end portion 32a of the free end portion 32 is displaced away from the semiconductor chip 1, for example, in a direction indicated by an arrow A. did. That is, the deformable portion 33 is configured to be bent at an obtuse angle θ1 in the present embodiment with respect to the joint portion 31 and bend at an acute angle θ2 with respect to the free end portion 32. .

このように構成したことで、半導体チップ1、第1導体部材3、第2導体部材5をはんだ4で接合した状態の上記半製品について、モールド金型11の型開閉方向12、つまり上記半製品の積層方向における寸法のバラツキを吸収し、かつ、半導体チップ1の損傷及び破壊、並びに、第1導体部材3の露出面3a及び第2導体部材5の露出面5aが封止部材9に覆われることを抑制しつつ、低コストで品質の安定した生産が可能となる。   With such a configuration, with respect to the semi-finished product in which the semiconductor chip 1, the first conductor member 3, and the second conductor member 5 are joined with the solder 4, the mold opening / closing direction 12 of the mold 11, that is, the semi-finished product. The dimension variation in the stacking direction is absorbed, the semiconductor chip 1 is damaged and destroyed, and the exposed surface 3a of the first conductor member 3 and the exposed surface 5a of the second conductor member 5 are covered with the sealing member 9. This makes it possible to produce products with stable quality at low cost.

尚、本実施の形態1では、半導体チップ1が1個だけの場合について説明したが、半導体装置100内に複数個の半導体チップ1が設けられてもよい。この場合、半導体チップ1毎に、第1導体部材3及び第2導体部材5を配置してもよいし、さらに、図3に示すように、第1導体部材3及び第2導体部材5が、複数個あるいは複数種類の半導体チップ1を連結する形で接合されていてもよい。   In the first embodiment, the case where only one semiconductor chip 1 is provided has been described. However, a plurality of semiconductor chips 1 may be provided in the semiconductor device 100. In this case, the first conductor member 3 and the second conductor member 5 may be arranged for each semiconductor chip 1, and further, as shown in FIG. 3, the first conductor member 3 and the second conductor member 5 are A plurality or a plurality of types of semiconductor chips 1 may be joined together.

このような構成とすることで、複数個の半導体チップ1を使用する場合でも、部品点数の増加を最小限に抑制できる。また、2種類の半導体チップ1を用いる場合で、半導体チップ1としてIGBTを、半導体チップ2としてFWDを適用すると、図4に示すようなインバータ回路20の一部を構成するIGBTとFWDの逆並列回路21を容易に構成することが可能となる。   With such a configuration, even when a plurality of semiconductor chips 1 are used, an increase in the number of components can be suppressed to a minimum. Further, when two types of semiconductor chips 1 are used and an IGBT is applied as the semiconductor chip 1 and an FWD is applied as the semiconductor chip 2, the IGBT and FWD that constitute a part of the inverter circuit 20 as shown in FIG. The circuit 21 can be easily configured.

また、IGBTとFWDとでは、その素子構成が異なり、一般的にIGBTの方が外力に対する破壊耐量が低い。上述のようなモールド金型11による樹脂封止の際に、第1導体部材3が変形するときには、変形部33に近接する半導体チップ1にも変形の力が作用する。したがって、図3に示す構成を採る場合には、変形部33に近接する半導体チップ1をFWDとし、変形部33から比較的遠い半導体チップ2をIGBTとして構成することが望ましい。   Moreover, the element structure differs between IGBT and FWD, and generally IGBT has lower breakdown resistance against external force. When the first conductor member 3 is deformed during resin sealing with the molding die 11 as described above, a deformation force acts on the semiconductor chip 1 adjacent to the deformed portion 33. Therefore, when the configuration shown in FIG. 3 is adopted, it is desirable to configure the semiconductor chip 1 close to the deforming portion 33 as FWD and the semiconductor chip 2 relatively far from the deforming portion 33 as IGBT.

また、第1導体部材3及び第2導体部材5と、封止部材9とが剥離すると、その剥離界面から水分等が浸入し腐食等により半導体装置100の信頼性が維持できないという問題が生じることもある。よって、第1導体部材3及び第2導体部材5と、封止部材9との密着性を向上させるために、第1導体部材3及び第2導体部材5の表面を粗化してもよい。   Further, when the first conductor member 3 and the second conductor member 5 and the sealing member 9 are separated, there is a problem that the reliability of the semiconductor device 100 cannot be maintained due to corrosion or the like due to moisture entering from the separation interface. There is also. Therefore, in order to improve the adhesion between the first conductor member 3 and the second conductor member 5 and the sealing member 9, the surfaces of the first conductor member 3 and the second conductor member 5 may be roughened.

また、自由端部32の露出面3aに外部配線を接続する手法として、はんだ接合又は超音波接合を採ることができるが、超音波接合を行う場合には、接合面は平滑であることが望ましい。したがって、上述のように第1導体部材3の表面は粗面化するのが好ましいが、第1導体部材3への配線接続方法として超音波接合を用いる場合には、自由端部32の少なくとも露出面3aは、粗面化しないのが好ましい。このように構成することで、半導体装置100の信頼性、及び超音波接合の安定性の両者を確保することが可能となる。   Further, as a method for connecting the external wiring to the exposed surface 3a of the free end portion 32, solder bonding or ultrasonic bonding can be employed. However, when ultrasonic bonding is performed, the bonding surface is preferably smooth. . Therefore, it is preferable that the surface of the first conductor member 3 is roughened as described above. However, when ultrasonic bonding is used as a wiring connection method to the first conductor member 3, at least the free end portion 32 is exposed. The surface 3a is preferably not roughened. With this configuration, it is possible to ensure both the reliability of the semiconductor device 100 and the stability of ultrasonic bonding.

また、第1導体部材3への配線接続方法として超音波接合を用いる場合、自由端部32には超音波振動が印加されることから、上記粗面化を行ったとしても、自由端部32と封止部材9との界面の剥離が助長されることも懸念される。よってこのような弊害の発生を防止するため、図5に示すように、半導体チップ1側へ凸とした突起32bを第1導体部材3に形成してもよい。図5では、突起32bの形成例として、第1導体部材3の他方の端部32aを半導体チップ1側へ折り曲げることで突起32bを形成した構成を図示している。このような突起32bを第1導体部材3に設けることで、封止部材9によるアンカー効果により、自由端部32と封止部材9との界面剥離を抑制することができる。   Further, when ultrasonic bonding is used as a wiring connection method to the first conductor member 3, since the ultrasonic vibration is applied to the free end portion 32, the free end portion 32 is provided even if the roughening is performed. There is also concern that peeling of the interface between the sealing member 9 and the sealing member 9 is promoted. Therefore, in order to prevent the occurrence of such an adverse effect, a protrusion 32b that protrudes toward the semiconductor chip 1 may be formed on the first conductor member 3 as shown in FIG. FIG. 5 illustrates a configuration in which the protrusion 32b is formed by bending the other end 32a of the first conductor member 3 toward the semiconductor chip 1 as an example of forming the protrusion 32b. By providing such a protrusion 32 b on the first conductor member 3, the interface peeling between the free end 32 and the sealing member 9 can be suppressed due to the anchor effect of the sealing member 9.

実施の形態2.
実施の形態1では、第1導体部材3は、図1に示すようなコ字の変形形状として説明した。しかしながら、第1導体部材3は、このような形状に限定されず、例えば図6に示すような、Z形状の第1導体部材3−2であっても、上述と同様の効果が得られることは容易に推察できる。
即ち、実施の形態2における半導体装置102でも、第1導体部材3−2が上モールド金型11aによって押圧され、変形する。その際に、自由端部32が上モールド金型11aに押し付けられるように、第1導体部材3−2は構成されていればよい。
Embodiment 2. FIG.
In Embodiment 1, the 1st conductor member 3 demonstrated as a U-shaped deformation | transformation shape as shown in FIG. However, the first conductor member 3 is not limited to such a shape. For example, even if it is a Z-shaped first conductor member 3-2 as shown in FIG. Can be easily guessed.
That is, also in the semiconductor device 102 in the second embodiment, the first conductor member 3-2 is pressed by the upper mold 11a and deformed. In that case, the 1st conductor member 3-2 should just be comprised so that the free end part 32 may be pressed on the upper mold 11a.

第1導体部材が、例えば図6に示すような形状を有する場合、つまり変形部33が接合部31に対して鈍角で屈曲し、自由端部32に対しても鈍角で屈曲して配置される構成では、モールド金型11の型締めによって変形部33が変位すると、自由端部32は、点線で示すように、上モールド金型11aから離れる方向に変位する。よって、第1導体部材が図6に示す形状を有する場合には、上述した効果が得られないことは明白である。   For example, when the first conductor member has a shape as shown in FIG. 6, that is, the deformed portion 33 is bent at an obtuse angle with respect to the joint portion 31 and is also bent at an obtuse angle with respect to the free end portion 32. In the configuration, when the deformation portion 33 is displaced by clamping the mold 11, the free end portion 32 is displaced in a direction away from the upper mold 11 a as indicated by a dotted line. Therefore, when the first conductor member has the shape shown in FIG. 6, it is obvious that the above-described effect cannot be obtained.

よって、第1導体部材3−2が上モールド金型11aによって押圧され変形する際に、自由端部32が上モールド金型11aに押し付けられるように、第1導体部材3−2では、変形部33は、上記角度θ1に対応する、接合部31に対して本実施形態2では鋭角な角度θ3で屈曲して配置され、かつ自由端部32に対して鋭角な角度θ2で屈曲して配置されるように構成した。   Therefore, when the first conductor member 3-2 is pressed and deformed by the upper mold 11a, the first conductor member 3-2 has a deformed portion so that the free end 32 is pressed against the upper mold 11a. In the second embodiment, 33 is bent at an acute angle θ3 and is bent at an acute angle θ2 with respect to the free end 32, corresponding to the angle θ1. It was configured as follows.

このように、実施の形態1、2から、第1導体部材における変形部33は、接合部31に対して鈍角又は鋭角な角度で屈曲して配置され、かつ自由端部32に対して鋭角な角度で屈曲して配置されるように構成することで、第1導体部材が上モールド金型11aによって押圧、変形される際に、自由端部32が上モールド金型11aに押し付け可能となる。   As described above, from the first and second embodiments, the deformed portion 33 of the first conductor member is bent and arranged at an obtuse or acute angle with respect to the joint portion 31 and is acute with respect to the free end portion 32. By being configured to be bent at an angle, the free end portion 32 can be pressed against the upper mold 11a when the first conductor member is pressed and deformed by the upper mold 11a.

尚、実施の形態1にて説明した、半導体装置100に対する種々の変形形態は、本実施の形態2の半導体装置102に対しても適用可能である。   Various modifications to the semiconductor device 100 described in the first embodiment can also be applied to the semiconductor device 102 of the second embodiment.

1 半導体チップ、1a 素子形成面、3 第1導体部材、3a 露出面、
5 第2導体部材、5a 露出面、9 封止部材、
11a 上モールド金型、11b 下モールド金型、
31 接合部、32 自由端部、33 変形部、
100、102 半導体装置。
DESCRIPTION OF SYMBOLS 1 Semiconductor chip, 1a Element formation surface, 1st conductor member, 3a Exposed surface,
5 Second conductor member, 5a Exposed surface, 9 Sealing member,
11a Upper mold die, 11b Lower mold die,
31 joint part, 32 free end part, 33 deformation part,
100, 102 Semiconductor device.

Claims (4)

半導体チップと、
この半導体チップの素子形成面に接合された第1導体部材と、
上記素子形成面に対向する半導体チップの対向面に接合された第2導体部材と、
上記半導体チップ、並びに、上記第1導体部材及び上記第2導体部材の一部を封止する封止部材と、を備え、
上記第1導体部材及び上記第2導体部材は、上記半導体チップ、上記第1導体部材、及び上記第2導体部材を積層した積層方向において上記封止部材の各主面に露出する露出面を有する、半導体装置において、
上記第1導体部材は、板状の部材であり、互いに屈曲して配置される接合部、変形部、及び自由端部を有し、接合部は、当該第1導体部材の一端側に位置し上記素子形成面と接合する部分であり、自由端部は、当該第1導体部材の他端側に位置し上記露出面を形成する部分であり、変形部は、接合部と自由端部との間に位置し、接合部に対して鈍角又は鋭角な角度で屈曲して配置され、かつ自由端部に対して鋭角な角度で屈曲して配置される、
ことを特徴とする半導体装置。
A semiconductor chip;
A first conductor member bonded to the element forming surface of the semiconductor chip;
A second conductor member bonded to the facing surface of the semiconductor chip facing the element forming surface;
A sealing member that seals a part of the semiconductor chip and the first conductor member and the second conductor member;
The first conductor member and the second conductor member have exposed surfaces exposed to the respective principal surfaces of the sealing member in the stacking direction in which the semiconductor chip, the first conductor member, and the second conductor member are stacked. In semiconductor devices,
The first conductor member is a plate-like member, and has a joint portion, a deformation portion, and a free end portion that are arranged to be bent with respect to each other, and the joint portion is located on one end side of the first conductor member. The portion that is joined to the element forming surface, the free end is a portion that is located on the other end side of the first conductor member and forms the exposed surface, and the deformed portion is a portion between the joined portion and the free end. Located between, bent and arranged at an obtuse or acute angle with respect to the joint, and arranged at an acute angle with respect to the free end,
A semiconductor device.
上記半導体チップは複数個設けられ、上記第1導体部材及び上記第2導体部材は、少なくとも2つの半導体チップを連結して接合される、請求項1記載の半導体装置。   The semiconductor device according to claim 1, wherein a plurality of the semiconductor chips are provided, and the first conductor member and the second conductor member are joined by connecting at least two semiconductor chips. 上記封止部材と接する上記第1導体部材及び上記第2導体部材の表面は、粗化された粗面である、請求項1又は2記載の半導体装置。   3. The semiconductor device according to claim 1, wherein surfaces of the first conductor member and the second conductor member in contact with the sealing member are roughened rough surfaces. 上記第1導体部材の自由端部は、半導体チップ側へ凸となる突起を有する、請求項1から3のいずれか1項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the free end portion of the first conductor member has a protrusion that protrudes toward the semiconductor chip. 5.
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WO2018020729A1 (en) 2016-07-27 2018-02-01 株式会社日立製作所 Semiconductor module and method for manufacturing semiconductor module
WO2020110170A1 (en) * 2018-11-26 2020-06-04 三菱電機株式会社 Semiconductor package and production method therefor, and semiconductor device
JP2022027946A (en) * 2018-11-26 2022-02-14 三菱電機株式会社 Semiconductor package and semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018020729A1 (en) 2016-07-27 2018-02-01 株式会社日立製作所 Semiconductor module and method for manufacturing semiconductor module
US10937731B2 (en) 2016-07-27 2021-03-02 Hitachi, Ltd. Semiconductor module and method for manufacturing semiconductor module
WO2020110170A1 (en) * 2018-11-26 2020-06-04 三菱電機株式会社 Semiconductor package and production method therefor, and semiconductor device
JPWO2020110170A1 (en) * 2018-11-26 2021-05-13 三菱電機株式会社 Semiconductor packages, their manufacturing methods, and semiconductor devices
JP6997340B2 (en) 2018-11-26 2022-01-17 三菱電機株式会社 Semiconductor packages, their manufacturing methods, and semiconductor devices
JP2022027946A (en) * 2018-11-26 2022-02-14 三菱電機株式会社 Semiconductor package and semiconductor device
JP7254156B2 (en) 2018-11-26 2023-04-07 三菱電機株式会社 Semiconductor package and semiconductor device

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