JP2012142466A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2012142466A
JP2012142466A JP2011000061A JP2011000061A JP2012142466A JP 2012142466 A JP2012142466 A JP 2012142466A JP 2011000061 A JP2011000061 A JP 2011000061A JP 2011000061 A JP2011000061 A JP 2011000061A JP 2012142466 A JP2012142466 A JP 2012142466A
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conductor member
semiconductor chip
semiconductor
conductor
mold
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Susumu Kimura
享 木村
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/331—Disposition
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    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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    • H01L2224/37001—Core members of the connector
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    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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  • Engineering & Computer Science (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure which allows conductor members serving as electrodes to be easily exposed on a main surface of a semiconductor module.SOLUTION: A semiconductor device is manufactured by respectively soldering a first conductor member 3 and a second conductor member 5 to an element formation surface 1a and a back surface 1b of a semiconductor chip 1 and resin-sealing the first conductor member and the second conductor member with a sealing member 9. The first conductor member has a spring structure 3c which expands and contracts in a lamination direction 51 of the semiconductor chip and the like.

Description

本発明は、半導体装置に関し、詳しくは、半導体チップの両面が導体部材と電気的に接続された構成を有する半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a configuration in which both surfaces of a semiconductor chip are electrically connected to a conductor member.

従来の樹脂モールド型半導体モジュール（以下、モジュールと記す）は、特許文献１及び特許文献２に示されるように、半導体素子を封止した樹脂封止部の２つの主面のいずれか一方から半導体素子で発生する熱を外部に放熱し、また、半導体素子と電気的に接続されかつ外部機器と接続される電極端子が樹脂封止部の側面から外部へ露出する構成を有する。   As shown in Patent Document 1 and Patent Document 2, a conventional resin mold type semiconductor module (hereinafter referred to as a module) is a semiconductor from either one of two main surfaces of a resin sealing portion in which a semiconductor element is sealed. The heat generated in the element is dissipated to the outside, and the electrode terminal that is electrically connected to the semiconductor element and connected to the external device is exposed to the outside from the side surface of the resin sealing portion.

このようなモジュールでは、複数のモジュールを近接して配置して、それぞれを電気的に接続して所望の回路を構成する製品の場合、隣接するモジュールの電極端子同士が接触しないように配置する必要がある。また、半導体素子が高電圧用の素子である場合、隣接するモジュールの電極端子同士が接触しないことはもちろんであるが、隣接する電極端子間の絶縁に必要な空間距離及び絶縁距離を確保する必要があり、製品の小型化を阻害していた。   In such a module, in the case of a product in which a plurality of modules are arranged close to each other and electrically connected to each other to form a desired circuit, it is necessary to arrange so that the electrode terminals of adjacent modules do not contact each other. There is. In addition, when the semiconductor element is an element for high voltage, the electrode terminals of adjacent modules are not in contact with each other, but it is necessary to secure a spatial distance and an insulation distance necessary for insulation between adjacent electrode terminals. There was a hindrance to product miniaturization.

これに対し、特許文献３及び特許文献４に開示されるモジュールでは、半導体素子に電気的に接続された導体部材が、樹脂封止部の主面に露出した構成を有する。特許文献３及び特許文献４では、樹脂封止部の主面に露出した導体部材は、放熱に利用しているのみであるが、電極端子として活用することで、特許文献１及び特許文献２に示されるモジュールにおける問題点を改善することが可能となる。   In contrast, the modules disclosed in Patent Document 3 and Patent Document 4 have a configuration in which the conductor member electrically connected to the semiconductor element is exposed on the main surface of the resin sealing portion. In patent document 3 and patent document 4, although the conductor member exposed to the main surface of the resin sealing part is only utilized for heat dissipation, patent document 1 and patent document 2 are utilized by utilizing as an electrode terminal. It is possible to improve the problems in the modules shown.

特許第４４０３６６５号公報Japanese Patent No. 4403665 特開２００２−０３３４４５号公報Japanese Patent Laid-Open No. 2002-033445 特開２０１０−１０９０００号公報JP 2010-109000 A 特許第３６０１４３２号公報Japanese Patent No. 3601432

特許文献３及び特許文献４に開示されるモジュールのように、半導体素子に電気的に接続された導体部材を樹脂封止部の主面に露出させるためには、モールド金型にて樹脂封止を行う際に、露出面となるべき導体部材の側面とモールド金型内面との間に、モールド樹脂が流れ込むような隙間が発生しないように、導体部材の側面とモールド金型内面とを密着させておく必要がある。   As in the modules disclosed in Patent Document 3 and Patent Document 4, in order to expose the conductor member electrically connected to the semiconductor element to the main surface of the resin sealing portion, resin sealing is performed with a mold. When conducting the process, make sure that the side surface of the conductor member and the inner surface of the mold die are in close contact with each other so that there is no gap between the side surface of the conductive member that should be the exposed surface and the inner surface of the mold die. It is necessary to keep.

しかしながら、導体部材と半導体素子とをはんだを介して積層した構造では、積層方向におけるモジュールの寸法をモールド金型の型締め寸法に一致させる精度にて、モジュールを製造することは非常に困難である、ということは容易に推察できる。   However, in the structure in which the conductor member and the semiconductor element are laminated via the solder, it is very difficult to manufacture the module with the accuracy of matching the module dimension in the lamination direction with the mold clamping dimension of the mold. It can be easily guessed.

また、導体部材及びはんだは、剛性の高い金属部材であり、また、半導体素子も含めて容易に変形できる形状ではない。よって、積層方向におけるモジュールの寸法と型締め寸法との不一致を、いずれかの部材の変形によって吸収させることは、やはり困難であると推察できる。   Further, the conductor member and the solder are highly rigid metal members and are not in a shape that can be easily deformed including the semiconductor element. Therefore, it can be inferred that it is still difficult to absorb the mismatch between the dimension of the module and the clamping dimension in the stacking direction by deformation of any member.

本発明は、このような問題点を解決するためになされたもので、電極となる導体部材がモジュールの主面に容易に露出可能となる構造を有する半導体装置を提供することを目的とする。   The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device having a structure in which a conductor member serving as an electrode can be easily exposed to the main surface of a module.

上記目的を達成するため、本発明は以下のように構成する。
即ち、本発明の一態様における半導体装置は、半導体チップと、上記半導体チップの素子形成面に接合された第１導体部材と、上記素子形成面に対向する半導体チップの対向面に接合された第２導体部材と、上記半導体チップ、並びに、上記第１導体部材及び上記第２導体部材の一部を封止する封止部材と、を備え、上記第１導体部材及び上記第２導体部材は、上記半導体チップ、上記第１導体部材、及び上記第２導体部材を積層した積層方向において上記封止部材の各主面に露出する露出面を有し、上記第１導体部材は、上記積層方向に伸縮可能なばね構造を有する、ことを特徴とする。 In order to achieve the above object, the present invention is configured as follows.
That is, a semiconductor device in one embodiment of the present invention includes a semiconductor chip, a first conductor member bonded to the element formation surface of the semiconductor chip, and a first bond bonded to the facing surface of the semiconductor chip facing the element formation surface. A two-conductor member, the semiconductor chip, and a sealing member that seals a part of the first conductor member and the second conductor member, the first conductor member and the second conductor member, The semiconductor chip, the first conductor member, and the second conductor member have an exposed surface exposed in each main surface of the sealing member in the stacking direction in which the second conductor member is stacked, and the first conductor member extends in the stacking direction. It has an elastic spring structure.

本発明の一態様における半導体装置によれば、第１導体部はバネ構造を有することから、積層方向においてモールド金型にて樹脂封止が行われる際、第１導体部材及び第２導体部材における露出面は、バネ構造の変形によって、モールド金型に密接した状態を維持する。よって、半導体装置における封止部材の主面に導体部材を容易に露出させることが可能となる。   According to the semiconductor device of one aspect of the present invention, since the first conductor portion has a spring structure, when resin sealing is performed with a mold in the stacking direction, the first conductor member and the second conductor member The exposed surface is kept in close contact with the mold due to the deformation of the spring structure. Therefore, the conductor member can be easily exposed on the main surface of the sealing member in the semiconductor device.

本発明の実施の形態１における半導体装置の構造を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention. （ａ）から（ｃ）は、図１に示す半導体装置の製造方法を示す工程図である。(A) to (c) are process diagrams showing a method of manufacturing the semiconductor device shown in FIG. 図１に示す半導体装置の変形例における構造を示す概略断面図である。FIG. 7 is a schematic cross-sectional view showing a structure in a modified example of the semiconductor device shown in FIG. 1. 図３に示す半導体装置の一例としてのインバータ回路の一部を示す回路図である。FIG. 4 is a circuit diagram showing a part of an inverter circuit as an example of the semiconductor device shown in FIG. 3.

本発明の実施形態である半導体装置について、図を参照しながら以下に説明する。尚、各図において、同一又は同様の構成部分については同じ符号を付している。   A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals.

実施の形態１．
本発明の実施の形態１について、図１及び図２を用いて説明する。図１は、本実施形態における半導体装置１００の概略断面図である。半導体装置１００は、基本的構成部分として、半導体チップ１、第１導体部材３、第２導体部材５、及び封止部材９を備える。 Embodiment 1 FIG.
Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to this embodiment. The semiconductor device 100 includes a semiconductor chip 1, a first conductor member 3, a second conductor member 5, and a sealing member 9 as basic components.

半導体チップ１は、本実施形態では、主としてＳｉ又はＳｉＣからなる、厚み０．1〜０．２ｍｍ程度の半導体チップであり、エミッタ電極が形成された素子形成面１ａと、この素子形成面１ａに対向する面でコレクタ電極が形成された裏面１ｂとを有する。   In this embodiment, the semiconductor chip 1 is a semiconductor chip mainly made of Si or SiC and having a thickness of about 0.1 to 0.2 mm. The element formation surface 1a on which the emitter electrode is formed, and the element formation surface 1a And a back surface 1b having a collector electrode formed on the opposing surface.

第１導体部材３は、電極となる帯状の板材にてなる導電性の部材であり、延在方向において中央箇所に位置する中央部と、その両端に位置する端部とを有する。中央部は、素子形成面１ａに平行又はほぼ平行に延在する部分であり、後述の露出面３ａを有する。端部は、素子形成面１ａのエミッタ電極に接続される接続部３ｂと、接続部３ｂと上記中央部とを連結する部分に位置し本実施形態ではＳ字状に屈曲したばね構造３ｃとを有する。接続部３ｂは、電気伝導性を有する接合部材（第１の接合部材）の一例としての半田４を介してエミッタ電極に接続される。   The 1st conductor member 3 is an electroconductive member which consists of a strip | belt-shaped board | plate material used as an electrode, and has the center part located in the center location in the extending direction, and the edge part located in the both ends. The central portion is a portion extending in parallel or substantially parallel to the element forming surface 1a, and has an exposed surface 3a described later. The end portion includes a connecting portion 3b connected to the emitter electrode of the element forming surface 1a, and a spring structure 3c which is located at a portion connecting the connecting portion 3b and the central portion and bent in an S shape in this embodiment. Have. The connection portion 3b is connected to the emitter electrode via a solder 4 as an example of a bonding member (first bonding member) having electrical conductivity.

ばね構造３ｃは、素子形成面１ａに平行又はほぼ平行に延在する上記中央部と、接続部３ｂの少なくとも一部とが、中央部と接続部３ｂとの間において、第１導体部材３の板厚方向において重なるように、本実施形態では湾曲部分を形成しながら層状に折り返した構造である。よって、ばね構造３ｃは、第１導体部材３の板厚方向、つまり、後述するモールド金型１１の型開閉方向１２、さらに換言すると、半導体チップ１、第１導体部材３、及び第２導体部材５を積層した方向である積層方向５１に伸縮可能な構造である。本実施の形態では、ばね構造３ｃは、図示するように、積層方向５１に沿う断面において、略Ｓ字形状であるが、これに限定するものではない。例えば、「Ｚ」状、「＜」若しくは「＞」状、又はこれらを組み合わせた形状、等でもよい。要するに、ばね構造３ｃは、モールド金型の型開閉方向１２つまり積層方向５１に伸縮可能な、蛇腹構造であればよい。   In the spring structure 3c, the central portion extending in parallel or substantially parallel to the element forming surface 1a and at least a part of the connection portion 3b are located between the central portion and the connection portion 3b. In the present embodiment, the structure is folded in layers while forming a curved portion so as to overlap in the plate thickness direction. Therefore, the spring structure 3c is formed in the plate thickness direction of the first conductor member 3, that is, the mold opening / closing direction 12 of the mold 11 to be described later, in other words, the semiconductor chip 1, the first conductor member 3, and the second conductor member. 5 is a structure that can be expanded and contracted in a laminating direction 51 that is a direction in which 5 are laminated. In the present embodiment, the spring structure 3c is substantially S-shaped in the cross section along the stacking direction 51 as shown in the figure, but is not limited thereto. For example, a “Z” shape, a “<” or “>” shape, or a combination of these may be used. In short, the spring structure 3c may be a bellows structure that can expand and contract in the mold opening / closing direction 12 of the mold, that is, the stacking direction 51.

また、半導体チップ１の素子形成面１ａには、ガードリング等の、エミッタ電極と同電位にすると不具合を生じる部位が存在し、この部位が第１導体部材３と接触すると第１導体部材３を介してエミッタ電極と同電位になってしまう。従って、第１導体部材３の接続部３ｂは、半導体チップ１のエミッタ電極のみと接合する構成としている。   Further, the element forming surface 1a of the semiconductor chip 1 has a part such as a guard ring that causes a malfunction when the potential is the same as that of the emitter electrode. When this part comes into contact with the first conductor member 3, the first conductor member 3 is attached. The same potential as the emitter electrode. Therefore, the connection part 3 b of the first conductor member 3 is configured to be joined only to the emitter electrode of the semiconductor chip 1.

第２導体部材５は、電極となるブロック状の導電性部材であり、半導体チップ１の裏面１ｂにおけるコレクタ電極と、第２の接合部材の一例である半田４を介して電気的に接続される。尚、第２導体部材５において、コレクタ電極と接続された面に対向する面が後述する露出面５ａとなる。
また、第１導体部材３及び第２導体部材５として、本実施形態ではＣｕ又はＣｕ合金を用いている。 The second conductor member 5 is a block-like conductive member that serves as an electrode, and is electrically connected to the collector electrode on the back surface 1b of the semiconductor chip 1 via a solder 4 that is an example of a second bonding member. . In the second conductor member 5, the surface facing the surface connected to the collector electrode is an exposed surface 5a described later.
In the present embodiment, Cu or Cu alloy is used as the first conductor member 3 and the second conductor member 5.

封止部材９は、例えばエポキシ系モールド樹脂を用いることができ、モールド金型内へ注入され、半導体チップ１、露出面３ａを除いた第１導体部材３、及び露出面５ａを除いた第２導体部材５、さらに、図示を省略しているが、ボンディングワイヤ、制御用端子の一部も含めて、一括してこれらを封止する。半導体チップ１等を封止した封止部材９において、対向する２つの主面９ａ、９ｂには、第１導体部材３の露出面３ａが、及び第２導体部材５の露出面５ａがそれぞれ露出する。   The sealing member 9 can be made of, for example, an epoxy mold resin, and is injected into a mold, and the semiconductor chip 1, the first conductor member 3 excluding the exposed surface 3a, and the second excluding the exposed surface 5a. Although not shown, the conductor member 5 and the bonding wires and part of the control terminals are collectively sealed. In the sealing member 9 that seals the semiconductor chip 1 and the like, the exposed surface 3a of the first conductor member 3 and the exposed surface 5a of the second conductor member 5 are exposed on the two opposing main surfaces 9a and 9b, respectively. To do.

このようにして、本実施形態の半導体装置１００が構成されている。この半導体装置１００では、半導体チップ１からの発熱を熱伝導性にも優れた半田４を介して主に第２導体部材５に伝え、第２導体部材５の露出面５ａから放熱を行うことができるようになっている。   In this way, the semiconductor device 100 of this embodiment is configured. In the semiconductor device 100, heat generated from the semiconductor chip 1 is mainly transmitted to the second conductor member 5 through the solder 4 having excellent thermal conductivity, and heat is radiated from the exposed surface 5 a of the second conductor member 5. It can be done.

また、第２導体部材５の露出面５ａに冷却部材等を当接させて、更に放熱を促すようにすることもできる。また、第１及び第２の導体部材３、５は、半導体チップ１との電気的な経路となっている。つまり、第２導体部材５を介して半導体チップ１のコレクタ電極との導通を図り、第１導体部材３を介して半導体チップ１のエミッタ電極との導通を図るようになっている。   In addition, a cooling member or the like may be brought into contact with the exposed surface 5a of the second conductor member 5 to further promote heat dissipation. Further, the first and second conductor members 3 and 5 are electrical paths to the semiconductor chip 1. That is, conduction with the collector electrode of the semiconductor chip 1 is achieved via the second conductor member 5, and conduction with the emitter electrode of the semiconductor chip 1 is achieved via the first conductor member 3.

次に、上述した半導体装置１００の製造方法について、図２を参照して説明する。
まず、半導体チップ１の素子形成面１ａに平行又はほぼ平行に第１導体部材３の中央部を配置し、かつ素子形成面１ａのエミッタ電極に第１導体部材３の接続部３ｂを板状の半田４を挟んで配置する。さらに、半導体チップ１の裏面１ｂのコレクタ電極に板状の半田４を挟み第２導体部材５を配置する。このように、半導体チップ１、第１導体部材３、及び第２導体部材５を配置した状態で、これらを還元雰囲気中で一括加熱することにより半田４を溶融させ、その後、冷却することで、半導体チップ１に第１導体部材３及び第２導体部材５が接合された半製品を作製する。 Next, a method for manufacturing the semiconductor device 100 described above will be described with reference to FIG.
First, the central portion of the first conductor member 3 is arranged in parallel or substantially parallel to the element formation surface 1a of the semiconductor chip 1, and the connection portion 3b of the first conductor member 3 is formed in a plate shape on the emitter electrode of the element formation surface 1a. It arrange | positions on both sides of the solder 4. Further, the second conductor member 5 is disposed with the plate-like solder 4 sandwiched between the collector electrodes on the back surface 1 b of the semiconductor chip 1. Thus, in a state where the semiconductor chip 1, the first conductor member 3, and the second conductor member 5 are arranged, the solder 4 is melted by collectively heating them in a reducing atmosphere, and then cooled. A semi-finished product in which the first conductor member 3 and the second conductor member 5 are joined to the semiconductor chip 1 is produced.

次に、上述の半製品を、図２の（ａ）に示すように、モールド金型１１を開いた状態で、下モールド金型１１ｂの内面に第２導体部材５の露出面５ａを接した状態で配置する。
次に、型開閉方向１２に沿ってモールド金型１１を閉じていくと、図２の（ｂ）に示すように、上モールド金型１１ａが第１導体部材３の露出面３ａに接触する。この時点ではモールド金型１１は、完全には閉じておらず、わずかに隙間がある状態になっている。 Next, as shown in FIG. 2A, the above-mentioned semi-finished product is brought into contact with the exposed surface 5a of the second conductor member 5 on the inner surface of the lower mold 11b with the mold 11 opened. Arrange in a state.
Next, when the mold 11 is closed along the mold opening / closing direction 12, the upper mold 11 a comes into contact with the exposed surface 3 a of the first conductor member 3 as shown in FIG. At this time, the mold 11 is not completely closed and is slightly in the state of a gap.

さらにモールド金型１１を閉じていくと、上モールド金型１１ａが第１導体部材３の露出面３ａを押圧し、第１導体部材３のばね構造３ｃが変形する。このような変形を可能にするため、上記半製品は、積層方向５１において、モールド金型１１が完全に型締めされた状態における金型内寸法に比べて、幾分大きく作製する必要がある。しかしながらこれは、第１導体部材３のばね構造３ｃによって容易に寸法調整することが可能である。   When the mold 11 is further closed, the upper mold 11a presses the exposed surface 3a of the first conductor member 3, and the spring structure 3c of the first conductor member 3 is deformed. In order to enable such deformation, the semi-finished product needs to be produced somewhat larger in the stacking direction 51 than the in-mold dimension when the mold 11 is completely clamped. However, this can be easily adjusted by the spring structure 3 c of the first conductor member 3.

そして、図２の（ｃ）に示すように、モールド金型１１が完全に閉じたときには、第１導体部材３のばね構造３ｃの反発力により、第１導体部材３の露出面３ａ及び第２導体部材５の露出面５ａは、それぞれ上モールド金型１１ａ及び下モールド金型１１ｂに押し付けられ密接する。   As shown in FIG. 2C, when the mold 11 is completely closed, the exposed surface 3a of the first conductor member 3 and the second conductor member 3 are repelled by the repulsive force of the spring structure 3c of the first conductor member 3. The exposed surface 5a of the conductor member 5 is pressed against and closely contacts the upper mold 11a and the lower mold 11b, respectively.

このような状態において、モールド金型１１内に封止部材９を注入することで、第１導体部材３の露出面３ａと上モールド金型１１ａの内面との間に、及び、第２導体部材５の露出面５ａと下モールド金型１１ｂの内面との間に封止部材９が入り込むことはない。よって、第１導体部材３の露出面３ａ及び第２導体部材５の露出面５ａが露出する状態で、半導体チップ１等の各部材が封止部材９により封止され、半導体装置１００が完成する。   In such a state, by injecting the sealing member 9 into the mold 11, between the exposed surface 3 a of the first conductor member 3 and the inner surface of the upper mold 11 a and the second conductor member 5, the sealing member 9 does not enter between the exposed surface 5a and the inner surface of the lower mold 11b. Therefore, each member such as the semiconductor chip 1 is sealed by the sealing member 9 with the exposed surface 3a of the first conductor member 3 and the exposed surface 5a of the second conductor member 5 exposed, and the semiconductor device 100 is completed. .

このように、本実施形態の半導体装置１００では、第１導体部材３の両端には、略Ｓ字形のばね構造３ｃがあり、第１導体部材３は、モールド金型１１の型開閉方向１２に伸縮可能な構成となっている。よって、半導体チップ１、第１導体部材３、第２導体部材５を半田４で接合した状態の上記半製品について、モールド金型１１の型開閉方向１２の寸法バラツキを吸収し、かつ、半導体チップ１の損傷及び破壊、並びに、第１導体部材３の露出面３ａ及び第２導体部材５の露出面５ａが封止部材９に覆われることを抑制しつつ、低コストで品質の安定した生産が可能となる。   As described above, in the semiconductor device 100 according to the present embodiment, the first conductor member 3 has the substantially S-shaped spring structure 3 c at both ends, and the first conductor member 3 extends in the mold opening / closing direction 12 of the mold 11. It can be expanded and contracted. Therefore, the semiconductor chip 1, the first conductor member 3, and the second conductor member 5 are joined to the semi-finished product in a state where the dimensional variation in the mold opening / closing direction 12 of the mold 11 is absorbed, and the semiconductor chip 1 and the production of stable and low-quality products while preventing the exposed surface 3a of the first conductor member 3 and the exposed surface 5a of the second conductor member 5 from being covered with the sealing member 9. It becomes possible.

尚、本実施の形態１では、半導体チップ１が１個だけの場合について説明したが、複数個の半導体チップ１が設けられてもよい。さらに、図３に示すように、第１導体部材３が、複数個あるいは複数種類の半導体チップ１に接合されていてもよい。   In the first embodiment, the case where only one semiconductor chip 1 is provided has been described. However, a plurality of semiconductor chips 1 may be provided. Furthermore, as shown in FIG. 3, the first conductor member 3 may be bonded to a plurality or types of semiconductor chips 1.

このような構成とすることで、複数個の半導体チップ１を使用する場合でも、部品点数の増加を最小限に抑制できる。また、２種類の半導体チップ１を用いる場合で、半導体チップ１としてＩＧＢＴを、半導体チップ２としてＦＷＤを適用すると、図４に示すようなインバータ回路２０の一部を構成するＩＧＢＴとＦＷＤの逆並列回路２１を容易に構成することが可能となる。   With such a configuration, even when a plurality of semiconductor chips 1 are used, an increase in the number of components can be suppressed to a minimum. Further, when two types of semiconductor chips 1 are used and an IGBT is applied as the semiconductor chip 1 and an FWD is applied as the semiconductor chip 2, the IGBT and FWD that constitute a part of the inverter circuit 20 as shown in FIG. The circuit 21 can be easily configured.

１ 半導体チップ、２ 半導体チップ、３ 第１導体部材、３ａ 露出面、
３ｃ バネ構造、５ 第２導体部材、５ａ 露出面、９ 封止部材、
１１ａ 上モールド金型、１１ｂ 下モールド金型、１２ 型開閉方向、
５１ 積層方向、１００，１０１ 半導体装置。 DESCRIPTION OF SYMBOLS 1 Semiconductor chip, 2 Semiconductor chip, 3 1st conductor member, 3a Exposed surface,
3c spring structure, 5 second conductor member, 5a exposed surface, 9 sealing member,
11a Upper mold die, 11b Lower mold die, 12 Mold opening / closing direction,
51 Stacking direction, 100, 101 Semiconductor device.

Claims (2)

半導体チップと、
上記半導体チップの素子形成面に接合された第１導体部材と、
上記素子形成面に対向する半導体チップの対向面に接合された第２導体部材と、
上記半導体チップ、並びに、上記第１導体部材及び上記第２導体部材の一部を封止する封止部材と、を備え、
上記第１導体部材及び上記第２導体部材は、上記半導体チップ、上記第１導体部材、及び上記第２導体部材を積層した積層方向において上記封止部材の各主面に露出する露出面を有し、
上記第１導体部材は、上記積層方向に伸縮可能なばね構造を有する、
ことを特徴とする半導体装置。 A semiconductor chip;
A first conductor member bonded to an element formation surface of the semiconductor chip;
A second conductor member bonded to the facing surface of the semiconductor chip facing the element forming surface;
A sealing member that seals a part of the semiconductor chip and the first conductor member and the second conductor member;
The first conductor member and the second conductor member have exposed surfaces that are exposed on the main surfaces of the sealing member in the stacking direction in which the semiconductor chip, the first conductor member, and the second conductor member are stacked. And
The first conductor member has a spring structure that can expand and contract in the stacking direction.
A semiconductor device. 上記半導体チップは複数個備わり、上記第１導体部材は複数の半導体チップと接合されている、請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein a plurality of the semiconductor chips are provided, and the first conductor member is bonded to the plurality of semiconductor chips.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014056916A (en) * 2012-09-12 2014-03-27 Mitsubishi Electric Corp Semiconductor device and semiconductor device manufacturing method
JP2014154611A (en) * 2013-02-06 2014-08-25 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
CN104823277A (en) * 2012-12-10 2015-08-05 罗伯特·博世有限公司 Method for producing a switching module and an associated grid module, and an associated grid module and corresponding electronic subassembly
WO2016039094A1 (en) * 2014-09-11 2016-03-17 株式会社日立パワーデバイス Semiconductor device, and alternator and electric power conversion device using same
US9472538B2 (en) 2013-07-04 2016-10-18 Mitsubishi Electric Corporation Semiconductor device manufacturing method and semiconductor device
US9706643B2 (en) 2014-06-19 2017-07-11 Panasonic Intellectual Property Management Co., Ltd. Electronic device and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283681A (en) * 1996-04-16 1997-10-31 Hitachi Ltd Semiconductor device
JP3601432B2 (en) * 2000-10-04 2004-12-15 株式会社デンソー Semiconductor device
JP2008227131A (en) * 2007-03-13 2008-09-25 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2009252838A (en) * 2008-04-02 2009-10-29 Mitsubishi Electric Corp Semiconductor device
JP2010278107A (en) * 2009-05-27 2010-12-09 Aisin Aw Co Ltd Semiconductor device and connection member

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283681A (en) * 1996-04-16 1997-10-31 Hitachi Ltd Semiconductor device
JP3601432B2 (en) * 2000-10-04 2004-12-15 株式会社デンソー Semiconductor device
JP2008227131A (en) * 2007-03-13 2008-09-25 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2009252838A (en) * 2008-04-02 2009-10-29 Mitsubishi Electric Corp Semiconductor device
JP2010278107A (en) * 2009-05-27 2010-12-09 Aisin Aw Co Ltd Semiconductor device and connection member

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014056916A (en) * 2012-09-12 2014-03-27 Mitsubishi Electric Corp Semiconductor device and semiconductor device manufacturing method
CN104823277A (en) * 2012-12-10 2015-08-05 罗伯特·博世有限公司 Method for producing a switching module and an associated grid module, and an associated grid module and corresponding electronic subassembly
JP2015536579A (en) * 2012-12-10 2015-12-21 ロベルト・ボッシュ・ゲゼルシャフト・ミト・ベシュレンクテル・ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ Method of making switching module and attached grid module, and attached grid module and corresponding electronic unit
JP2014154611A (en) * 2013-02-06 2014-08-25 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
US9735100B2 (en) 2013-02-06 2017-08-15 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing the same
US9472538B2 (en) 2013-07-04 2016-10-18 Mitsubishi Electric Corporation Semiconductor device manufacturing method and semiconductor device
US9706643B2 (en) 2014-06-19 2017-07-11 Panasonic Intellectual Property Management Co., Ltd. Electronic device and method for manufacturing the same
WO2016039094A1 (en) * 2014-09-11 2016-03-17 株式会社日立パワーデバイス Semiconductor device, and alternator and electric power conversion device using same
JP2016058594A (en) * 2014-09-11 2016-04-21 株式会社日立製作所 Semiconductor device, alternator employing the same and power conversion device
CN106605299A (en) * 2014-09-11 2017-04-26 株式会社日立功率半导体 Semiconductor device, and alternator and electric power conversion device using same
US9831145B2 (en) 2014-09-11 2017-11-28 Hitachi Power Semiconductor Device, Ltd. Semiconductor device, and alternator and power converter using the semiconductor device

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