JP2008042074A - Semiconductor device and power conversion device - Google Patents

Semiconductor device and power conversion device Download PDF

Info

Publication number
JP2008042074A
JP2008042074A JP2006216952A JP2006216952A JP2008042074A JP 2008042074 A JP2008042074 A JP 2008042074A JP 2006216952 A JP2006216952 A JP 2006216952A JP 2006216952 A JP2006216952 A JP 2006216952A JP 2008042074 A JP2008042074 A JP 2008042074A
Authority
JP
Japan
Prior art keywords
semiconductor element
surface electrode
semiconductor
main surface
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006216952A
Other languages
Japanese (ja)
Other versions
JP4973059B2 (en
Inventor
Yutaka Tajima
豊 田島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP2006216952A priority Critical patent/JP4973059B2/en
Publication of JP2008042074A publication Critical patent/JP2008042074A/en
Application granted granted Critical
Publication of JP4973059B2 publication Critical patent/JP4973059B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a power conversion device having a plurality of semiconductor elements laminated thereon, while preventing enlarging of the device, by preventing the entirety of the device from becoming thick. <P>SOLUTION: The semiconductor device comprises a first semiconductor element 11 and a second semiconductor element 12, with the principal plane electrodes having the same electric potential, a first heat radiator 15 with the first semiconductor element 11 laminated via a first power substrate 13, a second heat radiator 16 with the second semiconductor element 12 laminated via a second power substrate 14 bonded to the first power substrate 13, in a state with the principal planes disposed facing each other, and a first upper surface electrode 19 bonded to the principal plane electrode of the second semiconductor element 12, with a high thermally-conductive material 20 laminated in between the first semiconductor element 11 and the second semiconductor element 12 that is disposed facing the first semiconductor element 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、半導体装置及び電力変換装置に関し、特に、複数の半導体素子が積層された半導体装置及び電力変換装置に関する。   The present invention relates to a semiconductor device and a power conversion device, and more particularly to a semiconductor device and a power conversion device in which a plurality of semiconductor elements are stacked.

従来、複数の半導体素子が積層された「半導体装置」（特許文献１参照）が知られている。
図７は、従来の半導体装置の構成を示す断面説明図である。図７に示すように、半導体装置１は、下側半導体素子２と上側半導体素子３を積層して形成する。下側半導体素子２を、両側に金属パターンを有する絶縁基板４を介して冷却器５ａに実装する。この下側半導体素子２は、はんだ６ａによって絶縁基板４に実装される。また、上側半導体素子３も、両側に金属パターンを有する絶縁基板７を介して冷却器５ｂに実装する。この上側半導体素子３は、はんだ６ｂによって絶縁基板７に実装される。 Conventionally, a “semiconductor device” (see Patent Document 1) in which a plurality of semiconductor elements are stacked is known.
FIG. 7 is an explanatory cross-sectional view showing a configuration of a conventional semiconductor device. As shown in FIG. 7, the semiconductor device 1 is formed by stacking a lower semiconductor element 2 and an upper semiconductor element 3. The lower semiconductor element 2 is mounted on the cooler 5a via an insulating substrate 4 having metal patterns on both sides. The lower semiconductor element 2 is mounted on the insulating substrate 4 with solder 6a. The upper semiconductor element 3 is also mounted on the cooler 5b via an insulating substrate 7 having metal patterns on both sides. The upper semiconductor element 3 is mounted on the insulating substrate 7 with solder 6b.

そして、下側半導体素子２の主面電極上に電極２ａを実装し、更に、電極２ａ上に絶縁材８ａを介して冷却器５ｂを載せ、更に、上側半導体素子３の主面電極上に電極３ａを実装し、更に、電極３ａ上に絶縁材８ｂを介して冷却器５ｃを載せる。
この従来の半導体装置１は、下側半導体素子２と上側半導体素子３共に表裏面に冷却器５ａ，５ｂを有するため、冷却性能が高くなり、それにより温度上昇を抑えるとしている。また、両半導体素子２，３を積層しているので、半導体素子の実装密度を向上させて設置面積を縮小することができるとしている。
特開２００１−２４４４０７号公報 Then, the electrode 2 a is mounted on the main surface electrode of the lower semiconductor element 2, and the cooler 5 b is mounted on the electrode 2 a via the insulating material 8 a, and the electrode is further formed on the main surface electrode of the upper semiconductor element 3. 3a is mounted, and a cooler 5c is mounted on the electrode 3a via an insulating material 8b.
Since the conventional semiconductor device 1 has the coolers 5a and 5b on the front and back surfaces of both the lower semiconductor element 2 and the upper semiconductor element 3, the cooling performance is improved, thereby suppressing the temperature rise. In addition, since both semiconductor elements 2 and 3 are stacked, the mounting area of the semiconductor elements can be improved and the installation area can be reduced.
JP 2001-244407 A

しかしながら、従来の半導体装置１は、複数の半導体素子と複数の冷却器とを電気的な絶縁性を確保しながら積層する構造であるため、積層する部材の数が増えて装置全体が厚くなってしまい、装置が大型化してしまうことが避けられない。
この発明の目的は、装置全体が厚くならないようにして装置が大型化するのを防止した、複数の半導体素子が積層された半導体装置及び電力変換装置を提供することである。 However, since the conventional semiconductor device 1 has a structure in which a plurality of semiconductor elements and a plurality of coolers are stacked while ensuring electrical insulation, the number of members to be stacked increases and the entire device becomes thicker. Therefore, it is inevitable that the apparatus becomes large.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a power conversion device in which a plurality of semiconductor elements are stacked so that the device is prevented from becoming large without increasing the thickness of the entire device.

上記目的を達成するため、この発明に係る半導体装置は、主面電極同士が電気的に同電位の第１半導体素子及び第２半導体素子と、第１基板を介して前記第１半導体素子を積層した第１放熱器と、前記第１基板と主面同士を対向配置して接合した第２基板を介して前記第２半導体素子を積層した第２放熱器と、前記第１半導体素子と前記第１半導体素子に対向配置した前記第２半導体素子との間に積層され、前記第２半導体素子の主面電極に高熱伝導性材料で接合した第１上面電極とを有している。   In order to achieve the above object, a semiconductor device according to the present invention includes a first semiconductor element and a second semiconductor element whose main surface electrodes are electrically at the same potential, and the first semiconductor element stacked via a first substrate. A first radiator, a second radiator in which the second semiconductor elements are stacked via a second substrate in which main surfaces of the first substrate are arranged opposite to each other, and the first semiconductor element and the first substrate And a first upper surface electrode that is stacked between the second semiconductor element and the second semiconductor element that is disposed opposite to the first semiconductor element, and is joined to the main surface electrode of the second semiconductor element with a high thermal conductivity material.

また、この発明に係る電力変換装置は、この発明に係る半導体装置の前記第１半導体素子を絶縁ゲート型バイポーラトランジスタとし、前記第２半導体素子をダイオードとして、前記第１半導体素子と前記第２半導体素子の主面電極同士を電気的に接続すると共に、前記第１半導体素子と前記第２半導体素子の裏面電極同士を電気的に接続することによりスイッチ回路を形成し、前記スイッチ回路を複数個用いてインバータ回路を形成している。   The power conversion device according to the present invention is a semiconductor device according to the present invention, wherein the first semiconductor element is an insulated gate bipolar transistor, the second semiconductor element is a diode, and the first semiconductor element and the second semiconductor. The main surface electrodes of the element are electrically connected to each other, and the back electrodes of the first semiconductor element and the second semiconductor element are electrically connected to form a switch circuit, and a plurality of the switch circuits are used. To form an inverter circuit.

この発明によれば、第１基板を介して第１半導体素子を積層した第１放熱器と、第１基板と主面同士を対向配置して接合した第２基板を介して第２半導体素子を積層した第２放熱器とを有し、第１半導体素子と第１半導体素子に対向配置した前記第２半導体素子との間に、第２半導体素子の主面電極に高熱伝導性材料で接合した第１上面電極が積層されており、第１半導体素子及び第２半導体素子の主面電極同士が電気的に同電位にされている。このため、複数の半導体素子が積層された半導体装置において、装置全体が厚くならないようにして装置が大型化するのを防止することができる。
また、この発明に係る半導体装置により、電力変換装置を実現することができる。 According to the present invention, the first heatsink having the first semiconductor element laminated via the first substrate, and the second semiconductor element via the second substrate in which the first substrate and the main surface are arranged opposite to each other and joined. A second heat radiator laminated, and the first semiconductor element and the second semiconductor element disposed opposite to the first semiconductor element are joined to a main surface electrode of the second semiconductor element with a high thermal conductivity material. The first upper surface electrodes are stacked, and the main surface electrodes of the first semiconductor element and the second semiconductor element are electrically at the same potential. For this reason, in a semiconductor device in which a plurality of semiconductor elements are stacked, the size of the device can be prevented from being increased without increasing the thickness of the entire device.
In addition, a power conversion device can be realized by the semiconductor device according to the present invention.

以下、この発明を実施するための最良の形態について図面を参照して説明する。
（第１実施の形態）
図１は、この発明の第１実施の形態に係る電力変換装置の断面構造を示す説明図である。図１に示すように、電力変換装置（半導体装置）１０は、第１半導体素子１１と第２半導体素子１２の複数の半導体素子と共に、第１電力基板（基板）１３と第２電力基板（基板）１４、第１放熱器１５と第２放熱器１６を有している。第２電力基板１４は、一端側主面（表面）が段差面となるように屈曲して形成されており、第１電力基板１３の一端側主面上に第２電力基板１４の一端側主面を重ねて接続することにより、第２電力基板１４は、第１電力基板１３の上方に離間して位置する。 The best mode for carrying out the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is an explanatory diagram showing a cross-sectional structure of the power conversion device according to the first embodiment of the present invention. As shown in FIG. 1, a power conversion device (semiconductor device) 10 includes a first power substrate (substrate) 13 and a second power substrate (substrate) together with a plurality of semiconductor elements of a first semiconductor element 11 and a second semiconductor element 12. ) 14, a first radiator 15 and a second radiator 16 are provided. The second power board 14 is formed to be bent so that the one end side main surface (surface) becomes a stepped surface, and the one end side main face of the second power board 14 is formed on the one end side main face of the first power board 13. The second power board 14 is positioned above the first power board 13 by being connected with overlapping surfaces.

この電力変換装置１０は、以下の工程を経て形成される。
先ず、第１半導体素子１１を第１電力基板１３の主面上に実装すると共に、第２半導体素子１２を第２電力基板１４の主面上に実装する。そして、第１電力基板１３を、第１放熱器１５に、直接、又は絶縁領域１７或いはベースプレート（図示しない）を介して実装する。同様に、第２電力基板１４を、第２放熱器１６に、直接、又は絶縁領域１８或いはベースプレート（図示しない）を介して実装する。
次に、第１半導体素子１１の主面電極と第２半導体素子１２の主面電極が対向するように、第１電力基板１３の主面上に第２電力基板１４の主面を向かい合わせにして近接配置する。これにより、第１電力基板１３と第２電力基板１４は、それぞれの主面を対向させると共に各主面の間に空間を有することになる。 This power converter 10 is formed through the following steps.
First, the first semiconductor element 11 is mounted on the main surface of the first power substrate 13 and the second semiconductor element 12 is mounted on the main surface of the second power substrate 14. Then, the first power board 13 is mounted on the first radiator 15 directly or via the insulating region 17 or a base plate (not shown). Similarly, the second power board 14 is mounted on the second radiator 16 directly or via an insulating region 18 or a base plate (not shown).
Next, the main surface of the second power substrate 14 faces the main surface of the first power substrate 13 so that the main surface electrode of the first semiconductor element 11 and the main surface electrode of the second semiconductor element 12 face each other. And place them close together. Thereby, the 1st power board 13 and the 2nd power board 14 have space between each main surface while making each main surface oppose.

次に、第１半導体素子１１の主面電極上に、第１上面電極１９を実装し、その後、第１上面電極１９と第２半導体素子１２の主面電極を、高熱伝導性材料２０で接合する。そして、第１半導体素子１１の主面電極と第２半導体素子１２の主面電極が電気的に同電位である構成とする。また、第１半導体素子１１と第２半導体素子１２は、互いに同一の電気的動作をしない構成とする。高熱伝導性材料２０としては、例えば、銀ペーストや、金属粒子又はセラミック粒子を含有しているエポキシ系或いはシリコン系接着剤等の導電性接着剤が用いられる。   Next, the first upper surface electrode 19 is mounted on the main surface electrode of the first semiconductor element 11, and then the first upper surface electrode 19 and the main surface electrode of the second semiconductor element 12 are joined by the high thermal conductive material 20. To do. The main surface electrode of the first semiconductor element 11 and the main surface electrode of the second semiconductor element 12 are configured to be electrically at the same potential. The first semiconductor element 11 and the second semiconductor element 12 are configured not to perform the same electrical operation. As the high thermal conductive material 20, for example, a silver paste or a conductive adhesive such as an epoxy-based or silicon-based adhesive containing metal particles or ceramic particles is used.

ここで、第１電力基板１３と第２電力基板１４の接続は、例えば、溶接や超音波接合等により行う。また、第１半導体素子１１の主面電極と第１上面電極１９の接合、第１半導体素子１１の裏面電極と第１電力基板１３の実装接合、第２半導体素子１２の裏面電極と第２電力基板１４の実装接合は、それぞれ、例えば、はんだ２１を用いたはんだ付けで行なう。
この電力変換装置１０は、第１半導体素子１１を絶縁ゲート型バイポーラトランジスタ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ：ＩＧＢＴ）とし、第２半導体素子１２を高速整流ダイオード（Ｆａｓｔ Ｒｅｃｏｖｅｒｙ Ｄｉｏｄｅｓ：ＦＲＤ）とすることにより、スイッチ回路を形成する。 Here, the connection between the first power board 13 and the second power board 14 is performed by, for example, welding or ultrasonic bonding. Also, the junction between the main surface electrode of the first semiconductor element 11 and the first upper surface electrode 19, the back electrode of the first semiconductor element 11 and the mounting junction of the first power substrate 13, the back electrode of the second semiconductor element 12 and the second power. The mounting joining of the board | substrate 14 is performed by soldering using the solder 21, for example.
The power conversion device 10 uses a first semiconductor element 11 as an insulated gate bipolar transistor (IGBT) and a second semiconductor element 12 as a fast rectifier diode (FRD), thereby switching. Form a circuit.

図２は、図１の電力変換装置により形成したスイッチ回路を用いた３相インバータ回路の回路図である。図２に示すように、電力変換装置１０により形成したスイッチ回路２２を用いた３相インバータ回路２３は、電動機２４を駆動する。
ＩＧＢＴ２５（第１半導体素子１１）の主面電極とＦＲＤ２６（第２半導体素子１２）の主面電極を、電気的に接続すると共に、ＩＧＢＴ２５の裏面電極とＦＲＤ２６の裏面電極を、電気的に接続する。これらの接続により、スイッチ回路２２を形成する。そして、このスイッチ回路２２を複数個直列乃至並列に接続することにより、３相インバータ回路２３を形成する。 FIG. 2 is a circuit diagram of a three-phase inverter circuit using a switch circuit formed by the power conversion device of FIG. As shown in FIG. 2, the three-phase inverter circuit 23 using the switch circuit 22 formed by the power converter 10 drives the electric motor 24.
The main surface electrode of the IGBT 25 (first semiconductor element 11) and the main surface electrode of the FRD 26 (second semiconductor element 12) are electrically connected, and the back electrode of the IGBT 25 and the back electrode of the FRD 26 are electrically connected. . The switch circuit 22 is formed by these connections. A plurality of switch circuits 22 are connected in series or in parallel to form a three-phase inverter circuit 23.

即ち、電動機２４を駆動する３相インバータ回路２３は、一般的に、ＩＧＢＴ２５とＦＲＤ２６を並列接続したスイッチ回路２２を直列接続して、電気的な１相（Ｕ相，Ｖ相，Ｗ相）分の駆動回路を構成し、この駆動回路を３相分並列接続して、３相インバータ回路２３を構成する。３相インバータ回路２３の直流入力側には平滑コンデンサ２７と電源２８が接続される。なお、
上記構成を有する電力変換装置１０は、以下の効果を得ることができる。 That is, the three-phase inverter circuit 23 for driving the electric motor 24 is generally connected in series with a switch circuit 22 in which an IGBT 25 and an FRD 26 are connected in parallel, and is electrically divided into one phase (U phase, V phase, W phase). The three-phase inverter circuit 23 is configured by connecting the drive circuits in parallel for three phases. A smoothing capacitor 27 and a power source 28 are connected to the DC input side of the three-phase inverter circuit 23. In addition,
The power conversion device 10 having the above configuration can obtain the following effects.

第１に、半導体素子の温度上昇を顕著に抑制することができる。即ち、第１半導体素子１１が通電により発熱している場合、その熱は、第１半導体素子１１の裏面から第１電力基板１３を介して第１放熱器１５に伝わる。更に、第１半導体素子１１の主面側から第２半導体素子１２、そして、第２電力基板１４を介して、第２放熱器１６へも伝えることができる。
これにより、第１半導体素子１１の温度上昇を顕著に抑えることができると共に、第２半導体素子１２についても同様に温度上昇を顕著に抑制することができる。 First, the temperature rise of the semiconductor element can be remarkably suppressed. That is, when the first semiconductor element 11 generates heat by energization, the heat is transmitted from the back surface of the first semiconductor element 11 to the first radiator 15 via the first power substrate 13. Further, it can be transmitted from the main surface side of the first semiconductor element 11 to the second radiator 16 via the second semiconductor element 12 and the second power substrate 14.
Thereby, the temperature rise of the first semiconductor element 11 can be remarkably suppressed, and the temperature rise of the second semiconductor element 12 can be remarkably suppressed similarly.

ここで、本構成では、第１半導体素子１１の主面電極と第２半導体素子１２の主面電極が電気的に同電位であることにより、両半導体素子１１，１２の間で電気的な絶縁を得るために間隔を空ける必要が無く、両半導体素子１１，１２を十分に近接させた状態にすることができる。
また、両半導体素子１１，１２の主面電極の間、つまり、第１半導体素子１１の第１上面電極１９と第２半導体素子１２の主面電極を接合する高熱伝導性材料２０も絶縁体である必要が無い。このため、一般に、電気伝導性を有する接合材料は、絶縁性を有する接合材料よりも熱伝導性が良く、更に、絶縁性を必要としないので、薄くして熱抵抗を下げることができる。 Here, in this configuration, since the main surface electrode of the first semiconductor element 11 and the main surface electrode of the second semiconductor element 12 are at the same electric potential, electrical insulation is provided between the semiconductor elements 11 and 12. Therefore, it is not necessary to leave a space between the two semiconductor elements 11 and 12 in a sufficiently close state.
Further, the high thermal conductive material 20 that joins the main surface electrodes of both the semiconductor elements 11 and 12, that is, the first upper surface electrode 19 of the first semiconductor element 11 and the main surface electrode of the second semiconductor element 12 is also an insulator. There is no need. For this reason, in general, a bonding material having electrical conductivity has better thermal conductivity than a bonding material having insulating properties, and further, since insulating properties are not required, it can be thinned to reduce thermal resistance.

この結果、両半導体素子１１，１２で生じた熱を、一方の半導体素子の主面側に対向して位置する他方の半導体素子を介して、他方の半導体素子側に配置された放熱器にも低熱抵抗により伝熱することができる。即ち、両半導体素子１１，１２の発熱を上下面の両方に低熱抵抗により伝熱することができるので、両半導体素子１１，１２における温度上昇を顕著に抑制することができる。
また、熱結合部分は、高熱伝導性材料２０である、例えば、銀ペースト等の導電性接着剤を用いているので、はんだ付けによる接合後は金属応力緩和不能であったのに対し、応力緩和が可能になる。 As a result, the heat generated in both the semiconductor elements 11 and 12 is also transferred to the radiator disposed on the other semiconductor element side through the other semiconductor element positioned opposite to the main surface side of the one semiconductor element. Heat can be transferred by low thermal resistance. That is, since the heat generation of both the semiconductor elements 11 and 12 can be transferred to both the upper and lower surfaces with a low thermal resistance, the temperature rise in both the semiconductor elements 11 and 12 can be remarkably suppressed.
In addition, since the heat-bonded portion is made of a highly heat-conductive material 20, for example, a conductive adhesive such as silver paste, the metal stress cannot be relieved after joining by soldering. Is possible.

第２に、両半導体素子１１，１２の各主面側に、放熱経路を簡便、且つ、確実に設けることができる。
本構成では、第１半導体素子１１の主面側に対向して第２半導体素子１２を載せる構成を有している。ここで、単純に両半導体素子１１，１２を対向して接合させようとすると、これら半導体素子１１，１２がそれぞれ複数ある場合、第１半導体素子１１に対して第２半導体素子１２を固定する部分の形状精度によって、両半導体素子１１，１２の主面電極間隔がばらつく懸念がある。この場合でも、本構成では、高熱伝導性材料からなる高熱伝導性材料２０の潰れによって寸法ばらつきを吸収した後に、硬化させ接合することが可能である。 Secondly, a heat radiation path can be easily and reliably provided on each main surface side of both semiconductor elements 11 and 12.
In this configuration, the second semiconductor element 12 is placed opposite to the main surface side of the first semiconductor element 11. Here, when both the semiconductor elements 11 and 12 are simply joined to face each other, when there are a plurality of these semiconductor elements 11 and 12, a portion for fixing the second semiconductor element 12 to the first semiconductor element 11. There is a concern that the distance between the principal surface electrodes of the semiconductor elements 11 and 12 varies depending on the shape accuracy. Even in this case, in this configuration, the high thermal conductivity material 20 made of the high thermal conductivity material can be cured and bonded after the dimensional variation is absorbed by the collapse.

更に、第１の効果でも述べたように、両半導体素子１１，１２の主面電極が同電位であるので、両半導体素子１１，１２の間に絶縁材料を介在させる必要が無い。このため、介在させた絶縁材料の厚さばらつきによって、接合が不十分、且つ、不安定になることや、絶縁材料の表裏面と両半導体素子１１，１２の主面電極の接合を共に行なうことによって、製造工程が複雑になり製造コストが上昇することも、防止することができる。   Further, as described in the first effect, since the principal surface electrodes of both semiconductor elements 11 and 12 are at the same potential, there is no need to interpose an insulating material between both semiconductor elements 11 and 12. For this reason, due to the thickness variation of the interposed insulating material, the bonding becomes insufficient and unstable, and the front and back surfaces of the insulating material and the main surface electrodes of both semiconductor elements 11 and 12 are bonded together. Therefore, it is possible to prevent the manufacturing process from becoming complicated and the manufacturing cost from increasing.

第３に、第１半導体素子１１の主面上に第２半導体素子１２を載せる構成を有しているので、両半導体素子１１，１２を実装する部分の投影面積を大幅に減らすことができる。更に、第２の効果でも述べたように、両半導体素子１１，１２の主面電極の間に新たに絶縁材料を介在させず、且つ、主面電極が同電位であるので、両半導体素子１１，１２を十分に近接させて配置することができる。よって、電力変換装置１０の厚み増加を押さえると共に投影面積を大幅に抑えることができるので、装置全体を大幅に小型化することができる。   Thirdly, since the second semiconductor element 12 is placed on the main surface of the first semiconductor element 11, the projected area of the portion where both the semiconductor elements 11 and 12 are mounted can be greatly reduced. Furthermore, as described in the second effect, since no new insulating material is interposed between the main surface electrodes of both semiconductor elements 11 and 12 and the main surface electrodes are at the same potential, both semiconductor elements 11 , 12 can be placed close enough. Therefore, since the increase in thickness of the power conversion device 10 can be suppressed and the projected area can be greatly suppressed, the entire device can be greatly reduced in size.

第４に、第３の効果によって、電力変換器１０の投影面積が減れば、両半導体素子１１，１２のそれぞれから、平滑コンデンサ２９（図２参照）までのバスバを大幅に短くすることができる。よって、このバスバの寄生インダクタンスが小さくなり、電力変換装置１０の大電流動作に対する安定度を著しく高めることができる。
なお、各半導体素子（１１，１２）と放熱器（１５，１６）との間の熱結合は、従来通り、半導体素子の裏面側を絶縁領域１７，１８或いはベースプレートを介して実装する。この熱結合を、十分に低い熱抵抗で確実に行なうことは困難では無い。 Fourth, if the projected area of the power converter 10 is reduced by the third effect, the bus bar from each of the semiconductor elements 11 and 12 to the smoothing capacitor 29 (see FIG. 2) can be significantly shortened. . Therefore, the parasitic inductance of the bus bar is reduced, and the stability of the power conversion device 10 with respect to a large current operation can be significantly increased.
In addition, as for the thermal coupling between each semiconductor element (11, 12) and the radiator (15, 16), the back surface side of the semiconductor element is mounted via the insulating regions 17 and 18 or the base plate as usual. It is not difficult to reliably perform this thermal coupling with a sufficiently low thermal resistance.

また、第１半導体素子１１と第２半導体素子１２は、互いに同一の電気的動作をしない構成とすることにより、以下の効果を得ることができる。
電力変換器として、例えば、３相インバータ回路２３を例に挙げると、電力変換を行なうスイッチ回路２２は、ＩＧＢＴ２５に高速整流ダイオード（Ｆａｓｔ Ｒｅｃｏｖｅｒｙ Ｄｉｏｄｅｓ：ＦＲＤ）２６が並列接続されている構成が一般的である。 Moreover, the following effects can be acquired by making the 1st semiconductor element 11 and the 2nd semiconductor element 12 into the structure which does not mutually perform the same electrical operation.
As an example of a power converter, taking a three-phase inverter circuit 23 as an example, the switch circuit 22 that performs power conversion generally has a configuration in which a fast rectifier diode (FRD) 26 is connected in parallel to an IGBT 25. It is.

この第１半導体素子１１をＩＧＢＴ２５、第２半導体素子１２をＦＲＤ２６とした場合は、両半導体素子１１，１２の裏面側電極は同電位になり、且つ、主面電極も同電位になる。そして、並列接続されているＩＧＢＴ２５とＦＲＤ２６は、スイッチング動作での極短時間の遷移状態を除けば、ＩＧＢＴ２５とＦＲＤ２６の両方に電流が流れることは無い。更に、３相インバータ回路２３が電動機２４を力行状態にしているときは、主に、ＩＧＢＴ２５に電流が流れ、３相インバータ回路２３が電動機２４を回生状態にしているときは、主に、ＦＲＤ２６に電流が流れる。このため、第１半導体素子１１と第２半導体素子１２に同時に大電流が流れて、大きな発熱が生じることは無い。   When the first semiconductor element 11 is the IGBT 25 and the second semiconductor element 12 is the FRD 26, the back surface side electrodes of both the semiconductor elements 11 and 12 have the same potential, and the main surface electrode also has the same potential. The IGBTs 25 and FRDs 26 connected in parallel do not cause current to flow through both the IGBTs 25 and FRDs 26 except for a very short transition state in the switching operation. Further, when the three-phase inverter circuit 23 is in the power running state of the motor 24, current flows mainly to the IGBT 25, and when the three-phase inverter circuit 23 is in the regenerative state of the motor 24, mainly the FRD 26 is Current flows. For this reason, a large current does not flow through the first semiconductor element 11 and the second semiconductor element 12 at the same time, and no significant heat is generated.

よって、電動機２４を力行駆動して、主に、ＩＧＢＴ２５である第１半導体素子１１が発熱している間は、第１半導体素子１１の裏面側と主面側の両方から放熱される。このとき、第２半導体素子１２の発熱は小さく、第１半導体素子１１の放熱に悪影響を与えることはない。また、電動機２４を回生駆動している間は、主に、ＦＲＤ２６である第２半導体素子１２が発熱し、素子の裏面側と主面側の両方から放熱される。このとき、第１半導体素子１１の発熱は小さく、第２半導体素子１２の放熱に悪影響を与えることはない。つまり、第１半導体素子１１と第２半導体素子１２が上下に積層された状態であるが、大きな発熱を生じる素子は１個であるため、その発熱を上下に放熱することができる。また、半導体素子同士の熱が加わって、過剰に発熱してしまう懸念は無い。   Therefore, while the electric motor 24 is driven by powering and the first semiconductor element 11 that is the IGBT 25 generates heat, heat is radiated from both the back surface side and the main surface side of the first semiconductor element 11. At this time, the heat generation of the second semiconductor element 12 is small, and the heat dissipation of the first semiconductor element 11 is not adversely affected. While the electric motor 24 is being regeneratively driven, the second semiconductor element 12 that is the FRD 26 mainly generates heat and is radiated from both the back surface side and the main surface side of the element. At this time, the heat generation of the first semiconductor element 11 is small, and the heat dissipation of the second semiconductor element 12 is not adversely affected. That is, the first semiconductor element 11 and the second semiconductor element 12 are stacked one above the other. However, since there is one element that generates a large amount of heat, the generated heat can be radiated up and down. Further, there is no concern that heat is generated between the semiconductor elements and excessive heat is generated.

また、第１上面電極１９と第２半導体素子１２の主面電極を、高熱伝導性材料２０である導電性接着剤で接合する構成とすることにより、以下の効果を得ることができる。
第１に、製造工程が更に容易になる。即ち、導電性接着剤は、塗布後に熱硬化処理を行なえばよいので、本構成のような複数の部品を積層する構造であっても、常温で導電性接着剤を塗布し、その後、熱硬化をすれば、容易に形成することができる。 Moreover, the following effects can be acquired by making it the structure which joins the 1st upper surface electrode 19 and the main surface electrode of the 2nd semiconductor element 12 with the electroconductive adhesive which is the high heat conductive material 20. FIG.
First, the manufacturing process is further facilitated. That is, the conductive adhesive only needs to be heat-cured after application, so even if it has a structure in which a plurality of parts are laminated as in this configuration, the conductive adhesive is applied at room temperature and then heat-cured. If it does, it can form easily.

第２に、材料の寸法公差ばらつきが生じてしまうことによる問題を容易に解決することができる。即ち、本構成のような複数の材料を積層する構造、更に、半導体素子部分の積層構造以外に、第１電力基板１３と第２電力基板１４とを直接又は接続用の電極を介して接続する場合は、各部材の寸法公差による精度ばらつきが発生することが避けられないが、本構成では、導電性接着剤が熱硬化処理前は容易に変形可能な性質を利用し、接着剤の潰れにより寸法公差のばらつきを吸収することができる。
また、電力変換装置１０の第１半導体素子１１を絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）とし、第２半導体素子１２をダイオードとすることにより、スイッチ回路を形成する構成とすることにより、以下の効果を得ることができる。 Secondly, it is possible to easily solve the problem caused by variation in the dimensional tolerance of the material. That is, in addition to the structure in which a plurality of materials are stacked as in this configuration, and in addition to the stacked structure of the semiconductor element portion, the first power board 13 and the second power board 14 are connected directly or via electrodes for connection. In this case, it is inevitable that variations in accuracy due to dimensional tolerances of each member will occur, but in this configuration, the conductive adhesive uses the property that it can be easily deformed before the thermosetting treatment, and the adhesive is crushed. Variations in dimensional tolerances can be absorbed.
Further, the first semiconductor element 11 of the power conversion device 10 is an insulated gate bipolar transistor (IGBT), and the second semiconductor element 12 is a diode, thereby forming a switch circuit, thereby providing the following effects. Obtainable.

３相インバータ回路２３を構成するＩＧＢＴ２５とＦＲＤ２６からなるスイッチ回路２２の投影面積を大幅に減らすことができる。これにより、３相インバータ回路２３を大幅に小型化することができる。合わせて、ＩＧＢＴ２５とＦＲＤ２６が、同時に大きな発熱を生じることは無く、且つ、ＩＧＢＴ２５とＦＲＤ２６が何れも裏面と主面の双方から放熱することできる。これにより、３相インバータ回路２３を更に小型化することができる。
（第２実施の形態） The projected area of the switch circuit 22 composed of the IGBT 25 and the FRD 26 constituting the three-phase inverter circuit 23 can be greatly reduced. Thereby, the three-phase inverter circuit 23 can be significantly reduced in size. In addition, the IGBT 25 and the FRD 26 do not generate large heat at the same time, and both the IGBT 25 and the FRD 26 can radiate heat from both the back surface and the main surface. Thereby, the three-phase inverter circuit 23 can be further reduced in size.
(Second Embodiment)

図３は、この発明の第２実施の形態に係る電力変換装置の断面構造を示す説明図である。図３に示すように、電力変換装置３０は、第１上面電極１９の主面（表面）の上に第２上面電極３１を配置し、第１半導体素子１１と第２半導体素子１２の間に、第１上面電極１９と第２上面電極３１を介在させている。その他の構成及び作用は、第１実施の形態の電力変換装置１０と同様である。   FIG. 3 is an explanatory diagram showing a cross-sectional structure of the power conversion device according to the second embodiment of the present invention. As shown in FIG. 3, the power conversion device 30 includes a second upper surface electrode 31 disposed on the main surface (front surface) of the first upper surface electrode 19, and is interposed between the first semiconductor element 11 and the second semiconductor element 12. The first upper surface electrode 19 and the second upper surface electrode 31 are interposed. Other configurations and operations are the same as those of the power conversion device 10 of the first embodiment.

この電力変換装置３０を形成する場合、第２半導体素子１２の主面に第２上面電極３１を実装して、第１上面電極１９と第２上面電極３１を電気的に接続する。それと共に、第１半導体素子１１の主面電極に対応する第１上面電極１９と、第２半導体素子１２の主面電極に対応する第２上面電極３１を、第１上面電極１９の主面に第２上面電極３１の段差面となるように屈曲して形成された一端側主面を載置して、両上面電極１９，３１間に層状に位置する高熱伝導性材料２０により接合する。なお、第２半導体素子１２の主面電極と第２上面電極３１の接合には、例えば、はんだ２１を用いたはんだ付けで行う。
上記構成を有する電力変換装置３０は、第１実施の形態の電力変換装置１０の効果に加えて、以下の効果を得ることができる。 When forming this power converter 30, the 2nd upper surface electrode 31 is mounted in the main surface of the 2nd semiconductor element 12, and the 1st upper surface electrode 19 and the 2nd upper surface electrode 31 are electrically connected. At the same time, the first upper surface electrode 19 corresponding to the main surface electrode of the first semiconductor element 11 and the second upper surface electrode 31 corresponding to the main surface electrode of the second semiconductor element 12 are formed on the main surface of the first upper surface electrode 19. One main surface of the second upper surface electrode 31 that is bent so as to be a stepped surface is placed, and the upper surface electrodes 19 and 31 are joined by the high thermal conductive material 20 located in a layered manner. For example, the main surface electrode of the second semiconductor element 12 and the second upper surface electrode 31 are joined by soldering using the solder 21.
The power conversion device 30 having the above configuration can obtain the following effects in addition to the effects of the power conversion device 10 of the first embodiment.

第１に、電気的な接続をより一層確実に行なうことができる。例えば、３相インバータ回路２３において、電力制御を行なうために並列に接続されている第１半導体素子１１（ＩＧＢＴ２５）と第２半導体素子１２（ＦＲＤ２６）のそれぞれの主面電極は、前述したように同電位となる。この場合、各上面電極１９，３１をはんだ付け等で主面電極に接続すると共に、各上面電極１９，３１同士を接続すれば、両主面電極の間の電気的接続を確実に行うことができる。
また、高熱伝導性材料２０は、必ずしも大電流を流すことに適さない場合もあるが、本構成では、このような場合でも大電流を確実に流せる電気的接続を、各上面電極１９，３１で確実、且つ、容易に行うことができる。なお、両上面電極１９，３１間の熱結合は、高熱伝導性材料２０でもって行なえば良い。 First, electrical connection can be made more reliably. For example, in the three-phase inverter circuit 23, the main surface electrodes of the first semiconductor element 11 (IGBT 25) and the second semiconductor element 12 (FRD 26) connected in parallel to perform power control are as described above. It becomes the same potential. In this case, the upper surface electrodes 19 and 31 are connected to the main surface electrodes by soldering or the like, and if the upper surface electrodes 19 and 31 are connected to each other, the electrical connection between the two main surface electrodes can be reliably performed. it can.
In addition, the high thermal conductivity material 20 may not necessarily be suitable for flowing a large current. However, in this configuration, the upper surface electrodes 19 and 31 can provide an electrical connection that allows a large current to flow reliably even in such a case. It can be performed reliably and easily. The thermal coupling between the upper surface electrodes 19 and 31 may be performed with the high thermal conductivity material 20.

ここで、両半導体素子１１，１２の裏面側電極も電気的に接続する場合は、これら半導体素子１１，１２が実装されている第１電力基板１３と第２電力基板１４を電気的に接続すれば良い。
第２に、各上面電極１９，３１が、各半導体素子１１，１２で生じた熱を上面側に伝熱する際にヒートスプレッダとして機能する。即ち、高熱伝導性材料２０の熱抵抗は、金属の値ほど低くない場合が多いが、本構成では、熱が高熱伝導性材料２０に達する前に、低熱抵抗の金属からなる各上面電極１９，３１でヒートスプレッドすることができる。よって、この高熱伝導性材料２０部分での温度勾配を、更に低減することができ、各半導体素子１１，１２の温度をより一層、且つ、容易に低減することができる。
（第３実施の形態） Here, when the back side electrodes of both the semiconductor elements 11 and 12 are also electrically connected, the first power board 13 and the second power board 14 on which the semiconductor elements 11 and 12 are mounted are electrically connected. It ’s fine.
Second, each upper surface electrode 19, 31 functions as a heat spreader when the heat generated in each semiconductor element 11, 12 is transferred to the upper surface side. That is, the thermal resistance of the high thermal conductivity material 20 is often not as low as the value of the metal. However, in this configuration, before the heat reaches the high thermal conductivity material 20, the upper surface electrodes 19, You can heat spread at 31. Therefore, the temperature gradient in the high thermal conductive material 20 portion can be further reduced, and the temperatures of the semiconductor elements 11 and 12 can be further and easily reduced.
(Third embodiment)

図４は、この発明の第３実施の形態に係る電力変換装置の断面構造を示す説明図である。図４に示すように、電力変換装置３５は、第１上面電極３６の主面（表面）の上に、金属体３７を介して第２上面電極３８を配置し、第１半導体素子１１と第２半導体素子１２の間に、金属体３７を上下（表裏面）両側から挟み込む第１上面電極３６と第２上面電極３８を介在させている。また、第１配線電極３９と第２配線電極４０を設け、第１半導体素子１１の主面電極又は第１上面電極３６と第１配線電極３９を、第２半導体素子１２の主面電極又は第２上面電極３８と第２配線電極４０を、それぞれボンディングワイヤ４１を用いたワイヤボンディングにより接続する。その他の構成及び作用は、第２実施の形態の電力変換装置３０と同様である。   FIG. 4 is an explanatory diagram showing a cross-sectional structure of a power conversion device according to the third embodiment of the present invention. As shown in FIG. 4, the power conversion device 35 has a second upper surface electrode 38 disposed on the main surface (front surface) of the first upper surface electrode 36 via a metal body 37, and the first semiconductor element 11 and the first semiconductor device 11. The first upper surface electrode 36 and the second upper surface electrode 38 that sandwich the metal body 37 from both the upper and lower (front and back) sides are interposed between the two semiconductor elements 12. In addition, the first wiring electrode 39 and the second wiring electrode 40 are provided, and the main surface electrode of the first semiconductor element 11 or the first upper surface electrode 36 and the first wiring electrode 39 are connected to the main surface electrode of the second semiconductor element 12 or the first electrode. The two upper surface electrodes 38 and the second wiring electrodes 40 are connected by wire bonding using bonding wires 41, respectively. Other configurations and operations are the same as those of the power conversion device 30 of the second embodiment.

この電力変換装置３５を形成する場合、第１半導体素子１１の主面電極上に、中央部に凹部を有する皿形状の第１上面電極３６を実装し、第２半導体素子１２の主面電極上に、中央部に凹部を有する皿形状の第２上面電極３８を実装する。そして、対向配置した第１上面電極３６の凹部と第２上面電極３８の凹部の間に、金属体３７を配置し、第１上面電極３６の凹部と金属体３７、及び第２上面電極３８の凹部と金属体３７を、それぞれ高熱伝導性材料２０で接合する。なお、第１半導体素子１１の主面電極と第１上面電極３６、及び第２半導体素子１２の主面電極と第２上面電極３８は、例えば、はんだ２１を用いたはんだ付けにより接合する。また、高熱伝導性材料２０として、例えば、銀ペースト等の導電性接着剤が用いられる。   When forming this power conversion device 35, a dish-shaped first upper surface electrode 36 having a recess in the center is mounted on the main surface electrode of the first semiconductor element 11, and the main surface electrode of the second semiconductor element 12 is In addition, the dish-shaped second upper surface electrode 38 having a recess at the center is mounted. Then, a metal body 37 is disposed between the concave portion of the first upper surface electrode 36 and the concave portion of the second upper surface electrode 38 that are arranged to face each other, and the concave portion of the first upper surface electrode 36, the metal body 37, and the second upper surface electrode 38. The concave portion and the metal body 37 are joined together by the high thermal conductivity material 20. The main surface electrode of the first semiconductor element 11 and the first upper surface electrode 36 and the main surface electrode of the second semiconductor element 12 and the second upper surface electrode 38 are joined by soldering using, for example, solder 21. Moreover, as the high thermal conductive material 20, for example, a conductive adhesive such as a silver paste is used.

また、第１電力基板１３の他端側に離間して第１配線電極３９を、第２電力基板１４の他端側に離間して、他端側主面が段差面となるように屈曲して形成された第２配線電極４０を、それぞれ設ける。即ち、第１電力基板１３の側方に第１配線電極３９が、第２電力基板１４の側方に第２配線電極４０が、それぞれ並設されている。なお、第１配線電極３９と第２配線電極４０を電気的に接続すれば、第１半導体素子１１の主面電極と第２半導体素子１２の主面電極が電気的に接続される。
上記構成を有する電力変換装置３５は、第２実施の形態の電力変換装置３０の効果に加えて、以下の効果を得ることができる。 Further, the first wiring electrode 39 is spaced apart to the other end side of the first power board 13 and bent to the other end side of the second power board 14 so that the other end side main surface becomes a stepped surface. The second wiring electrodes 40 formed in this manner are provided. That is, the first wiring electrode 39 is provided on the side of the first power board 13, and the second wiring electrode 40 is provided on the side of the second power board 14. If the first wiring electrode 39 and the second wiring electrode 40 are electrically connected, the main surface electrode of the first semiconductor element 11 and the main surface electrode of the second semiconductor element 12 are electrically connected.
The power conversion device 35 having the above configuration can obtain the following effects in addition to the effects of the power conversion device 30 of the second embodiment.

第１に、半導体素子の主面側電極から放熱器に至る熱抵抗を低減した状態で、電力変換装置３５を容易に製造することができる。つまり、両半導体素子１１，１２の上面電極３６，３８同士を高熱伝導性材料２０で接合する際、高熱伝導性材料２０の厚さを百乃至数百μｍ程度に抑えることが望ましい。しかしながら、両半導体素子１１，１２の上面電極３６，３８をこの程度まで単純に近づけると、両上面電極３６，３８同士の接続、或いは半導体素子１１，１２が実装されている第１電力基板１３と第２電力基板１４の間の電気的接続に支障をきたす可能性がある。本構成では、高熱伝導性材料２０を薄く保ったまま、両上面電極３６，３８の間に適宣な間隙を設けることができるので、容易に製造することができる。   1stly, the power converter device 35 can be manufactured easily in the state which reduced the thermal resistance from the main surface side electrode of a semiconductor element to a heat radiator. That is, when the upper surface electrodes 36 and 38 of both the semiconductor elements 11 and 12 are joined together by the high thermal conductivity material 20, it is desirable to suppress the thickness of the high thermal conductivity material 20 to about one hundred to several hundred μm. However, if the upper surface electrodes 36 and 38 of both semiconductor elements 11 and 12 are simply brought close to this extent, the connection between the upper surface electrodes 36 and 38 or the first power substrate 13 on which the semiconductor elements 11 and 12 are mounted and There is a possibility that the electrical connection between the second power boards 14 may be hindered. In this configuration, an appropriate gap can be provided between the upper surface electrodes 36 and 38 while keeping the high thermal conductive material 20 thin, and therefore it can be manufactured easily.

第２に、熱抵抗を更に低減することができる。つまり、金属体３７がヒートスプレッダとして機能するので、熱抵抗を低減することができ、温度上昇を更に抑制することができる。併せて金属体３７が持つ熱容量により、過渡的な発熱による温度上昇を更に抑制することができる。
ここで、例えば、電力変換装置３５が、電動自動車用の３相インバータ回路２３とすると、この３相インバータ回路２３が特に過大な発熱をするのは、電動自動車の発進時等の短時間に限られる可能性が高い。この際、本構成では熱容量を大きくすることができるので、短時間大発熱での温度上昇も効果的に抑制することができる。 Second, the thermal resistance can be further reduced. That is, since the metal body 37 functions as a heat spreader, the thermal resistance can be reduced and the temperature rise can be further suppressed. In addition, due to the heat capacity of the metal body 37, the temperature rise due to transient heat generation can be further suppressed.
Here, for example, if the power conversion device 35 is a three-phase inverter circuit 23 for an electric vehicle, the three-phase inverter circuit 23 generates particularly excessive heat only in a short time such as when the electric vehicle starts. Is likely to be. At this time, since the heat capacity can be increased in this configuration, the temperature increase due to the large heat generation in a short time can be effectively suppressed.

第３に、高熱伝導性材料２０を上面電極３６，３８に塗布する際に、半導体素子の主面電極以外の部分に溢れることを防止できる。即ち、各上面電極３６，３８が、各半導体素子１１，１２の外側部分まで張り出すと共に、高熱伝導性材料２０を塗布する部分は、凹んだ皿形状の領域であるので、各上面電極３６，３８の凹部周辺の皿形状部分が、高熱伝導性材料２０の溢れ出しを防止する。このため、高熱伝導性材料２０が溢れ出たことで各半導体素子１１，１２の主面電極と裏面側電極が短絡してしまうのを、確実、且つ、容易に防止することができる。
なお、各上面電極３６，３８に設けた凹部に金属体３７を配置するので、この凹部が金属体３７の位置合わせ機能を有する。このため、金属体３７を容易に配置することができる。 Third, when the high thermal conductive material 20 is applied to the upper surface electrodes 36 and 38, it is possible to prevent the semiconductor element from overflowing other than the main surface electrode. That is, each upper surface electrode 36, 38 extends to the outer portion of each semiconductor element 11, 12, and the portion to which the high thermal conductivity material 20 is applied is a concave dish-shaped region. The dish-shaped portion around the 38 recesses prevents the high thermal conductivity material 20 from overflowing. For this reason, it is possible to reliably and easily prevent the main surface electrode and the back surface side electrode of each of the semiconductor elements 11 and 12 from being short-circuited due to the overflow of the high thermal conductive material 20.
In addition, since the metal body 37 is disposed in the recess provided in each of the upper surface electrodes 36, 38, the recess has a function of aligning the metal body 37. For this reason, the metal body 37 can be arrange | positioned easily.

更に、各上面電極３６，３８が皿形状で、各半導体素子１１，１２の主面端部に接しない形状とすることが容易であるので、各半導体素子１１，１２の主面電極と主面端部が、各上面電極３６，３８を介して接してしまう事態を確実に防止することができる。
また、各半導体素子１１，１２の主面電極又は各上面電極３６，３８と、各配線電極３９，４０の電気的な接続が容易になる。即ち、各半導体素子１１，１２の主面電極又は各上面電極３６，３８と、各配線電極３９，４０の高さが同じにならない場合もあるが、この場合、各上面電極３６，３８の端部を曲げて各配線電極３９，４０に直接接合しようとしても、曲げ加工精度や接合方法の問題で必ずしも円滑に接続できるわけではない。本構成では、異なる高さの電極間の接続はボンディングワイヤ４１によるワイヤボンディングで行うので、容易に接続することができる。 Furthermore, since each upper surface electrode 36,38 is dish-shaped and it is easy to make it the shape which does not contact the main surface edge part of each semiconductor element 11,12, the main surface electrode and main surface of each semiconductor element 11,12 are obtained. It is possible to reliably prevent the end portion from coming into contact with the upper surface electrodes 36 and 38.
In addition, electrical connection between the main surface electrodes or the upper surface electrodes 36 and 38 of the semiconductor elements 11 and 12 and the wiring electrodes 39 and 40 is facilitated. That is, the heights of the main surface electrodes or upper surface electrodes 36 and 38 of the semiconductor elements 11 and 12 and the wiring electrodes 39 and 40 may not be the same. Even if the portion is bent and directly joined to the wiring electrodes 39 and 40, the connection is not always smooth due to problems in bending accuracy and joining method. In this configuration, since the connection between the electrodes having different heights is performed by wire bonding using the bonding wire 41, the connection can be easily made.

このため、電気的な接続を、一般的なワイヤボンディングにより確実、容易に行った状態で、高熱伝導性材料２０よる結合により、各半導体素子１１，１２の裏面側だけでなく上面側からも放熱することができる。ここで、本構成では、各上面電極３６，３８自体が金属体からなり剛性を有することから、各上面電極３６，３８にワイヤボンディングによりボンディングワイヤ４１を接続することも簡単、且つ、確実にできる。
（第４実施の形態） Therefore, heat is radiated not only from the back surface side but also from the top surface side of each of the semiconductor elements 11 and 12 by bonding with the high thermal conductivity material 20 in a state where the electrical connection is surely and easily performed by general wire bonding. can do. Here, in this structure, since each upper surface electrode 36 and 38 itself consists of a metal body, and has rigidity, it is also easy and reliable to connect the bonding wire 41 to each upper surface electrode 36 and 38 by wire bonding. .
(Fourth embodiment)

図５は、この発明の第４実施の形態に係る電力変換装置の断面構造を示す説明図である。図５に示すように、電力変換装置４５は、第１上面電極３６と第２上面電極３８に代えて、各上面電極３６，３８に金属体３７を配置する凹部を設けずに形成した、第１上面電極４６と第２上面電極４７を有しており、両上面電極４６，４７の少なくとも一方には、主面側に凸部（突形状）を有している。また、この凸部を介して、高熱伝導性材料２０により、第１上面電極４６と第２上面電極４７を接合している。その他の構成及び作用は、第３実施の形態の電力変換装置３５と同様である。   FIG. 5 is an explanatory diagram showing a cross-sectional structure of a power conversion device according to the fourth embodiment of the present invention. As shown in FIG. 5, the power conversion device 45 is formed in place of the first upper surface electrode 36 and the second upper surface electrode 38 without providing a recess for arranging the metal body 37 in each of the upper surface electrodes 36, 38. The first upper surface electrode 46 and the second upper surface electrode 47 are provided, and at least one of the upper surface electrodes 46 and 47 has a convex portion (protruding shape) on the main surface side. Further, the first upper surface electrode 46 and the second upper surface electrode 47 are joined by the high thermal conductivity material 20 through the convex portion. Other configurations and operations are the same as those of the power conversion device 35 of the third embodiment.

この電力変換装置４５を形成する場合、両上面電極４６，４７の少なくとも一方、例えば、第１上面電極４６の主面側に形成された、台状の凸部４６ａ（図５参照）と、第２上面電極４７を対向配置し、凸部４６ａと第２上面電極４７の間に配置した高熱伝導性材料２０を介して、第１上面電極４６と第２上面電極４７を接合する。
上記構成を有する電力変換装置４５は、第３実施の形態の電力変換装置３５の効果に加えて、以下の効果を得ることができる。 When the power converter 45 is formed, at least one of the upper surface electrodes 46 and 47, for example, the main surface side of the first upper surface electrode 46, a table-like convex portion 46a (see FIG. 5), The two upper surface electrodes 47 are arranged opposite to each other, and the first upper surface electrode 46 and the second upper surface electrode 47 are joined via the high thermal conductive material 20 disposed between the convex portion 46 a and the second upper surface electrode 47.
The power conversion device 45 having the above configuration can obtain the following effects in addition to the effects of the power conversion device 35 of the third embodiment.

第１に、凸部を有する上面電極（第１上面電極４６と第２上面電極４７の少なくとも一方）は、電力変換装置３５の中央部に凹部を有する皿形状の上面電極（第１上面電極３６或いは第２上面電極３８）と金属体３７（図４参照）を一体にした構造と見なすことができる。よって、金属体３７を省略することができるので、部品点数の低減と製造工程の簡略化を図ることができる。
なお、第３実施の形態の電力変換装置３５における第１及び第２の効果は、同様に得ることができる。また、各上面電極３６，３８自体は、各半導体素子１１，１２から外側に張り出した形状であるので、電力変換装置３５における第３の効果と同様に、高熱伝導性材料２０の溢れによる各半導体素子１１，１２の主面側電極と裏面側電極の短絡を防止することができる。 First, the upper surface electrode (at least one of the first upper surface electrode 46 and the second upper surface electrode 47) having a convex portion is a dish-shaped upper surface electrode (first upper surface electrode 36) having a concave portion in the central portion of the power converter 35. Or it can be considered that the 2nd upper surface electrode 38) and the metal body 37 (refer FIG. 4) were integrated. Therefore, since the metal body 37 can be omitted, the number of parts can be reduced and the manufacturing process can be simplified.
In addition, the 1st and 2nd effect in the power converter device 35 of 3rd Embodiment can be acquired similarly. Moreover, since each upper surface electrode 36 and 38 itself has a shape protruding outward from each semiconductor element 11 and 12, each semiconductor due to overflow of the high thermal conductivity material 20, as in the third effect in the power converter 35. A short circuit between the main surface side electrode and the back surface side electrode of the elements 11 and 12 can be prevented.

また、電力変換装置３５に比べ高熱伝導性材料２０の塗布層数を減らすことができるので、高熱伝道性材料２０全体を薄くすることができる。よって、熱抵抗を更に低減することができ、各半導体素子１１，１２の温度上昇を抑制することができる。
（第５実施の形態） Moreover, since the number of coating layers of the high thermal conductivity material 20 can be reduced as compared with the power converter 35, the entire high thermal conductivity material 20 can be made thin. Therefore, the thermal resistance can be further reduced, and the temperature rise of each of the semiconductor elements 11 and 12 can be suppressed.
(Fifth embodiment)

図６は、この発明の第５実施の形態に係る電力変換装置の断面構造を示す説明図である。図６に示すように、電力変換装置５０は、第３実施の形態の電力変換装置３５の第１半導体素子１１の主面に絶縁枠５１を、第２半導体素子１２の主面に絶縁枠５２を、それぞれ設け、絶縁枠５１の内側に第１上面電極３６を、絶縁枠５２の内側部分に第２上面電極３８を、それぞれ配置する。また、各絶縁枠５１，５２の外側部分に、第１半導体素子１１と第２半導体素子１２の制御電極を配置する。その他の構成及び作用は、第３実施の形態の電力変換装置３５と同様である。   FIG. 6 is an explanatory view showing a cross-sectional structure of a power converter according to the fifth embodiment of the present invention. As shown in FIG. 6, the power conversion device 50 includes an insulating frame 51 on the main surface of the first semiconductor element 11 and an insulating frame 52 on the main surface of the second semiconductor element 12 of the power conversion device 35 of the third embodiment. The first upper surface electrode 36 is disposed inside the insulating frame 51, and the second upper surface electrode 38 is disposed inside the insulating frame 52. In addition, the control electrodes of the first semiconductor element 11 and the second semiconductor element 12 are arranged on the outer portions of the insulating frames 51 and 52. Other configurations and operations are the same as those of the power conversion device 35 of the third embodiment.

この電力変換装置５０を形成する場合、第１半導体素子１１と第２半導体素子１２の各主面に、共に絶縁材料で形成した絶縁枠５１と絶縁枠５２を、それぞれ実装する。そして、各絶縁枠５１，５２の内側部分に、第１上面電極３６と第２上面電極３８をそれぞれ実装する。更に、各絶縁枠５１，５２の外側部分に、第１半導体素子１１と第２半導体素子１２の制御電極（ゲート電極）を配置する。なお、この実施の形態に係る電力変換装置５０では、ＩＧＢＴ２５である第１半導体素子１１の制御電極とゲート信号基板５３をボンディングワイヤ５４により接続する（第２半導体素子１２はＦＲＤ２６）。
上記構成を有する電力変換装置５０は、第１〜３実施の形態の電力変換装置の効果に加えて、以下の効果を得ることができる。 In the case of forming the power conversion device 50, an insulating frame 51 and an insulating frame 52, both of which are formed of an insulating material, are mounted on the main surfaces of the first semiconductor element 11 and the second semiconductor element 12, respectively. Then, the first upper surface electrode 36 and the second upper surface electrode 38 are mounted on the inner portions of the insulating frames 51 and 52, respectively. Furthermore, the control electrodes (gate electrodes) of the first semiconductor element 11 and the second semiconductor element 12 are arranged on the outer portions of the insulating frames 51 and 52. In the power conversion device 50 according to this embodiment, the control electrode of the first semiconductor element 11 that is the IGBT 25 and the gate signal substrate 53 are connected by the bonding wire 54 (the second semiconductor element 12 is the FRD 26).
The power conversion device 50 having the above configuration can obtain the following effects in addition to the effects of the power conversion devices of the first to third embodiments.

各半導体素子１１，１２の主面電極は、各絶縁枠５１，５２の内側で各上面電極３６，３８に接続され、各半導体素子１１，１２の主面側に設けられている制御端子は、各絶縁枠５１，５２の外側、即ち、各絶縁枠５１，５２で主面電極と仕切られた領域に位置することになる。よって、制御端子が、この主面端子と各上面電極３６，３８を接合する際の実装材料、つまり、はんだ材料や高熱伝導性材料に接触してしまうことを確実に防止することができる。   The main surface electrode of each semiconductor element 11, 12 is connected to each upper surface electrode 36, 38 inside each insulating frame 51, 52, and the control terminal provided on the main surface side of each semiconductor element 11, 12 is It is located outside each insulating frame 51, 52, that is, in a region partitioned from the main surface electrode by each insulating frame 51, 52. Therefore, it is possible to reliably prevent the control terminal from coming into contact with the mounting material when joining the main surface terminal and the upper surface electrodes 36, 38, that is, the solder material or the high thermal conductivity material.

なお、上述した各実施の形態は、何れも電力基板として金属板を想定し、この金属板を絶縁領域を介して放熱器上に実装する構成で説明した。しかしながら、本発明は、上記構成に限らず、電力基板として表面に金属領域を有する絶縁基板を用いて、この金属領域上に半導体素子を実装しても良い。また、この絶縁基板は、直接或いはベースプレートを介して放熱器上に実装すればよい。
また、各実施の形態は、電力変換回路について説明したが、電力変換回路に限らず、スイッチング電源回路、Ｈブリッジ回路等にも適用することができる。 In each of the above-described embodiments, a metal plate is assumed as a power board, and the metal plate is mounted on a radiator via an insulating region. However, the present invention is not limited to the above configuration, and an insulating substrate having a metal region on the surface may be used as a power substrate, and a semiconductor element may be mounted on the metal region. In addition, this insulating substrate may be mounted on the radiator directly or via a base plate.
Moreover, although each embodiment demonstrated the power converter circuit, it is applicable not only to a power converter circuit but a switching power supply circuit, an H bridge circuit, etc.

この発明の第１実施の形態に係る電力変換装置の断面構造を示す説明図である。It is explanatory drawing which shows the cross-section of the power converter device which concerns on 1st Embodiment of this invention. 図１の電力変換装置により形成したスイッチ回路を用いた３相インバータ回路の回路図である。It is a circuit diagram of the three-phase inverter circuit using the switch circuit formed with the power converter device of FIG. この発明の第２実施の形態に係る電力変換装置の断面構造を示す説明図である。It is explanatory drawing which shows the cross-section of the power converter device which concerns on 2nd Embodiment of this invention. この発明の第３実施の形態に係る電力変換装置の断面構造を示す説明図である。It is explanatory drawing which shows the cross-section of the power converter device which concerns on 3rd Embodiment of this invention. この発明の第４実施の形態に係る電力変換装置の断面構造を示す説明図である。It is explanatory drawing which shows the cross-section of the power converter device which concerns on 4th Embodiment of this invention. この発明の第５実施の形態に係る電力変換装置の断面構造を示す説明図である。It is explanatory drawing which shows the cross-section of the power converter device which concerns on 5th Embodiment of this invention. 従来の半導体装置の構成を示す断面説明図である。It is sectional explanatory drawing which shows the structure of the conventional semiconductor device.

符号の説明Explanation of symbols

１０，３０，３５，４５，５０ 電力変換装置
１１ 第１半導体素子
１２ 第２半導体素子
１３ 第１電力基板
１４ 第２電力基板
１５ 第１放熱器
１６ 第２放熱器
１７，１８ 絶縁領域
１９，３６，４６ 第１上面電極
２０ 高熱伝導性材料
２１ はんだ
２２ スイッチ回路
２３ ３相インバータ回路
２４ 電動機
２５ ＩＧＢＴ
２６ ＦＲＤ
２７ 平滑コンデンサ
２８ 電源
３１，３８，４７ 第２上面電極
３７ 金属体
３９ 第１配線電極
４０ 第２配線電極
４１，５４ ボンディングワイヤ
４２ 第１絶縁層
４３ 第２絶縁層
４６ａ 凸部
５１，５２ 絶縁枠
５３ ゲート信号基板 10, 30, 35, 45, 50 Power conversion device 11 First semiconductor element 12 Second semiconductor element 13 First power board 14 Second power board 15 First radiator 16 Second radiator 17, 18 Insulating region 19, 36 , 46 First upper surface electrode 20 High thermal conductivity material 21 Solder 22 Switch circuit 23 Three-phase inverter circuit 24 Electric motor 25 IGBT
26 FRD
27 Smoothing capacitor 28 Power supply 31, 38, 47 Second upper surface electrode 37 Metal body 39 First wiring electrode 40 Second wiring electrode 41, 54 Bonding wire 42 First insulating layer 43 Second insulating layer 46a Convex portion 51, 52 Insulating frame 53 Gate signal board

Claims (10)

主面電極同士が電気的に同電位の第１半導体素子及び第２半導体素子と、
第１基板を介して前記第１半導体素子を積層した第１放熱器と、
前記第１基板と主面同士を対向配置して接合した第２基板を介して前記第２半導体素子を積層した第２放熱器と、
前記第１半導体素子と前記第１半導体素子に対向配置した前記第２半導体素子との間に積層され、前記第２半導体素子の主面電極に高熱伝導性材料で接合した第１上面電極と
を有する半導体装置。 A first semiconductor element and a second semiconductor element whose main surface electrodes are electrically at the same potential;
A first radiator in which the first semiconductor elements are stacked via a first substrate;
A second radiator in which the second semiconductor element is stacked through a second substrate in which the first substrate and the main surfaces are arranged opposite to each other and bonded;
A first upper surface electrode laminated between the first semiconductor element and the second semiconductor element disposed opposite to the first semiconductor element, and joined to a main surface electrode of the second semiconductor element with a high thermal conductivity material; A semiconductor device having the same. 前記第１基板は前記第１放熱器の上に、前記第２基板は前記第２放熱器の上に、それぞれ直接又は絶縁領域或いはベースプレートを介して接合されている請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first substrate is joined to the first radiator and the second substrate is joined to the second radiator directly or through an insulating region or a base plate. . 前記第１半導体素子と前記第２半導体素子は、同一の電気的動作をしない請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element do not perform the same electrical operation. 前記第２半導体素子の主面に高熱伝導性材料により接合されて、前記第１上面電極と電気的に接続される第２上面電極を有する請求項１から３のいずれか一項に記載の半導体装置。   4. The semiconductor according to claim 1, further comprising a second upper surface electrode joined to a main surface of the second semiconductor element by a high thermal conductivity material and electrically connected to the first upper surface electrode. 5. apparatus. 前記第１上面電極の主面及び前記第２上面電極の主面に凹部を形成し、対向する両凹部の間に配置されて両凹部と高熱伝導性材料により接合された金属体を有する請求項４に記載の半導体装置。   A concave body is formed in a main surface of the first upper surface electrode and a main surface of the second upper surface electrode, and the metal body is disposed between the opposing concave portions and joined to both the concave portions by a high thermal conductive material. 5. The semiconductor device according to 4. 前記第１上面電極及び前記第２上面電極の少なくとも一方の主面側に形成した凸部を介して、前記第１上面電極及び前記第２上面電極を高熱伝導性材料で接合する請求項４に記載の半導体装置。   The said 1st upper surface electrode and the said 2nd upper surface electrode are joined with a highly heat conductive material through the convex part formed in the at least one main surface side of the said 1st upper surface electrode and the said 2nd upper surface electrode. The semiconductor device described. 前記第１半導体素子の主面電極又は前記第１上面電極と、前記第１電力基板に並設した第１配線電極を、前記第２半導体素子の主面電極又は前記第２上面電極と、前記第２電力基板に並設した第２配線電極を、それぞれワイヤボンディングにより接続する請求項１から６のいずれか一項に記載の半導体装置。   The main surface electrode of the first semiconductor element or the first upper surface electrode, and the first wiring electrode arranged side by side on the first power substrate, the main surface electrode of the second semiconductor element or the second upper surface electrode, The semiconductor device according to claim 1, wherein the second wiring electrodes arranged in parallel on the second power substrate are connected by wire bonding. 前記第１半導体素子及び前記第２半導体素子の各主面に、前記第１上面電極及び前記第２上面電極を内側に位置させ、前記第１半導体素子及び前記第２半導体素子の各制御電極を外側に位置させる、絶縁枠を形成した請求項１から７のいずれか一項に記載の半導体装置。   The first upper surface electrode and the second upper surface electrode are positioned inside the main surfaces of the first semiconductor element and the second semiconductor element, and the control electrodes of the first semiconductor element and the second semiconductor element are provided The semiconductor device according to claim 1, wherein an insulating frame is formed on an outer side. 前記高熱伝導性材料が導電性接着剤である請求項１から８のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the high thermal conductivity material is a conductive adhesive. 請求項１から９のいずれか一項に記載の半導体装置の前記第１半導体素子を絶縁ゲート型バイポーラトランジスタとし、前記第２半導体素子をダイオードとして、
前記第１半導体素子と前記第２半導体素子の主面電極同士を電気的に接続すると共に、前記第１半導体素子と前記第２半導体素子の裏面電極同士を電気的に接続することによりスイッチ回路を形成し、
前記スイッチ回路を複数個用いてインバータ回路を形成した電力変換装置。 The semiconductor device according to any one of claims 1 to 9, wherein the first semiconductor element is an insulated gate bipolar transistor, and the second semiconductor element is a diode.
A main circuit electrode of the first semiconductor element and the second semiconductor element are electrically connected to each other, and a back circuit electrode of the first semiconductor element and the second semiconductor element are electrically connected to each other to form a switch circuit. Forming,
A power converter in which an inverter circuit is formed by using a plurality of the switch circuits.
JP2006216952A 2006-08-09 2006-08-09 Semiconductor device and power conversion device Active JP4973059B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006216952A JP4973059B2 (en) 2006-08-09 2006-08-09 Semiconductor device and power conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006216952A JP4973059B2 (en) 2006-08-09 2006-08-09 Semiconductor device and power conversion device

Publications (2)

Publication Number Publication Date
JP2008042074A true JP2008042074A (en) 2008-02-21
JP4973059B2 JP4973059B2 (en) 2012-07-11

Family

ID=39176721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006216952A Active JP4973059B2 (en) 2006-08-09 2006-08-09 Semiconductor device and power conversion device

Country Status (1)

Country Link
JP (1) JP4973059B2 (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010062492A (en) * 2008-09-08 2010-03-18 Denso Corp Semiconductor device
JP2011003636A (en) * 2009-06-17 2011-01-06 Toyota Motor Corp Semiconductor device
JP2011258632A (en) * 2010-06-07 2011-12-22 Nissan Motor Co Ltd Semiconductor device
DE112009005394T5 (en) 2009-11-25 2012-09-27 Toyota Jidosha Kabushiki Kaisha Cooling structure of a semiconductor device
ITMI20120711A1 (en) * 2012-04-27 2013-10-28 St Microelectronics Srl POWER DEVICE
JP2014096412A (en) * 2012-11-07 2014-05-22 Toyota Motor Corp Semiconductor module
WO2014173801A1 (en) * 2013-04-25 2014-10-30 Conti Temic Microelectronic Gmbh Power module, power converter and drive arrangement with a power module
US8890313B2 (en) 2012-04-27 2014-11-18 Stmicroelectronics S.R.L. Through-hole electronic device with double heat-sink
JP2015027133A (en) * 2013-07-24 2015-02-05 株式会社デンソー Power-supply device
EP2624294A4 (en) * 2011-10-12 2015-06-17 Ngk Insulators Ltd Circuit board for large-capacity module peripheral circuit and large-capacity module containing peripheral circuit using said circuit board
US9125322B2 (en) 2012-04-27 2015-09-01 Stmicroelectronics S.R.L. Through-hole mounting system with heat sinking elements clamped to one another against insulating body
US9171773B2 (en) 2013-07-03 2015-10-27 Mitsubishi Electric Corporation Semiconductor device
CN110137167A (en) * 2018-02-09 2019-08-16 本田技研工业株式会社 Cell
WO2020184383A1 (en) * 2019-03-12 2020-09-17 住友電気工業株式会社 Semiconductor device
CN113013113A (en) * 2021-02-22 2021-06-22 合肥仙湖半导体科技有限公司 Stacked integrated circuit chip and packaging method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795388B (en) * 2015-03-23 2017-11-14 广东美的制冷设备有限公司 SPM and its manufacture method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000174180A (en) * 1998-12-02 2000-06-23 Shibafu Engineering Kk Semiconductor device
JP2001352023A (en) * 2000-06-08 2001-12-21 Denso Corp Refrigerant cooling double-faced cooling semiconductor device
JP2002208673A (en) * 2001-01-10 2002-07-26 Mitsubishi Electric Corp Semiconductor device and power module
JP2004158489A (en) * 2002-11-01 2004-06-03 Honda Motor Co Ltd Pressure contact semiconductor device
JP2004193476A (en) * 2002-12-13 2004-07-08 Denso Corp Semiconductor device
JP2005302951A (en) * 2004-04-09 2005-10-27 Toshiba Corp Semiconductor device package for power
JP2005340639A (en) * 2004-05-28 2005-12-08 Toyota Industries Corp Semiconductor device and three-phase inverter device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000174180A (en) * 1998-12-02 2000-06-23 Shibafu Engineering Kk Semiconductor device
JP2001352023A (en) * 2000-06-08 2001-12-21 Denso Corp Refrigerant cooling double-faced cooling semiconductor device
JP2002208673A (en) * 2001-01-10 2002-07-26 Mitsubishi Electric Corp Semiconductor device and power module
JP2004158489A (en) * 2002-11-01 2004-06-03 Honda Motor Co Ltd Pressure contact semiconductor device
JP2004193476A (en) * 2002-12-13 2004-07-08 Denso Corp Semiconductor device
JP2005302951A (en) * 2004-04-09 2005-10-27 Toshiba Corp Semiconductor device package for power
JP2005340639A (en) * 2004-05-28 2005-12-08 Toyota Industries Corp Semiconductor device and three-phase inverter device

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010062492A (en) * 2008-09-08 2010-03-18 Denso Corp Semiconductor device
JP2011003636A (en) * 2009-06-17 2011-01-06 Toyota Motor Corp Semiconductor device
DE112009005394T5 (en) 2009-11-25 2012-09-27 Toyota Jidosha Kabushiki Kaisha Cooling structure of a semiconductor device
JP2011258632A (en) * 2010-06-07 2011-12-22 Nissan Motor Co Ltd Semiconductor device
EP2624294A4 (en) * 2011-10-12 2015-06-17 Ngk Insulators Ltd Circuit board for large-capacity module peripheral circuit and large-capacity module containing peripheral circuit using said circuit board
US9125322B2 (en) 2012-04-27 2015-09-01 Stmicroelectronics S.R.L. Through-hole mounting system with heat sinking elements clamped to one another against insulating body
ITMI20120711A1 (en) * 2012-04-27 2013-10-28 St Microelectronics Srl POWER DEVICE
US8890313B2 (en) 2012-04-27 2014-11-18 Stmicroelectronics S.R.L. Through-hole electronic device with double heat-sink
US9202766B2 (en) 2012-04-27 2015-12-01 Stmicroelectronics S.R.L. Package for power device and method of making the same
JP2014096412A (en) * 2012-11-07 2014-05-22 Toyota Motor Corp Semiconductor module
WO2014173801A1 (en) * 2013-04-25 2014-10-30 Conti Temic Microelectronic Gmbh Power module, power converter and drive arrangement with a power module
US20160105004A1 (en) * 2013-04-25 2016-04-14 Conti Temic Microelectronic Gmbh Power Module, Power Converter and Drive Arrangement With A Power Module
JP2016523069A (en) * 2013-04-25 2016-08-04 コンティ テミック マイクロエレクトロニック ゲゼルシャフト ミット ベシュレンクテル ハフツングＣｏｎｔｉ Ｔｅｍｉｃ ｍｉｃｒｏｅｌｅｃｔｒｏｎｉｃ ＧｍｂＨ POWER MODULE, POWER CONVERTER, AND DRIVE DEVICE PROVIDED WITH POWER MODULE
US10027094B2 (en) * 2013-04-25 2018-07-17 Conti Temic Microelectronic Gmbh Power module, power converter and drive arrangement with a power module
US9171773B2 (en) 2013-07-03 2015-10-27 Mitsubishi Electric Corporation Semiconductor device
JP2015027133A (en) * 2013-07-24 2015-02-05 株式会社デンソー Power-supply device
US9293994B2 (en) 2013-07-24 2016-03-22 Denso Corporation Electric power source device equipped with transformer
CN110137167A (en) * 2018-02-09 2019-08-16 本田技研工业株式会社 Cell
JP2019140254A (en) * 2018-02-09 2019-08-22 本田技研工業株式会社 Element unit
US10658942B2 (en) 2018-02-09 2020-05-19 Honda Motor Co., Ltd. Element unit
CN110137167B (en) * 2018-02-09 2023-04-07 本田技研工业株式会社 Element unit
WO2020184383A1 (en) * 2019-03-12 2020-09-17 住友電気工業株式会社 Semiconductor device
US11881524B2 (en) 2019-03-12 2024-01-23 Sumitomo Electric Industries, Ltd. Semiconductor device
CN113013113A (en) * 2021-02-22 2021-06-22 合肥仙湖半导体科技有限公司 Stacked integrated circuit chip and packaging method thereof

Also Published As

Publication number Publication date
JP4973059B2 (en) 2012-07-11

Similar Documents

Publication Publication Date Title
JP4973059B2 (en) Semiconductor device and power conversion device
EP3107120B1 (en) Power semiconductor module
JP4438489B2 (en) Semiconductor device
JP5434986B2 (en) Semiconductor module and semiconductor device including the same
WO2013021647A1 (en) Semiconductor module, semiconductor device provided with semiconductor module, and method for manufacturing semiconductor module
WO2013018343A1 (en) Semiconductor module and inverter having semiconductor module mounted thereon
JP6096614B2 (en) Power semiconductor module and power converter using the same
CN110506330B (en) Power electronic module and electric power converter comprising the same
US11296054B2 (en) Power converter module and method for production thereof
JP6610568B2 (en) Semiconductor device
JPWO2013171946A1 (en) Semiconductor device manufacturing method and semiconductor device
JP2015099846A (en) Semiconductor device, and method of manufacturing the same
JP2007068302A (en) Power semiconductor device and semiconductor power converter
WO2020184053A1 (en) Semiconductor device
JP2007173703A (en) Semiconductor device
JP2011115020A (en) Power unit
JP5217015B2 (en) Power converter and manufacturing method thereof
US9698076B1 (en) Metal slugs for double-sided cooling of power module
JP5840102B2 (en) Power semiconductor device
JP5028907B2 (en) Semiconductor device and power conversion device
JP5125530B2 (en) Power converter
JP2011023748A (en) Electronic apparatus
JP6906583B2 (en) Semiconductor power module
JP2013214783A (en) Semiconductor device and manufacturing method of member for electrode
JP6952824B2 (en) Power modules and power semiconductor devices using them

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090326

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091027

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20111117

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111227

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120223

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120313

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120326

R150 Certificate of patent or registration of utility model

Ref document number: 4973059

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150420

Year of fee payment: 3

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20130213