JP2006278598A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006278598A
JP2006278598A JP2005093566A JP2005093566A JP2006278598A JP 2006278598 A JP2006278598 A JP 2006278598A JP 2005093566 A JP2005093566 A JP 2005093566A JP 2005093566 A JP2005093566 A JP 2005093566A JP 2006278598 A JP2006278598 A JP 2006278598A
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insulating substrate
spacer
solder layer
semiconductor device
semiconductor element
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JP4704084B2 (en
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Shinji Akiyama
真治 秋山
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/364—Polymers
    • H01L2924/3641—Outgassing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where a base plate and an insulating substrate are fixed in a solder layer in almost parallel and air bubbles do not remain in the solder layer, a semiconductor element and the insulating substrate are fixed in the solder layer in almost parallel, and the air bubbles do not remain in the solder layer. <P>SOLUTION: In the semiconductor device where the semiconductor element is fixed to a surface of the insulating substrate in the solder layer and a rear face of the insulating substrate is fixed to the base plate in the solder layer, spacers which are arranged between the insulating substrate and the base plate and which keep an interval to be constant are arranged at least in four corners of the rear face of the insulating substrate. The spacers are arranged in a space formed by moving the bonding region of the rear face of the insulating substrate and the spacer to a normal direction of the rear face. The spacers may be arranged between the semiconductor element and the insulating substrate to keep the interval almost constant. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、スイッチング用の半導体装置に関し、特に、半導体素子と絶縁基板との間、絶縁基板とベース板との間が半田層で固定された半導体装置に関する。   The present invention relates to a semiconductor device for switching, and more particularly to a semiconductor device in which a semiconductor element and an insulating substrate are fixed, and between the insulating substrate and a base plate are fixed by a solder layer.

スイッチング用の半導体装置では、半導体素子が載置された絶縁基板が、ベース板の上に半田層で固定される。この場合、ベース板の表面と絶縁基板の裏面とが略平行となるように、絶縁基板の裏面の四隅にアルミニウムワイヤでバンプを形成したり、ベース板上に球状の金属粒子を配置することにより、これらをスペーサに用いてベース板と絶縁基板との間隔を略一定に保持しながら両者を半田で固定していた（例えば、特許文献１参照）。
また、ベース板上に絶縁基板を半田層で固定する工程では、半田層中に気泡が混入して半田層の亀裂や剥離の原因となるため、真空雰囲気中で気泡を除去する真空脱泡法や、ベース板等を振動させて気泡を除去するスクラブ法が用いられていた。
特許第２８１０２８５号公報 In a semiconductor device for switching, an insulating substrate on which a semiconductor element is placed is fixed on a base plate with a solder layer. In this case, bumps are formed with aluminum wires at the four corners of the back surface of the insulating substrate so that the surface of the base plate and the back surface of the insulating substrate are substantially parallel, or spherical metal particles are disposed on the base plate. These are used as spacers, and the distance between the base plate and the insulating substrate is kept substantially constant, and both are fixed with solder (for example, see Patent Document 1).
Also, in the process of fixing the insulating substrate with the solder layer on the base plate, air bubbles are mixed in the solder layer, causing cracks and peeling of the solder layer. Alternatively, a scrub method is used in which bubbles are removed by vibrating a base plate or the like.
Japanese Patent No. 2810285

アルミニウムワイヤのバンプや球状の金属粒子が半田層中に存在すると、真空脱泡法やスクラブ法を用いても、気泡がバンプ等に付着して半田層中に留まり、脱泡が不十分になった。半田層中に残った気泡は、半田層の亀裂や剥離を誘発し、半導体装置の信頼性を低下させるという問題があった。   If aluminum wire bumps or spherical metal particles are present in the solder layer, even if vacuum defoaming or scrubbing is used, bubbles will adhere to the bump and remain in the solder layer, resulting in insufficient defoaming. It was. Bubbles remaining in the solder layer induce cracks and peeling of the solder layer, and have a problem of reducing the reliability of the semiconductor device.

そこで、本発明は、ベース板と絶縁基板とが略平行に半田層で固定され、かつ半田層の中に気泡が残存しない半導体装置の提供を目的とする。また、半導体素子と絶縁基板とが略平行に半田層で固定され、かつ半田層の中に気泡が残存しない半導体装置の提供を目的とする。   Accordingly, an object of the present invention is to provide a semiconductor device in which a base plate and an insulating substrate are fixed substantially in parallel with a solder layer, and no bubbles remain in the solder layer. It is another object of the present invention to provide a semiconductor device in which a semiconductor element and an insulating substrate are fixed substantially in parallel with a solder layer and no bubbles remain in the solder layer.

本発明は、絶縁基板の表面に半導体素子が半田層で固定され、絶縁基板の裏面がベース板に半田層で固定された半導体装置であって、絶縁基板の裏面の少なくとも四隅に、絶縁基板とベース板との間に配置されてその間隔を略一定に保つスペーサを備え、スペーサが、絶縁基板の裏面とスペーサとの接合領域を裏面の法線方向に移動させてできる空間内に設けられたことを特徴とする半導体装置である。かかるスペーサは半導体素子と絶縁基板との間に配置されて、その間隔を略一定に保つものであっても良い。   The present invention is a semiconductor device in which a semiconductor element is fixed to a surface of an insulating substrate with a solder layer, and a back surface of the insulating substrate is fixed to a base plate with a solder layer, and at least four corners of the back surface of the insulating substrate, A spacer is provided between the base plate and the spacer so as to keep the distance substantially constant, and the spacer is provided in a space formed by moving the bonding area between the back surface of the insulating substrate and the spacer in the normal direction of the back surface. This is a semiconductor device. Such a spacer may be disposed between the semiconductor element and the insulating substrate and keep the distance substantially constant.

以上のように、本発明にかかる半導体装置では、気泡の残存しない半田層により、半導体素子と絶縁基板、ベース板と絶縁基板とを略平行に固定することができ、半田層の亀裂や剥離の無い半導体装置の提供が可能となる。   As described above, in the semiconductor device according to the present invention, the semiconductor element and the insulating substrate, the base plate and the insulating substrate can be fixed substantially in parallel by the solder layer in which bubbles do not remain, and the solder layer is not cracked or peeled off. It is possible to provide a semiconductor device that does not have any semiconductor devices.

以下に、図面を参照しながら、本発明の好適な実施の形態について説明する。なお、以下の説明では、「上」、「下」、「左」、「右」およびこれらの用語を含む名称を適宜使用するが、これらの方向は図面を参照した発明の理解を容易にするために用いるものであり、実施形態を上下反転、あるいは任意の方向に回転した形態も、当然に本願発明の技術的範囲に含まれる。   Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, “top”, “bottom”, “left”, “right” and names including these terms are used as appropriate, but these directions facilitate understanding of the invention with reference to the drawings. Therefore, a mode in which the embodiment is inverted upside down or rotated in an arbitrary direction is naturally included in the technical scope of the present invention.

実施の形態１．
図１は、全体が１００で表される、本実施の形態１にかかる半導体装置の側面図である。半導体装置１００は、例えば銅からなるベース板１を含む。ベース板の上には、例えばＰｂ−Ｓｎ系の半田層２により絶縁基板３が固定されている。絶縁基板３は、例えばアルミナからなり、表面には回路パターン（図示せず）が形成されている。更に、絶縁基板３の上に形成された回路パターンの上に、例えばＰｂ−Ｓｎ系の半田層４により半導体素子５が固定されている。半導体素子５は、例えばＦＥＴやＩＧＢＴである。 Embodiment 1 FIG.
FIG. 1 is a side view of the semiconductor device according to the first embodiment, the whole being represented by 100. The semiconductor device 100 includes a base plate 1 made of, for example, copper. On the base plate, an insulating substrate 3 is fixed by, for example, a Pb—Sn solder layer 2. The insulating substrate 3 is made of alumina, for example, and a circuit pattern (not shown) is formed on the surface. Furthermore, a semiconductor element 5 is fixed on a circuit pattern formed on the insulating substrate 3 by, for example, a Pb—Sn solder layer 4. The semiconductor element 5 is, for example, an FET or an IGBT.

図２は、半導体装置１００に使用される絶縁基板３であり、（ａ）に裏面図、（ｂ）に側面図を示す。図１では半田層２に覆われて見えないが、絶縁基板３の裏面の四隅には、略円柱状のスペーサ１３が固定されている。４つのスペーサ１３は同一形状である。   2A and 2B show an insulating substrate 3 used in the semiconductor device 100. FIG. 2A shows a back view and FIG. 2B shows a side view. In FIG. 1, a substantially cylindrical spacer 13 is fixed to the four corners of the back surface of the insulating substrate 3 although it is not visible because it is covered with the solder layer 2. The four spacers 13 have the same shape.

スペーサ１３の材料には、従来のようなアルミニウム等の金属の他、フォトレジストやポリイミドのような樹脂材料や、ガラスコーティング等に用いられるガラス材料が用いられる。   As the material of the spacer 13, in addition to a conventional metal such as aluminum, a resin material such as photoresist or polyimide, or a glass material used for glass coating or the like is used.

図２では、絶縁基板３の裏面の四隅にそれぞれスペーサ１３を設けたが、例えば、図３に示すように、絶縁基板３の裏面の周辺部に沿って、更にスペーサ１３を設けても構わない。   In FIG. 2, the spacers 13 are provided at the four corners of the back surface of the insulating substrate 3. However, for example, as shown in FIG. 3, the spacers 13 may be further provided along the peripheral portion of the back surface of the insulating substrate 3. .

図４は、本実施の形態１にかかるスペーサ１３を用いてベース板１上に絶縁基板３を半田層２で固定する場合の、気泡１０の動きである。図４（ａ）は側面図、（ｂ）は絶縁基板３の裏面図で、内部が理解しやすいように半田層２は透明に描いてある。スペーサ１３は、絶縁基板３とベース板１との間に配置されて、その間隔を略一定に保つ役割を果たす。   FIG. 4 shows the movement of the bubbles 10 when the insulating substrate 3 is fixed on the base plate 1 with the solder layer 2 using the spacer 13 according to the first embodiment. 4A is a side view and FIG. 4B is a rear view of the insulating substrate 3. The solder layer 2 is drawn transparent so that the inside can be easily understood. The spacer 13 is disposed between the insulating substrate 3 and the base plate 1 and plays a role of keeping the interval substantially constant.

一方、図５は、従来どおり、アルミニウムワイヤのバンプをスペーサ４３に用いたてベース板１上に絶縁基板３を半田層２で固定する場合の、気泡１０の動きである。図５（ａ）は側面図、（ｂ）は絶縁基板３の裏面図であり、半田層２は透明に描いてある。   On the other hand, FIG. 5 shows the movement of the bubbles 10 when the insulating substrate 3 is fixed to the base plate 1 with the solder layer 2 using the bumps of the aluminum wire as the spacers 43 as in the prior art. 5A is a side view, FIG. 5B is a back view of the insulating substrate 3, and the solder layer 2 is drawn transparently.

ベース板１上に絶縁基板３を半田層で固定する工程では、ベース板１の上面にクリーム状の半田材を塗布し、その上に絶縁基板３を載せる。かかる状態で、例えば２６５℃の加熱炉に入れて半田材を溶かす。同時に、スクラブ法等で半田材中の気泡を取り除く。
最後に加熱炉から取り出して冷却することにより、ベース板１と絶縁基板３との間隔がスペーサ１３で所定の間隔に保持された状態で半田層２が固化して、両者が接合される。 In the step of fixing the insulating substrate 3 on the base plate 1 with a solder layer, a cream-like solder material is applied to the upper surface of the base plate 1 and the insulating substrate 3 is placed thereon. In this state, the solder material is melted in a heating furnace at 265 ° C., for example. At the same time, bubbles in the solder material are removed by a scrub method or the like.
Finally, by taking out from the heating furnace and cooling, the solder layer 2 is solidified in a state in which the distance between the base plate 1 and the insulating substrate 3 is maintained at a predetermined distance by the spacer 13, and the two are joined.

かかる工程において、本実施の形態１にかかるスペーサ１３を用いた場合、図４（ｂ）中に矢印Ａで示すように、スペーサ１３近傍を通る気泡１０も、半田層２の外部に逃がすことができる。
これに対して、従来のスペーサ４３を用いた場合は、図５（ｂ）中に矢印Ｂで示すように、スペーサ４３近傍を通る気泡１０はスペーサ４３に付着して半田層２中に残留する。 In this process, when the spacer 13 according to the first embodiment is used, as shown by an arrow A in FIG. 4B, the bubbles 10 that pass through the vicinity of the spacer 13 can also escape to the outside of the solder layer 2. it can.
On the other hand, when the conventional spacer 43 is used, as indicated by an arrow B in FIG. 5B, the bubbles 10 passing near the spacer 43 adhere to the spacer 43 and remain in the solder layer 2. .

本実施の形態１にかかる半導体装置１００では、絶縁基板３の裏面とスペーサ１３との接合領域を、絶縁基板３の裏面の法線方向に移動させてできる空間内に入るように、スペーサ１３が設けられている。このため、従来のスペーサ４３のように、絶縁基板３とスペーサ１３との間に凹部が形成され、その凹部に気泡１０が付着することがない。従って、スクラブ法等による脱泡工程で、気泡を容易に半導体層２から外部に逃がすことができ、気泡の残存しない半田層２を得ることができる。
なお、半田層２中では、浮力により気泡は上方に位置するため、絶縁基板３とスペーサ１３との間に凹部を設けないことが有効である。 In the semiconductor device 100 according to the first embodiment, the spacer 13 is placed in a space formed by moving the junction region between the back surface of the insulating substrate 3 and the spacer 13 in the normal direction of the back surface of the insulating substrate 3. Is provided. For this reason, unlike the conventional spacer 43, a recessed part is formed between the insulating substrate 3 and the spacer 13, and the bubble 10 does not adhere to the recessed part. Therefore, in the defoaming step by the scrub method or the like, the bubbles can be easily released from the semiconductor layer 2 to the outside, and the solder layer 2 in which no bubbles remain can be obtained.
In the solder layer 2, since bubbles are located above due to buoyancy, it is effective not to provide a recess between the insulating substrate 3 and the spacer 13.

スペーサ１３の、半田層２と接する面（例えば、円柱状のスペーサでは側面）は、角部を有しない曲面であることが好ましい。曲面とすることにより、気泡１０が付着しにくくなるためである。
ただし、スペーサ１３の形状を三角柱として、３つの頂点の１つが絶縁基板の中心方向に向くように配置することも可能である。 The surface of the spacer 13 in contact with the solder layer 2 (for example, a side surface in the case of a columnar spacer) is preferably a curved surface having no corners. This is because the bubbles 10 are less likely to adhere by using a curved surface.
However, it is also possible to arrange the spacer 13 in a triangular prism so that one of the three apexes faces the center of the insulating substrate.

図６は、本実施の形態１にかかる半導体装置１００に含まれる他の絶縁基板であり、（ａ）が裏面図、（ｂ）が側面図である。
図６に示すように、スペーサ２３を半球形状として、円形の平坦面を絶縁基板３と接合させても良い。 6A and 6B are other insulating substrates included in the semiconductor device 100 according to the first embodiment. FIG. 6A is a back view and FIG. 6B is a side view.
As shown in FIG. 6, the spacer 23 may be hemispherical, and a circular flat surface may be bonded to the insulating substrate 3.

なお、本実施の形態１では、絶縁基板３の裏面に、別途作製したスペーサ１３、２３を取り付ける態様について説明したが、絶縁基板３の裏面をエッチングして一部を突出させることにより、スペーサを形成しても構わない。   In the first embodiment, the mode in which spacers 13 and 23 that are separately manufactured are attached to the back surface of the insulating substrate 3 has been described. However, by etching the back surface of the insulating substrate 3 and partially protruding the spacers, It may be formed.

実施の形態２．
実施の形態２では、図１に示す半導体装置１００の、半導体素子５の裏面にスペーサ１５が固定される。
図７は、本実施の形態２にかかる半導体装置の一部を示す図であり、（ａ）に側面図、（ｂ）に半導体素子５の裏面図を示す。このように、半導体素子５と絶縁基板３との間にスペーサ１５を配置することにより、両者の間隔を略一定に保持しながら、気泡が混入しない半田層４で両者を接合することができる。 Embodiment 2. FIG.
In the second embodiment, the spacer 15 is fixed to the back surface of the semiconductor element 5 of the semiconductor device 100 shown in FIG.
7A and 7B are diagrams showing a part of the semiconductor device according to the second embodiment. FIG. 7A is a side view and FIG. 7B is a back view of the semiconductor element 5. In this way, by arranging the spacer 15 between the semiconductor element 5 and the insulating substrate 3, both can be joined by the solder layer 4 in which bubbles are not mixed while the distance between the two is kept substantially constant.

なお、スペーサ１５の形状や材料、配置する位置は、実施の形態１の場合と同様である。また、スペーサ１５は、半導体素子５とは別に作製して半導体素子５の裏面に取り付けても良いし、半導体素子５の裏面をエッチングして形成しても構わない。   The shape, material, and position of the spacer 15 are the same as those in the first embodiment. The spacer 15 may be manufactured separately from the semiconductor element 5 and attached to the back surface of the semiconductor element 5, or may be formed by etching the back surface of the semiconductor element 5.

特に、スペーサ１５を樹脂やガラスのような材料から形成することにより、半導体素子５が小型になった場合にも、スペーサ１５の作製が容易に行える。   In particular, by forming the spacer 15 from a material such as resin or glass, the spacer 15 can be easily manufactured even when the semiconductor element 5 is downsized.

なお、本実施の形態２にかかる半導体装置では、スペーサ１３、１５は、ベース板１と絶縁基板３との間、および絶縁基板３と半導体素子５との間の、いずれか一方、または双方に形成することができる。   In the semiconductor device according to the second embodiment, the spacers 13 and 15 are provided between the base plate 1 and the insulating substrate 3 and between the insulating substrate 3 and the semiconductor element 5 or both. Can be formed.

本実施の形態１にかかる半導体装置の側面図である。1 is a side view of a semiconductor device according to a first embodiment. 本実施の形態１にかかる半導体装置に含まれる絶縁基板である。2 is an insulating substrate included in the semiconductor device according to the first embodiment; 本実施の形態１にかかる半導体装置に含まれる他の絶縁基板の裏面図である。FIG. 6 is a back view of another insulating substrate included in the semiconductor device according to the first embodiment. 本実施の形態１にかかるスペーサを用いた場合の気泡の動きである。This is the movement of bubbles when the spacer according to the first embodiment is used. 従来のスペーサを用いた場合の気泡の動きである。This is the movement of bubbles when a conventional spacer is used. 本実施の形態１にかかる半導体装置に含まれる他の絶縁基板である。3 is another insulating substrate included in the semiconductor device according to the first embodiment. 本実施の形態２にかかる半導体装置の一部である。2 is a part of a semiconductor device according to a second embodiment;

符号の説明Explanation of symbols

１ ベース板、２ 半田層、３ 絶縁基板、４ 半田層、５ 半導体チップ、１０ 気泡、１３、２３、４３ スペーサ、１００ 半導体装置。

DESCRIPTION OF SYMBOLS 1 Base board, 2 Solder layer, 3 Insulating substrate, 4 Solder layer, 5 Semiconductor chip, 10 Bubble, 13, 23, 43 Spacer, 100 Semiconductor device.

Claims (7)

絶縁基板の表面に半導体素子が半田層で固定され、該絶縁基板の裏面がベース板に半田層で固定された半導体装置であって、
該絶縁基板の該裏面の少なくとも四隅に、該絶縁基板と該ベース板との間に配置されてその間隔を略一定に保つスペーサを備え、
該スペーサが、該絶縁基板の該裏面と該スペーサとの接合領域を該裏面の法線方向に移動させてできる空間内に設けられたことを特徴とする半導体装置。 A semiconductor device in which a semiconductor element is fixed to a surface of an insulating substrate with a solder layer, and a back surface of the insulating substrate is fixed to a base plate with a solder layer,
Spacers arranged between the insulating substrate and the base plate at at least four corners of the back surface of the insulating substrate to keep the interval substantially constant,
A semiconductor device, wherein the spacer is provided in a space formed by moving a junction region between the back surface of the insulating substrate and the spacer in a normal direction of the back surface. 上記絶縁基板の裏面の周辺部に沿って上記スペーサが設けられたことを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the spacer is provided along a peripheral portion of a back surface of the insulating substrate. 絶縁基板の表面に半導体素子の底面が半田層で固定された半導体装置であって、
該半導体素子の該底面の少なくとも四隅に、該半導体素子と該絶縁基板との間に配置されてその間隔を略一定に保つスペーサを備え、
該スペーサが、該半導体素子の該底面と該スペーサとの接合領域を該底面の法線方向に移動させてできる空間内に設けられたことを特徴とする半導体装置。 A semiconductor device in which a bottom surface of a semiconductor element is fixed to a surface of an insulating substrate with a solder layer,
Spacers arranged at least at the four corners of the bottom surface of the semiconductor element and disposed between the semiconductor element and the insulating substrate to keep the interval substantially constant;
A semiconductor device, wherein the spacer is provided in a space formed by moving a junction region between the bottom surface of the semiconductor element and the spacer in a normal direction of the bottom surface. 上記半導体素子の底面の周辺部に沿って上記スペーサが設けられたことを特徴とする請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein the spacer is provided along a peripheral portion of a bottom surface of the semiconductor element. 上記半田層と接触する上記スペーサの面が、曲面であることを特徴とする請求項１〜４のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein a surface of the spacer in contact with the solder layer is a curved surface. 上記スペーサが、円柱形状または半球形状であることを特徴とする請求項１〜４のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the spacer has a cylindrical shape or a hemispherical shape. 上記スペーサが、樹脂またはガラスからなることを特徴とする請求項１〜４のいずれかに記載の半導体装置。

The semiconductor device according to claim 1, wherein the spacer is made of resin or glass.

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