JPH09162234A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Semiconductor integrated circuit device and its manufacturing method

Info

Publication number
JPH09162234A
JPH09162234A JP32336195A JP32336195A JPH09162234A JP H09162234 A JPH09162234 A JP H09162234A JP 32336195 A JP32336195 A JP 32336195A JP 32336195 A JP32336195 A JP 32336195A JP H09162234 A JPH09162234 A JP H09162234A
Authority
JP
Japan
Prior art keywords
mounting substrate
integrated circuit
semiconductor integrated
circuit device
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32336195A
Other languages
Japanese (ja)
Inventor
Nobuo Yoshida
伸生 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP32336195A priority Critical patent/JPH09162234A/en
Publication of JPH09162234A publication Critical patent/JPH09162234A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability upon bumps connecting a chip mounting substrate to a packaging substrate. SOLUTION: Within a semiconductor integrated circuit device composed of a sealing main body part 3 having a chip mounting substrate 2 while sealing a semiconductor chip 1 and a peripheral part 1a thereof, a printed substrate 5 packaging the sealing main body part 3 through the intermediary of bumps 4 to be ball electrodes as well as spacer members 6 supporting the sealing main body part 3 packaging the printed substrate 5 while maintaining a specific gap between the chip mounting substrate 2 and the printed substrate 5, the spacer members 6 are fitted to the angular parts 2b of the outer peripheries 2a of the chip mounting substrate 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体製造技術に
関し、特に、素子搭載基板と実装基板(プリント基板)
とをボール電極であるバンプによって接続する半導体集
積回路装置およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to an element mounting board and a mounting board (printed board).
The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the semiconductor integrated circuit device, wherein

【0002】[0002]

【従来の技術】以下に説明する技術は、本発明を研究、
完成するに際し、本発明者によって検討されたものであ
り、その概要は次のとおりである。
2. Description of the Related Art The technology described below studies the present invention,
The present invention was studied by the present inventors upon completion, and its outline is as follows.

【0003】多ピン化に対応する半導体集積回路装置の
一例として、BGA(Ball Grid Array)と称される半導
体集積回路装置が知られている。
A semiconductor integrated circuit device called BGA (Ball Grid Array) is known as an example of the semiconductor integrated circuit device which is compatible with the increase in the number of pins.

【0004】前記BGAは、はんだや金などによって形
成されたバンプを介して半導体素子を搭載した素子搭載
基板がプリント基板に実装されるものである。
In the BGA, an element mounting board on which a semiconductor element is mounted is mounted on a printed board through bumps formed of solder or gold.

【0005】この際、素子搭載基板とプリント基板との
距離は、はんだの表面張力、バンプの直径(または半
径)、各々の基板のランド径(バンプ搭載電極)および
半導体集積回路装置の封止本体部の重さによって決定さ
れる。
At this time, the distance between the device mounting board and the printed circuit board is determined by the surface tension of the solder, the diameter (or radius) of the bump, the land diameter of each board (bump mounting electrode) and the sealing body of the semiconductor integrated circuit device. Determined by the weight of the section.

【0006】なお、BGAについては、例えば、日経B
P社、1993年5月31日発行、香山晋、成瀬邦彦
(監)、「実践講座VLSIパッケージング技術
(下)」、174頁に記載されている。
Regarding BGA, for example, Nikkei B
Company P, published May 31, 1993, Shin Kayama, Kunihiko Naruse (supervisor), "Practical course VLSI packaging technology (below)", page 174.

【0007】[0007]

【発明が解決しようとする課題】ところが、前記した技
術においては、半導体集積回路装置の封止本体部の重さ
がその種類によって異なるため、1枚のプリント基板に
種々の半導体集積回路装置を実装する際に、プリント基
板ごとに一度にリフローすると、各々の半導体集積回路
装置のバンプの形状に差が生じる。
However, in the above-mentioned technique, since the weight of the sealing body of the semiconductor integrated circuit device differs depending on its type, various semiconductor integrated circuit devices are mounted on one printed circuit board. In this case, if the reflow process is performed once for each printed circuit board, a difference occurs in the bump shape of each semiconductor integrated circuit device.

【0008】これにより、バンプの接続信頼性にばらつ
きが発生し、接続不良を引き起こすことが問題とされ
る。
As a result, there arises a problem in that the connection reliability of the bumps varies and causes a connection failure.

【0009】本発明の目的は、素子搭載基板と実装基板
とを接続するバンプの接続信頼性を向上させる半導体集
積回路装置およびその製造方法を提供することにある。
An object of the present invention is to provide a semiconductor integrated circuit device and a method for manufacturing the semiconductor integrated circuit device, in which the connection reliability of bumps connecting the element mounting substrate and the mounting substrate is improved.

【0010】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0011】[0011]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。
SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【0012】すなわち、本発明の半導体集積回路装置
は、半導体素子を搭載する素子搭載基板を有しかつ前記
素子搭載基板に搭載された半導体素子およびその周辺部
を封止した封止本体部と、バンプを介して前記封止本体
部を実装する実装基板と、前記封止本体部を実装した際
に前記封止本体部を支持しかつ前記素子搭載基板と前記
実装基板との距離をほぼ一定に保つスペーサ部材とを有
するものである。
That is, the semiconductor integrated circuit device of the present invention has an element mounting substrate on which a semiconductor element is mounted, and a semiconductor body mounted on the element mounting substrate and a sealing main body portion sealing the peripheral portion thereof. A mounting board on which the sealing body is mounted via bumps, and which supports the sealing body when the sealing body is mounted and keeps the distance between the element mounting board and the mounting board substantially constant. And a spacer member for keeping the same.

【0013】これによって、バンプのはんだ付けを行う
際に封止本体部と実装基板との間にスペーサ部材を配置
させることにより、バンプ溶融後も素子搭載基板と実装
基板との距離をほぼ一定に保つことができる。
Thus, by disposing the spacer member between the sealing body and the mounting substrate when soldering the bumps, the distance between the element mounting substrate and the mounting substrate can be kept substantially constant even after the bumps are melted. Can be kept.

【0014】つまり、封止本体部がスペーサ部材によっ
て支持され、封止本体部の重さに関係なく素子搭載基板
と実装基板との距離を一定に保つことができる。
That is, the sealing body is supported by the spacer member, and the distance between the element mounting board and the mounting board can be kept constant regardless of the weight of the sealing body.

【0015】したがって、バンプが封止本体部の重さの
影響を直接受けないため、封止本体部の荷重によってバ
ンプが変形することを防止でき、はんだ付け時(溶融
時)のバンプの形状を安定させることができる。
Therefore, since the bumps are not directly influenced by the weight of the sealing body, the bumps can be prevented from being deformed by the load of the sealing body, and the shape of the bumps at the time of soldering (at the time of melting) can be prevented. Can be stabilized.

【0016】その結果、バンプの接続不良の発生を低減
させることができるため、バンプの接続信頼性を向上さ
せることができるとともに、バンプの接続寿命の長寿命
化を図ることができる。
As a result, the occurrence of defective connection of the bumps can be reduced, so that the connection reliability of the bumps can be improved and the connection life of the bumps can be extended.

【0017】さらに、本発明の半導体集積回路装置は、
前記スペーサ部材が前記素子搭載基板に取り付けられて
いる。
Furthermore, the semiconductor integrated circuit device of the present invention
The spacer member is attached to the element mounting substrate.

【0018】なお、本発明の半導体集積回路装置は、前
記バンプの半径をP、前記素子搭載基板におけるバンプ
搭載電極の半径をQ、前記実装基板におけるバンプ搭載
電極の半径をR、前記スペーサ部材の高さをHとする際
に、前記バンプ、前記スペーサ部材、前記素子搭載基板
および前記実装基板が(4/3)×π×P3 ≦(1/
3)×π×(Q2 +Q×R+R2 )×H,H≦2×Pの
条件によって形成されているものである。
In the semiconductor integrated circuit device of the present invention, the radius of the bump is P, the radius of the bump mounting electrode on the element mounting substrate is Q, the radius of the bump mounting electrode on the mounting substrate is R, and the spacer member is When the height is set to H, the bump, the spacer member, the element mounting substrate and the mounting substrate are (4/3) × π × P 3 ≦ (1 /
3) × π × (Q 2 + Q × R + R 2 ) × H, H ≦ 2 × P.

【0019】また、本発明の半導体集積回路装置の製造
方法は、半導体素子およびその周辺部を封止した封止本
体部が有する素子搭載基板にバンプを仮固定し、前記バ
ンプのはんだ付けを行う際に前記封止本体部と実装基板
との間に、前記素子搭載基板と前記実装基板との距離を
ほぼ一定に保ちかつ前記封止本体部を支持するスペーサ
部材を配置し、前記バンプを介して前記封止本体部と前
記実装基板とを接続するものである。
Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, the bumps are temporarily fixed to the element mounting substrate of the encapsulating main body encapsulating the semiconductor element and its peripheral portion, and the bumps are soldered. At this time, a spacer member for maintaining the distance between the element mounting substrate and the mounting substrate substantially constant and supporting the sealing main body is arranged between the sealing main body and the mounting substrate, and the spacer member is interposed therebetween. To connect the sealing body and the mounting substrate.

【0020】[0020]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。
Embodiments of the present invention will be described below in detail with reference to the drawings.

【0021】図1は本発明による半導体集積回路装置の
構造の実施の形態の一例を示す部分断面図、図2は本発
明による半導体集積回路装置の製造方法の実施の形態の
一例を示す部分断面図、図3は本発明による半導体集積
回路装置の製造方法の実施の形態の一例を示す部分断面
図である。
FIG. 1 is a partial sectional view showing an example of an embodiment of a structure of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a partial sectional view showing an example of an embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention. 3 and 4 are partial cross-sectional views showing an example of an embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention.

【0022】本実施の形態による半導体集積回路装置の
構成について説明すると、素子搭載基板2を有しかつ素
子搭載基板2に搭載された半導体素子である半導体チッ
プ1およびその周辺部1aを封止した封止本体部3と、
はんだなどによって形成されるボール電極であるバンプ
4を介して封止本体部3を実装する実装基板であるプリ
ント基板5と、封止本体部3をプリント基板5に実装し
た際に封止本体部3を支持しかつ素子搭載基板2とプリ
ント基板5との距離をほぼ一定に保つスペーサ部材6と
から構成されている。
The structure of the semiconductor integrated circuit device according to the present embodiment will be described. A semiconductor chip 1 which is a semiconductor element having an element mounting substrate 2 and mounted on the element mounting substrate 2 and its peripheral portion 1a are sealed. The sealing body 3,
A printed circuit board 5 which is a mounting board on which the sealing body 3 is mounted via bumps 4 which are ball electrodes formed of solder, and a sealing body when the sealing body 3 is mounted on the printed board 5. It is composed of a spacer member 6 which supports 3 and keeps the distance between the element mounting substrate 2 and the printed circuit board 5 substantially constant.

【0023】すなわち、本実施の形態の半導体集積回路
装置は、BGAと同様の構造を有するものであり、封止
本体部3の素子搭載基板2とプリント基板5とを複数個
のバンプ4によって電気的に接続して封止本体部3をプ
リント基板5に実装するものである。
That is, the semiconductor integrated circuit device of this embodiment has the same structure as the BGA, and the element mounting substrate 2 and the printed circuit board 5 of the sealing body 3 are electrically connected by the plurality of bumps 4. And the sealing main body 3 is mounted on the printed circuit board 5 by connecting them physically.

【0024】なお、半導体チップ1は素子搭載基板2に
金などから成る細いワイヤ7によってワイヤボンディン
グされ、これにより電気的に接続されている。
The semiconductor chip 1 is wire-bonded to the element mounting substrate 2 by a thin wire 7 made of gold or the like, and is electrically connected thereto.

【0025】さらに、封止本体部3は、素子搭載基板2
上で素子搭載基板2に搭載された半導体チップ1とその
周辺部1aを樹脂封止によって気密封止して形成したも
のであり、前記樹脂封止には、例えば、エポキシ系の熱
硬化性樹脂などを用いる。
Further, the sealing body 3 is the element mounting substrate 2
The semiconductor chip 1 mounted on the element mounting substrate 2 and its peripheral portion 1a are hermetically sealed by resin sealing, and the resin sealing is, for example, an epoxy thermosetting resin. And so on.

【0026】また、素子搭載基板2はセラミックなどに
よって形成され、プリント基板5はエポキシ系の樹脂な
どによって形成されている。
The device mounting board 2 is made of ceramic or the like, and the printed board 5 is made of epoxy resin or the like.

【0027】ここで、本実施の形態による半導体集積回
路装置においては、スペーサ部材6が素子搭載基板2の
外周部2aの角部2bに取り付けられている場合を説明
する。
Here, in the semiconductor integrated circuit device according to the present embodiment, the case where the spacer member 6 is attached to the corner portion 2b of the outer peripheral portion 2a of the element mounting substrate 2 will be described.

【0028】すなわち、素子搭載基板2の4つの角部2
bのそれぞれに、4個のスペーサ部材6が取り付けられ
ている。
That is, the four corners 2 of the device mounting board 2
Four spacer members 6 are attached to each of b.

【0029】なお、スペーサ部材6は、バンプ4の素材
であるはんだよりも融点が高い素材、例えば、銅などに
よって形成され、その形状は、所定箇所の距離(例え
ば、高さ)が高精度に形成された円柱などである。
The spacer member 6 is made of a material having a melting point higher than that of the solder, which is the material of the bump 4, such as copper, and its shape is such that the distance (eg, height) at a predetermined location is highly accurate. For example, a formed cylinder.

【0030】つまり、各々のスペーサ部材6は、バンプ
4を介して封止本体部3をプリント基板5に実装する際
に、封止本体部3の素子搭載基板2とプリント基板5と
の間に配置され、かつ封止本体部3を支持するとともに
素子搭載基板2とプリント基板5との距離を一定に保つ
ものである。
That is, each spacer member 6 is provided between the device mounting board 2 and the printed circuit board 5 of the sealing body 3 when the sealing body 3 is mounted on the printed circuit board 5 via the bumps 4. They are arranged and support the sealing body 3 and keep the distance between the element mounting substrate 2 and the printed circuit board 5 constant.

【0031】また、本実施の形態による半導体集積回路
装置においては、バンプ4の半径をP、素子搭載基板2
におけるバンプ搭載電極2cの半径をQ、プリント基板
5におけるバンプ搭載電極5aの半径をR、スペーサ部
材6の高さをHとすると、バンプ4、スペーサ部材6、
素子搭載基板2およびプリント基板5におけるバンプ搭
載電極2c,5aを(4/3)×π×P3 ≦(1/3)
×π×(Q2 +Q×R+R2 )×H,H≦2×Pを満た
す条件によって形成することにより、封止本体部3がプ
リント基板5に実装された際(はんだリフロー後)のバ
ンプ4の形状を、その中央部4aが括れた鼓状にするこ
とができる。
Further, in the semiconductor integrated circuit device according to the present embodiment, the radius of the bump 4 is P and the element mounting substrate 2 is
When the radius of the bump mounting electrode 2c in the above is Q, the radius of the bump mounting electrode 5a in the printed circuit board 5 is R, and the height of the spacer member 6 is H, the bump 4, the spacer member 6,
The bump mounting electrodes 2c and 5a on the element mounting substrate 2 and the printed circuit board 5 are (4/3) × π × P 3 ≦ (1/3)
By forming the sealing main body 3 on the printed circuit board 5 (after solder reflow), the bumps 4 are formed under the conditions of × π × (Q 2 + Q × R + R 2 ) × H, H ≦ 2 × P. Can be shaped like an hourglass with the central portion 4a constricted.

【0032】次に、本実施の形態の半導体集積回路装置
の製造方法について説明する。
Next, a method of manufacturing the semiconductor integrated circuit device of this embodiment will be described.

【0033】まず、半導体チップ1およびその周辺部1
aを熱硬化性樹脂などによって封止した封止本体部3を
準備する。
First, the semiconductor chip 1 and its peripheral portion 1
A sealing body 3 in which a is sealed with a thermosetting resin or the like is prepared.

【0034】さらに、封止本体部3が有する素子搭載基
板2の所定箇所のバンプ搭載電極2cにフラックスなど
を用いてバンプ4を仮固定する。
Further, the bumps 4 are temporarily fixed to the bump mounting electrodes 2c at predetermined locations on the element mounting substrate 2 of the sealing body 3 by using flux or the like.

【0035】ここで、リフローなどによってバンプ4の
はんだ付けを行う際に封止本体部3とプリント基板5と
の間に、素子搭載基板2とプリント基板5との距離をほ
ぼ一定に保ちかつ封止本体部3を支持するスペーサ部材
6を配置する。
Here, when soldering the bumps 4 by reflowing or the like, a distance between the element mounting substrate 2 and the printed circuit board 5 is kept substantially constant and sealed between the sealing body 3 and the printed circuit board 5. A spacer member 6 that supports the stopper body 3 is arranged.

【0036】なお、本実施の形態の半導体集積回路装置
においては、バンプ4を素子搭載基板2に仮固定した
後、封止本体部3の素子搭載基板2の外周部2aの4つ
の角部2bに4個のスペーサ部材6を取り付ける。
In the semiconductor integrated circuit device of the present embodiment, the bumps 4 are temporarily fixed to the element mounting substrate 2 and then the four corners 2b of the outer peripheral portion 2a of the element mounting substrate 2 of the sealing body 3 are provided. The four spacer members 6 are attached to.

【0037】この時、スペーサ部材6の固定には、例え
ば、接着剤を用いる。
At this time, for example, an adhesive is used to fix the spacer member 6.

【0038】その後、リフローなどによってバンプ4の
はんだ付けを行い、バンプ4を介して封止本体部3とプ
リント基板5とを電気的に接続する。
After that, the bumps 4 are soldered by reflowing or the like, and the sealing body 3 and the printed circuit board 5 are electrically connected via the bumps 4.

【0039】本実施の形態の半導体集積回路装置および
その製造方法によれば、以下のような作用効果が得られ
る。
According to the semiconductor integrated circuit device and the method of manufacturing the same of the present embodiment, the following operational effects can be obtained.

【0040】すなわち、バンプ4のはんだ付け(リフロ
ー)を行う際に、封止本体部3とプリント基板5との間
にスペーサ部材6を配置させることにより、バンプ4の
溶融後も素子搭載基板2とプリント基板5との距離をほ
ぼ一定の距離に保つことができる。
That is, when the bumps 4 are soldered (reflowed), the spacer member 6 is arranged between the sealing body 3 and the printed circuit board 5, so that the element mounting substrate 2 is melted even after the bumps 4 are melted. The distance between the printed circuit board 5 and the printed circuit board 5 can be maintained at a substantially constant distance.

【0041】つまり、封止本体部3がスペーサ部材6に
よって支持されることにより、封止本体部3の重さに関
係なく素子搭載基板2とプリント基板5との距離を一定
に保つことができる。
That is, since the sealing body 3 is supported by the spacer member 6, the distance between the element mounting substrate 2 and the printed board 5 can be kept constant regardless of the weight of the sealing body 3. .

【0042】したがって、バンプ4が封止本体部3の重
さの影響を直接受けないため、封止本体部3の荷重によ
ってバンプ4が変形することを防げ、はんだ付け時(溶
融時)のバンプ4の形状を安定させることができる。
Therefore, since the bumps 4 are not directly affected by the weight of the sealing body 3, the bumps 4 can be prevented from being deformed by the load of the sealing body 3, and the bumps at the time of soldering (when melting) can be prevented. The shape of 4 can be stabilized.

【0043】その結果、バンプ4の接続不良の発生を低
減させることができるため、バンプ4の接続信頼性を向
上させることができるとともに、バンプ4の接続寿命の
長寿命化を図ることができる。
As a result, the occurrence of defective connection of the bumps 4 can be reduced, so that the connection reliability of the bumps 4 can be improved and the connection life of the bumps 4 can be extended.

【0044】また、バンプ4の形状が安定することによ
り、バンプ4の形状を制御することが可能になる。
Further, since the shape of the bump 4 is stable, the shape of the bump 4 can be controlled.

【0045】なお、素子搭載基板2の大きさや材質の違
いなどによる種々の重さの複数個の封止本体部3を1枚
のプリント基板5に実装する際、プリント基板5ごと一
度にはんだ付け(リフロー)しても、バンプ4は封止本
体部3の荷重の影響は直接受けないため、各々の封止本
体部3に接続したバンプ4の形状変化を防止することが
できる。
When mounting a plurality of sealing main bodies 3 having various weights due to the size and material of the device mounting board 2 on one printed circuit board 5, the printed circuit boards 5 are soldered together at one time. Even if (reflow) is performed, the bumps 4 are not directly affected by the load of the sealing body 3, so that it is possible to prevent the bumps 4 connected to the respective sealing bodies 3 from changing in shape.

【0046】これにより、種々の重さの複数個の封止本
体部3を1枚のプリント基板5に実装する際に、プリン
ト基板5ごと一度にはんだ付けしても、各々のバンプ4
の接続信頼性がばらつくことがなく、さらに、各々のバ
ンプ4の変形を抑えることができるため、バンプ4の接
続不良の発生を低減させることができる。
As a result, when a plurality of sealing main body portions 3 having various weights are mounted on one printed circuit board 5, even if each printed circuit board 5 is soldered at once, each bump 4
Since the connection reliability does not vary and the deformation of each bump 4 can be suppressed, the occurrence of connection failure of the bump 4 can be reduced.

【0047】したがって、バンプ4の接続信頼性を向上
させることができるとともに、バンプ4の接続寿命の長
寿命化を図ることができる。
Therefore, the connection reliability of the bumps 4 can be improved and the connection life of the bumps 4 can be extended.

【0048】特に、大形の封止本体部3を小形の封止本
体部3と一緒に1枚のプリント基板5に搭載して一度に
リフローする際には、より大きな効果が得られる。
In particular, when the large-sized sealing body 3 and the small-sized sealing body 3 are mounted on one printed circuit board 5 and reflowed at once, a greater effect can be obtained.

【0049】なお、バンプ4の半径をP、素子搭載基板
2におけるバンプ搭載電極2cの半径をQ、プリント基
板5におけるバンプ搭載電極5aの半径をR、スペーサ
部材6の高さをHとし、バンプ4、スペーサ部材6、素
子搭載基板2およびプリント基板5を(4/3)×π×
3 ≦(1/3)×π×(Q2 +Q×R+R2 )×H,
H≦2×Pを満たす条件によって形成することにより、
バンプ4の溶融後の形状をその中央部4aが括れた鼓状
に制御することができる。
It should be noted that the radius of the bump 4 is P, the radius of the bump mounting electrode 2c on the element mounting substrate 2 is Q, the radius of the bump mounting electrode 5a on the printed circuit board 5 is R, and the height of the spacer member 6 is H. 4, the spacer member 6, the element mounting substrate 2 and the printed circuit board 5 are (4/3) × π ×
P 3 ≦ (1/3) × π × (Q 2 + Q × R + R 2 ) × H,
By forming under the condition that H ≦ 2 × P,
It is possible to control the shape of the bump 4 after melting into a drum shape in which the central portion 4a is constricted.

【0050】これにより、バンプ4の形状を素子搭載基
板2とプリント基板5との熱膨張差を吸収する形状にす
ることができるため、バンプ4の接続部に作用する応力
を低減することができる。
As a result, the shape of the bump 4 can be made to absorb the difference in thermal expansion between the element mounting substrate 2 and the printed circuit board 5, so that the stress acting on the connecting portion of the bump 4 can be reduced. .

【0051】その結果、バンプ4の接続不良の発生を低
減させることができ、さらに、バンプ4の接続信頼性を
向上させることができる。
As a result, the occurrence of defective connection of the bumps 4 can be reduced, and the connection reliability of the bumps 4 can be improved.

【0052】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記発明の実施の形態に限定されるものではなく、その
要旨を逸脱しない範囲で種々変更可能であることは言う
までもない。
Although the invention made by the present inventor has been specifically described based on the embodiment of the invention, the invention is not limited to the embodiment of the invention, and does not depart from the gist of the invention. It goes without saying that various changes can be made with.

【0053】例えば、前記実施の形態で説明した半導体
集積回路装置においては、スペーサ部材が封止本体部の
素子搭載基板に取り付けられた場合を説明したが、図4
もしくは図5に示す本発明の他の実施の形態の半導体集
積回路装置のように、スペーサ部材6が実装基板である
プリント基板5に取り付けられていてもよく(図4)、
また、素子搭載基板2とプリント基板5とによって挟持
されていてもよい(図5)。
For example, in the semiconductor integrated circuit device described in the above embodiment, the case where the spacer member is attached to the element mounting substrate of the sealing body has been described.
Alternatively, like the semiconductor integrated circuit device according to another embodiment of the present invention shown in FIG. 5, the spacer member 6 may be attached to the printed board 5 which is a mounting board (FIG. 4).
Further, it may be sandwiched between the element mounting board 2 and the printed board 5 (FIG. 5).

【0054】ここで、図4に示す半導体集積回路装置
は、スペーサ部材6がプリント基板5に取り付けられた
場合のものである。
Here, the semiconductor integrated circuit device shown in FIG. 4 is one in which the spacer member 6 is attached to the printed board 5.

【0055】この場合、少なくともバンプ4のはんだ付
け(リフロー)を行う前に、プリント基板5の所定箇所
にスペーサ部材6を接着剤などによって取り付けてお
く。
In this case, at least before soldering (reflowing) the bumps 4, the spacer member 6 is attached to a predetermined portion of the printed board 5 with an adhesive or the like.

【0056】また、図5に示す半導体集積回路装置は、
スペーサ部材6が封止本体部3の素子搭載基板2とプリ
ント基板5とによって挟持されている場合のものであ
る。
Further, the semiconductor integrated circuit device shown in FIG.
This is a case where the spacer member 6 is sandwiched between the element mounting substrate 2 of the sealing body 3 and the printed circuit board 5.

【0057】この場合、バンプ4のはんだ付けを行う際
に、封止本体部3の素子搭載基板2とプリント基板5と
の間にスペーサ部材6を挿入し、素子搭載基板2とプリ
ント基板5とによってスペーサ部材6を挟持してはんだ
付けを行う。
In this case, when soldering the bumps 4, the spacer member 6 is inserted between the device mounting board 2 and the printed circuit board 5 of the encapsulating main body 3 so that the device mounting circuit board 2 and the printed circuit board 5 are connected to each other. The spacer member 6 is sandwiched by and soldered.

【0058】したがって、スペーサ部材6を素子搭載基
板2やプリント基板5に固定することは行わず、素子搭
載基板2とプリント基板5との間にスペーサ部材6を挟
み込み、両者によって支持する。
Therefore, the spacer member 6 is not fixed to the device mounting board 2 or the printed circuit board 5, but the spacer member 6 is sandwiched between the device mounting circuit board 2 and the printed circuit board 5 and supported by both.

【0059】なお、図4および図5に示した他の実施の
形態の半導体集積回路装置においても、本発明の実施の
形態の半導体集積回路装置と同様の作用効果が得られ
る。
The semiconductor integrated circuit device of the other embodiments shown in FIGS. 4 and 5 can also provide the same effects as the semiconductor integrated circuit device of the embodiment of the present invention.

【0060】また、前記実施の形態あるいは他の実施の
形態の半導体集積回路装置においては、半導体チップ1
の封止が樹脂による樹脂封止の場合につい説明したが、
前記封止は、樹脂封止に限らず気密された封止であれ
ば、キャップなどを用いた封止であってもよい。
Further, in the semiconductor integrated circuit device of the above-mentioned embodiment or another embodiment, the semiconductor chip 1
I explained about the case where the sealing of is the resin sealing by the resin,
The sealing is not limited to resin sealing and may be sealing using a cap or the like as long as it is hermetically sealed.

【0061】さらに、半導体チップ1と素子搭載基板2
との接続は、ワイヤボンド接続に限らず小形バンプなど
による接続であってもよい。
Further, the semiconductor chip 1 and the element mounting substrate 2
The connection with and is not limited to wire bond connection, and may be connection by a small bump or the like.

【0062】また、スペーサ部材6の配置箇所は、素子
搭載基板2の外周部2a以外の箇所であってもよく、封
止本体部3を支持するとともに素子搭載基板2とプリン
ト基板5との距離を一定に保つことが可能な箇所であれ
ば、例えば、素子搭載基板2の内部、すなわち半導体チ
ップ1の下部などの箇所に配置されていてもよい。
Further, the spacer member 6 may be arranged at a position other than the outer peripheral portion 2a of the element mounting substrate 2, and it supports the sealing main body 3 and distances between the element mounting substrate 2 and the printed circuit board 5. As long as it is possible to keep it constant, for example, it may be arranged inside the element mounting substrate 2, that is, in the lower part of the semiconductor chip 1 or the like.

【0063】さらに、スペーサ部材6の設置数について
も特に限定はなく、封止本体部3を支持するとともに素
子搭載基板2とプリント基板5との距離を一定に保つこ
とが可能であれば、何個設置されていてもよい。
Further, the number of spacer members 6 to be installed is not particularly limited as long as it is possible to support the sealing body 3 and keep the distance between the element mounting board 2 and the printed board 5 constant. It may be installed individually.

【0064】なお、スペーサ部材6の形状については、
所定箇所の距離(例えば、高さ)が高精度に形成されて
いれば、円柱以外の角柱や円筒形、あるいは球(球の場
合の所定箇所は直径または半径)などであってもよい。
Regarding the shape of the spacer member 6,
As long as the distance (for example, height) of the predetermined place is formed with high accuracy, it may be a prism or a cylinder other than a cylinder, or a sphere (the predetermined place in the case of a sphere is a diameter or a radius).

【0065】また、スペーサ部材6の素材については、
バンプ4の素材であるはんだよりも融点が高い素材で、
かつ封止本体部3を支持できる程度の強度を有するもの
であれば、銅に限らず、他の素材であってもよい。
Regarding the material of the spacer member 6,
A material with a higher melting point than the solder that is the material of the bump 4,
In addition, the material is not limited to copper and may be another material as long as it has a strength enough to support the sealing body 3.

【0066】[0066]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。
Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

【0067】(1).バンプのはんだ付けを行う際に封
止本体部と実装基板との間にスペーサ部材を配置させる
ことにより、封止本体部の重さに関係なく素子搭載基板
と実装基板との距離を一定に保つことができる。これに
より、封止本体部の荷重によってバンプが変形すること
を防止できるため、はんだ付け時(溶融時)のバンプの
形状を安定させることができる。その結果、バンプの接
続不良の発生を低減させることができるため、バンプの
接続信頼性を向上させることができるとともに、バンプ
の接続寿命の長寿命化を図ることができる。
(1). By placing a spacer member between the sealing body and the mounting board when soldering bumps, the distance between the device mounting board and the mounting board is kept constant regardless of the weight of the sealing body. be able to. As a result, it is possible to prevent the bumps from being deformed by the load of the sealing main body portion, and thus it is possible to stabilize the shape of the bumps during soldering (when melting). As a result, the occurrence of defective connection of the bumps can be reduced, so that the connection reliability of the bumps can be improved and the connection life of the bumps can be extended.

【0068】(2).バンプの形状が安定することによ
り、バンプの形状を制御することが可能になる。これに
より、種々の重さの複数個の封止本体部を1枚の実装基
板に実装する際に、実装基板ごと一度にはんだ付けして
も、各々のバンプの接続信頼性がばらつくことがなく、
各々のバンプの変形を抑えることができるため、バンプ
の接続不良の発生を低減させることができる。したがっ
て、バンプの接続信頼性を向上させることができる。
(2). The stable shape of the bumps makes it possible to control the shape of the bumps. As a result, when mounting a plurality of sealing main bodies of various weights on one mounting board, even if the mounting boards are soldered at the same time, the connection reliability of each bump does not vary. ,
Since it is possible to suppress the deformation of each bump, it is possible to reduce the occurrence of defective connection of the bumps. Therefore, the connection reliability of the bump can be improved.

【0069】(3).バンプの半径をP、素子搭載基板
におけるバンプ搭載電極の半径をQ、実装基板における
バンプ搭載電極の半径をR、スペーサ部材の高さをHと
し、バンプ、スペーサ部材、素子搭載基板および実装基
板を(4/3)×π×P3 ≦(1/3)×π×(Q2
Q×R+R2 )×H,H≦2×Pの条件によって形成す
ることにより、バンプ溶融後のバンプの形状を鼓状に制
御することができる。これにより、バンプの接続部に作
用する応力を低減することができるため、バンプの接続
不良の発生を低減させることができる。
(3). Let P be the radius of the bump, Q be the radius of the bump mounting electrode on the device mounting board, R be the radius of the bump mounting electrode on the mounting substrate, and H be the height of the spacer member. (4/3) × π × P 3 ≦ (1/3) × π × (Q 2 +
By forming under the conditions of Q × R + R 2 ) × H and H ≦ 2 × P, the shape of the bump after the melting of the bump can be controlled in a drum shape. As a result, it is possible to reduce the stress acting on the connection portion of the bump, so that it is possible to reduce the occurrence of defective connection of the bump.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による半導体集積回路装置の構造の実施
の形態の一例を示す部分断面図である。
FIG. 1 is a partial sectional view showing an example of an embodiment of the structure of a semiconductor integrated circuit device according to the present invention.

【図2】本発明による半導体集積回路装置の製造方法の
実施の形態の一例を示す部分断面図である。
FIG. 2 is a partial cross-sectional view showing an example of an embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention.

【図3】本発明による半導体集積回路装置の製造方法の
実施の形態の一例を示す部分断面図である。
FIG. 3 is a partial cross-sectional view showing an example of an embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention.

【図4】本発明の他の実施の形態である半導体集積回路
装置の構造の一例を示す部分断面図である。
FIG. 4 is a partial cross-sectional view showing an example of the structure of a semiconductor integrated circuit device according to another embodiment of the present invention.

【図5】本発明の他の実施の形態である半導体集積回路
装置の構造の一例を示す部分断面図である。
FIG. 5 is a partial cross-sectional view showing an example of the structure of a semiconductor integrated circuit device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体チップ(半導体素子) 1a 周辺部 2 素子搭載基板 2a 外周部 2b 角部 2c バンプ搭載電極 3 封止本体部 4 バンプ 4a 中央部 5 プリント基板(実装基板) 5a バンプ搭載電極 6 スペーサ部材 7 ワイヤ P バンプの半径 Q 素子搭載基板におけるバンプ搭載電極の半径 R 実装基板におけるバンプ搭載電極の半径 H スペーサ部材の高さ 1 semiconductor chip (semiconductor element) 1a peripheral portion 2 element mounting substrate 2a outer peripheral portion 2b corner portion 2c bump mounting electrode 3 sealing main body portion 4 bump 4a central portion 5 printed circuit board (mounting substrate) 5a bump mounting electrode 6 spacer member 7 wire P Radius of bump Q Radius of bump mounting electrode on element mounting board R Radius of bump mounting electrode on mounting board H Height of spacer member

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を搭載する素子搭載基板がバ
ンプを介して実装された半導体集積回路装置であって、 前記素子搭載基板を有し、かつ前記素子搭載基板に搭載
された半導体素子およびその周辺部を封止した封止本体
部と、 前記バンプを介して前記封止本体部を実装する実装基板
と、 前記封止本体部を実装した際に前記封止本体部を支持
し、かつ前記素子搭載基板と前記実装基板との距離をほ
ぼ一定に保つスペーサ部材とを有することを特徴とする
半導体集積回路装置。
1. A semiconductor integrated circuit device in which an element mounting substrate on which a semiconductor element is mounted is mounted via bumps, the semiconductor element having the element mounting substrate, and the semiconductor element mounted on the element mounting substrate, and the same. A sealing main body that seals the peripheral portion, a mounting substrate that mounts the sealing main body via the bumps, supports the sealing main body when mounting the sealing main body, and A semiconductor integrated circuit device comprising: a device mounting board and a spacer member for keeping a distance between the mounting board and the mounting board substantially constant.
【請求項2】 請求項1記載の半導体集積回路装置であ
って、前記スペーサ部材が前記素子搭載基板に取り付け
られていることを特徴とする半導体集積回路装置。
2. The semiconductor integrated circuit device according to claim 1, wherein the spacer member is attached to the element mounting substrate.
【請求項3】 請求項1記載の半導体集積回路装置であ
って、前記スペーサ部材が前記実装基板に取り付けられ
ていることを特徴とする半導体集積回路装置。
3. The semiconductor integrated circuit device according to claim 1, wherein the spacer member is attached to the mounting substrate.
【請求項4】 請求項1記載の半導体集積回路装置であ
って、前記スペーサ部材が前記封止本体部の素子搭載基
板と前記実装基板とによって挟持されていることを特徴
とする半導体集積回路装置。
4. The semiconductor integrated circuit device according to claim 1, wherein the spacer member is sandwiched between the element mounting substrate of the sealing body and the mounting substrate. .
【請求項5】 請求項1,2,3または4記載の半導体
集積回路装置であって、前記バンプの半径をP、前記素
子搭載基板におけるバンプ搭載電極の半径をQ、前記実
装基板におけるバンプ搭載電極の半径をR、前記スペー
サ部材の高さをHとする際に、前記バンプ、前記スペー
サ部材、前記素子搭載基板および前記実装基板が(4/
3)×π×P3 ≦(1/3)×π×(Q2 +Q×R+R
2 )×H,H≦2×Pの条件によって形成されているこ
とを特徴とする半導体集積回路装置。
5. The semiconductor integrated circuit device according to claim 1, 2, 3 or 4, wherein a radius of the bump is P, a radius of a bump mounting electrode on the element mounting substrate is Q, and a bump mounting on the mounting substrate is mounted. When the radius of the electrode is R and the height of the spacer member is H, the bump, the spacer member, the element mounting substrate and the mounting substrate are (4 /
3) × π × P 3 ≦ (1/3) × π × (Q 2 + Q × R + R
2 ) A semiconductor integrated circuit device characterized in that it is formed under the conditions of H × 2 , H ≦ 2 × P.
【請求項6】 半導体素子を搭載する素子搭載基板を有
した半導体集積回路装置の製造方法であって、 前記半導体素子およびその周辺部を封止した封止本体部
が有する素子搭載基板にバンプを仮固定し、 前記バンプのはんだ付けを行う際に前記封止本体部と実
装基板との間に、前記素子搭載基板と前記実装基板との
距離をほぼ一定に保ちかつ前記封止本体部を支持するス
ペーサ部材を配置し、 前記バンプを介して前記封止本体部と前記実装基板とを
接続することを特徴とする半導体集積回路装置の製造方
法。
6. A method of manufacturing a semiconductor integrated circuit device having an element mounting substrate on which a semiconductor element is mounted, wherein bumps are provided on an element mounting substrate included in a sealing main body that seals the semiconductor element and its peripheral portion. Temporarily fixed, and when the soldering of the bumps is performed, the distance between the element mounting board and the mounting board is kept substantially constant between the sealing body and the mounting board, and the sealing body is supported. A spacer member is disposed, and the sealing main body portion and the mounting substrate are connected via the bump, and a method for manufacturing a semiconductor integrated circuit device.
【請求項7】 請求項6記載の半導体集積回路装置の製
造方法であって、前記バンプを前記素子搭載基板に仮固
定した後、前記封止本体部の素子搭載基板に前記スペー
サ部材を取り付けることを特徴とする半導体集積回路装
置の製造方法。
7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the bump is temporarily fixed to the element mounting substrate, and then the spacer member is attached to the element mounting substrate of the sealing body. A method for manufacturing a semiconductor integrated circuit device, comprising:
【請求項8】 請求項6記載の半導体集積回路装置の製
造方法であって、前記バンプのはんだ付けを行う前に、
前記実装基板に前記スペーサ部材を取り付けることを特
徴とする半導体集積回路装置の製造方法。
8. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein before soldering the bumps,
A method of manufacturing a semiconductor integrated circuit device, comprising: mounting the spacer member on the mounting substrate.
【請求項9】 請求項6記載の半導体集積回路装置の製
造方法であって、前記バンプのはんだ付けを行う際に前
記封止本体部の素子搭載基板と前記実装基板との間に前
記スペーサ部材を挿入し、前記素子搭載基板と前記実装
基板とによって前記スペーサ部材を挟持してはんだ付け
することを特徴とする半導体集積回路装置の製造方法。
9. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the spacer member is provided between the element mounting substrate and the mounting substrate of the sealing main body when soldering the bumps. Is inserted, and the spacer member is sandwiched between the element mounting substrate and the mounting substrate and soldered, and a method for manufacturing a semiconductor integrated circuit device.
JP32336195A 1995-12-12 1995-12-12 Semiconductor integrated circuit device and its manufacturing method Pending JPH09162234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32336195A JPH09162234A (en) 1995-12-12 1995-12-12 Semiconductor integrated circuit device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32336195A JPH09162234A (en) 1995-12-12 1995-12-12 Semiconductor integrated circuit device and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH09162234A true JPH09162234A (en) 1997-06-20

Family

ID=18153925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32336195A Pending JPH09162234A (en) 1995-12-12 1995-12-12 Semiconductor integrated circuit device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPH09162234A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245435A (en) * 2005-03-04 2006-09-14 Ricoh Co Ltd Assembly component, mother board therefor, module substrate therefor, module substrate manufacturing method therefor, electronic circuit device and electronic equipment
JP2006278598A (en) * 2005-03-29 2006-10-12 Mitsubishi Electric Corp Semiconductor device
JP2012033696A (en) * 2010-07-30 2012-02-16 Fujitsu Ltd Circuit substrate unit, method for manufacturing the same, and electronic device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245435A (en) * 2005-03-04 2006-09-14 Ricoh Co Ltd Assembly component, mother board therefor, module substrate therefor, module substrate manufacturing method therefor, electronic circuit device and electronic equipment
JP4545615B2 (en) * 2005-03-04 2010-09-15 株式会社リコー Assembly parts, module substrate, module substrate manufacturing method, electronic circuit device, and electronic apparatus
JP2006278598A (en) * 2005-03-29 2006-10-12 Mitsubishi Electric Corp Semiconductor device
JP4704084B2 (en) * 2005-03-29 2011-06-15 三菱電機株式会社 Semiconductor device
JP2012033696A (en) * 2010-07-30 2012-02-16 Fujitsu Ltd Circuit substrate unit, method for manufacturing the same, and electronic device

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