JPH1140608A - Semiconductor device and its mounting method - Google Patents
Semiconductor device and its mounting methodInfo
- Publication number
- JPH1140608A JPH1140608A JP19699497A JP19699497A JPH1140608A JP H1140608 A JPH1140608 A JP H1140608A JP 19699497 A JP19699497 A JP 19699497A JP 19699497 A JP19699497 A JP 19699497A JP H1140608 A JPH1140608 A JP H1140608A
- Authority
- JP
- Japan
- Prior art keywords
- mounting board
- support member
- main body
- semiconductor device
- solder bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体製造技術に
関し、特に、素子搭載基板と実装基板(プリント基板)
とをボール電極であるはんだバンプによって接続する半
導体装置およびその実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly, to an element mounting board and a mounting board (printed board).
And a method of mounting the semiconductor device, wherein the semiconductor device is connected to the semiconductor device by solder bumps as ball electrodes.
【0002】[0002]
【従来の技術】以下に説明する技術は、本発明を研究、
完成するに際し、本発明者によって検討されたものであ
り、その概要は次のとおりである。2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.
【0003】高機能・低価格な中央演算装置(MPU)
を必要とするパーソナルコンピュータ(以降、パソコン
と略す)は様々な分野で利用されているが、ユーザから
の多機能化や高性能化の要求が強くなってきている。High-performance, low-cost central processing unit (MPU)
Although personal computers (hereinafter, abbreviated to personal computers) that require a computer are used in various fields, demands for multifunctional and high performance from users are increasing.
【0004】なお、パソコンの機能(特に高速化)は、
中央演算装置によってそのほとんどが決定される。[0004] The functions of the personal computer (especially speeding up) are as follows.
Most are determined by the central processing unit.
【0005】そこで、高速化に対応した半導体装置の一
例として、BGA(Ball Grid Array)と称される半導体
装置が知られている。Therefore, a semiconductor device called a BGA (Ball Grid Array) is known as an example of a semiconductor device corresponding to high speed operation.
【0006】前記BGAは、半導体素子が搭載された素
子搭載基板を備える装置本体部がはんだバンプを介して
プリント基板(実装基板)に実装されるものであるが、
中央演算装置の高速化に伴い、半導体素子からの発熱量
も増えるため、その対策として、半導体素子に熱拡散板
などの放熱部材を取り付けて放熱性を向上させるものが
ある。In the BGA, a device body including an element mounting board on which a semiconductor element is mounted is mounted on a printed board (mounting board) via solder bumps.
As the speed of the central processing unit increases, the amount of heat generated from the semiconductor element also increases. As a countermeasure, there is a method in which a heat radiating member such as a heat diffusion plate is attached to the semiconductor element to improve heat radiation.
【0007】ここで、BGAについては、例えば、日経
BP社、1993年5月31日発行、香山晋、成瀬邦彦
(監)、「実践講座VLSIパッケージング技術
(下)」、174頁に記載されている。The BGA is described in, for example, Nikkei BP, published on May 31, 1993, Susumu Kayama and Kunihiko Naruse (monitoring), “Practical Course VLSI Packaging Technology (Lower)”, page 174. ing.
【0008】[0008]
【発明が解決しようとする課題】ところが、前記した技
術のBGAにおいては、その装置本体部をプリント基板
に実装した際に、その構造上、前記装置本体部の重量が
そのままはんだバンプにかかる。However, in the BGA of the above-described technology, when the device main body is mounted on a printed circuit board, the weight of the device main body is directly applied to the solder bumps due to its structure.
【0009】このため、半導体素子に大きな放熱部材を
取り付けることは、バンプ潰れを引き起こすことに繋が
る。したがって、大きな放熱部材を設置するのは困難で
あることが問題とされる。For this reason, attaching a large heat radiating member to a semiconductor element leads to bump collapse. Therefore, it is a problem that it is difficult to install a large heat radiation member.
【0010】また、はんだバンプの潰れは発生しなくて
も、放熱部材を半導体素子に取り付けた場合、その装置
本体部の重量によってはんだバンプの接続高さが低くな
る場合があり、これにより、はんだバンプの接続寿命が
短くなることが問題とされる。In addition, even if the solder bumps are not crushed, when the heat radiating member is attached to the semiconductor element, the connection height of the solder bumps may be reduced due to the weight of the device main body. The problem is that the connection life of the bump is shortened.
【0011】本発明の目的は、はんだバンプ溶融時のバ
ンプ高さを制御してはんだバンプの接続寿命を延ばすと
ともに、はんだバンプの接続信頼性を向上させる半導体
装置およびその実装方法を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of mounting the same, which control the height of the bump when the solder bump is melted to extend the connection life of the solder bump and improve the connection reliability of the solder bump. is there.
【0012】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【0013】[0013]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【0014】すなわち、本発明の半導体装置は、半導体
素子が搭載された素子搭載基板を備える装置本体部と、
前記装置本体部を前記はんだバンプを介して実装する実
装基板と、前記はんだバンプを形成するはんだより熱膨
張係数の大きな材料によって形成され、かつ前記装置本
体部実装後の前記はんだバンプの高さより低く形成され
た支持部材とを有し、前記装置本体部を前記はんだバン
プを介して前記実装基板に実装する際の前記はんだバン
プの溶融時に、前記支持部材が前記素子搭載基板と前記
実装基板とに接触して前記装置本体部を支持するもので
ある。That is, the semiconductor device of the present invention comprises a device body having an element mounting board on which a semiconductor element is mounted;
A mounting board for mounting the device main body via the solder bumps, formed of a material having a larger coefficient of thermal expansion than the solder forming the solder bumps, and lower than the height of the solder bumps after mounting the device main body; Having a support member formed, when the solder bump is melted when mounting the device main body portion on the mounting board via the solder bump, the support member is attached to the element mounting board and the mounting board. The device supports the device main body in contact with the device.
【0015】これにより、装置本体部の重量が増えても
はんだバンプ溶融時のはんだバンプの高さを支持部材に
よって制御して装置本体部を実装基板に実装できる。Thus, even if the weight of the device main body increases, the height of the solder bump when the solder bump is melted can be controlled by the support member to mount the device main body on the mounting board.
【0016】したがって、はんだバンプ溶融時のバンプ
潰れを防止でき、その結果、はんだバンプ同士のショー
トを防ぐことができるとともに、はんだバンプの接続信
頼性を向上できる。Therefore, it is possible to prevent the bumps from being crushed when the solder bumps are melted. As a result, it is possible to prevent short-circuiting between the solder bumps and improve the connection reliability of the solder bumps.
【0017】また、本発明の半導体装置の実装方法は、
半導体装置の装置本体部を実装した後のはんだバンプの
高さより低く形成され、かつ前記はんだバンプのはんだ
より熱膨張係数の大きな材料によって形成された支持部
材を有する素子搭載基板または実装基板を準備する工程
と、前記素子搭載基板に半導体素子を搭載して前記装置
本体部を形成する工程と、前記支持部材と前記実装基板
または前記素子搭載基板との間に間隙を形成して、前記
半導体素子が搭載された前記素子搭載基板を備える前記
装置本体部を前記実装基板上に前記はんだバンプを介し
て配置する工程と、前記はんだバンプを溶融し、前記支
持部材によって前記装置本体部を支持しながら前記はん
だバンプによって前記素子搭載基板と前記実装基板とを
電気的に接続する工程と、前記はんだバンプを硬化させ
るとともに前記支持部材を収縮させて、前記支持部材と
前記実装基板または前記素子搭載基板との間に間隙を形
成した状態で、前記装置本体部を前記実装基板上に前記
はんだバンプを介して実装する工程とを有するものであ
る。Further, a method of mounting a semiconductor device according to the present invention comprises:
An element mounting board or a mounting board having a supporting member formed to be lower than the height of the solder bump after mounting the device body of the semiconductor device and having a larger thermal expansion coefficient than the solder of the solder bump is prepared. Forming a device body by mounting a semiconductor element on the element mounting board, forming a gap between the support member and the mounting board or the element mounting board, the semiconductor element is Arranging the device main body including the mounted element mounting board on the mounting board via the solder bumps, melting the solder bumps, and supporting the device main body by the support member; Electrically connecting the element mounting board and the mounting board by solder bumps; Shrinking the member and mounting the device body on the mounting board via the solder bumps in a state where a gap is formed between the support member and the mounting board or the element mounting board. Have
【0018】[0018]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【0019】図1は本発明による半導体装置の構造の実
施の形態の一例を示す断面図、図2は本発明の半導体装
置の素子搭載基板における支持部材の設置状態の実施の
形態の一例を示す底面図、図3(a),(b),(c)は本
発明の半導体装置の実装方法の実施の形態の一例を示す
拡大部分断面図である。FIG. 1 is a sectional view showing an embodiment of a structure of a semiconductor device according to the present invention, and FIG. 2 is an example of an embodiment of a mounting state of a support member on an element mounting board of the semiconductor device of the present invention. FIGS. 3A, 3B, and 3C are enlarged partial cross-sectional views illustrating an example of an embodiment of a method for mounting a semiconductor device according to the present invention.
【0020】本実施の形態による半導体装置は、BGA
と同様の構造を有する装置本体部3がはんだバンプ4を
介してプリント基板5に実装されたものであり、装置本
体部3の素子搭載基板2とプリント基板5とを格子状に
配置された複数個のはんだバンプ4によって電気的に接
続して装置本体部3をプリント基板5に実装するもので
ある。The semiconductor device according to the present embodiment has a BGA
A device main body 3 having the same structure as that of the above is mounted on a printed circuit board 5 via solder bumps 4, and the device mounting board 2 and the printed circuit board 5 of the device main body 3 are arranged in a grid pattern. The device body 3 is mounted on the printed circuit board 5 by being electrically connected by the solder bumps 4.
【0021】図1に示す前記半導体装置の構成について
説明すると、半導体素子である半導体チップ1(LSI
(Large Scale Integration))が搭載された素子搭載基
板2を備える装置本体部3と、装置本体部3をはんだバ
ンプ4を介して実装するプリント基板5(実装基板)
と、はんだバンプ4を形成するはんだより熱膨張係数の
大きな材料によって形成され、かつ装置本体部3実装後
のはんだバンプ4の高さより低く形成された支持部材6
とからなり、装置本体部3をはんだバンプ4を介してプ
リント基板5に実装する際のはんだバンプ4の溶融時
に、支持部材6が素子搭載基板2とプリント基板5とに
接触して装置本体部3を支持するものである。The structure of the semiconductor device shown in FIG. 1 will be described.
(Large Scale Integration)) and a printed circuit board 5 on which the device body 3 is mounted via solder bumps 4 (mounting board).
And a support member 6 formed of a material having a larger coefficient of thermal expansion than the solder forming the solder bumps 4, and formed to be lower than the height of the solder bumps 4 after mounting the device body 3.
When the device body 3 is mounted on the printed circuit board 5 via the solder bumps 4 and the solder bumps 4 are melted, the support member 6 comes into contact with the element mounting board 2 and the printed circuit board 5 and 3 is supported.
【0022】ここで、半導体チップ1は、素子搭載基板
2にはんだなどから成るCCB(Controlled Collapse
bonding )バンプ7によってCCBバンプ接続され、こ
れによって、素子搭載基板2に表面実装されるととも
に、素子搭載基板2に電気的に接続されている。Here, the semiconductor chip 1 is mounted on the element mounting board 2 by CCB (Controlled Collapse) made of solder or the like.
Bonding) CCB bumps are connected by the bumps 7, thereby being surface-mounted on the element mounting board 2 and electrically connected to the element mounting board 2.
【0023】さらに、装置本体部3は、素子搭載基板2
上で素子搭載基板2に搭載された半導体チップ1を封止
樹脂8(アンダーフィル用樹脂)によって封止するとと
もに、封止樹脂8によってCCBバンプ7の補強を行
い、かつ半導体チップ1の表面1bに放熱部材9を取り
付けて形成したものであり、前記封止樹脂8には、例え
ば、エポキシ系の熱硬化性樹脂などを用いる。Further, the device main body 3 includes the element mounting board 2.
The semiconductor chip 1 mounted on the element mounting substrate 2 is sealed with a sealing resin 8 (resin for underfill), the CCB bump 7 is reinforced by the sealing resin 8, and the surface 1b of the semiconductor chip 1 is sealed. The sealing resin 8 is formed of, for example, an epoxy-based thermosetting resin.
【0024】また、素子搭載基板2は、BGAベースと
も呼ばれ、例えば、ガラスエポキシ樹脂などによって形
成され、かつ平面形状は四角形を成すものであり、格子
状に配置された複数のはんだバンプ4によってプリント
基板5に実装される。The element mounting board 2 is also called a BGA base, and is formed of, for example, glass epoxy resin and has a square planar shape, and is formed by a plurality of solder bumps 4 arranged in a grid. The printed circuit board 5 is mounted.
【0025】さらに、プリント基板5は、種々の半導体
装置や電子部品などを搭載する実装基板であり、例え
ば、エポキシ系の樹脂などによって形成されている。The printed board 5 is a mounting board on which various semiconductor devices and electronic components are mounted, and is formed of, for example, an epoxy resin.
【0026】また、支持部材6は、はんだバンプ4溶融
時のこのはんだバンプ4のバンプ潰れを防止するもので
あり、はんだバンプ4を形成するはんだより熱膨張係数
の大きな材料、例えば、素子搭載基板2と同様のガラス
エポキシ樹脂によって形成され、かつ、装置本体部3を
プリント基板5に実装した後のはんだバンプ4の高さよ
り低くなるように形成されたものである。The supporting member 6 is for preventing the bumps of the solder bumps 4 from being crushed when the solder bumps 4 are melted, and is made of a material having a larger coefficient of thermal expansion than the solder forming the solder bumps 4, for example, an element mounting board. 2 and is formed so as to be lower than the height of the solder bumps 4 after the device main body 3 is mounted on the printed circuit board 5.
【0027】前記ガラスエポキシ樹脂の熱膨張係数は、
一例として、30×10-6/℃であり、はんだバンプ4
に用いるはんだの熱膨張係数は、一例として、24×1
0-6/℃である。The coefficient of thermal expansion of the glass epoxy resin is as follows:
As an example, 30 × 10 −6 / ° C.
The coefficient of thermal expansion of the solder used for is, for example, 24 × 1
0 -6 / ° C.
【0028】また、前記はんだの融点は、例えば、前記
はんだの組成がPb−63wt%Snの場合、約183
℃である。The melting point of the solder is, for example, about 183 when the composition of the solder is Pb-63 wt% Sn.
° C.
【0029】ここで、本実施の形態の半導体装置におい
ては、支持部材6が装置本体部3の素子搭載基板2に設
けられ、かつ装置本体部3のプリント基板5への実装後
に支持部材6とプリント基板5との間に間隙a(図3
(c)参照)が形成される場合を説明する。Here, in the semiconductor device of the present embodiment, the support member 6 is provided on the element mounting board 2 of the apparatus main body 3, and after the apparatus main body 3 is mounted on the printed board 5, the support member 6 A gap a (FIG. 3)
(C) will be described.
【0030】つまり、図3(c)に示すように、装置本
体部3実装後のはんだバンプ4の高さをHとし、支持部
材6の高さをhとし、支持部材6とプリント基板5との
間隙をaとすると、H≒h+aで表される。That is, as shown in FIG. 3C, the height of the solder bumps 4 after mounting the device body 3 is H, the height of the support member 6 is h, and the support member 6 and the printed circuit board 5 are connected to each other. If a gap is represented by a, then H 表 h + a.
【0031】なお、支持部材6は、縦断面が四角形の枠
状(図2参照)に形成され、図1に示すように、かつ、
この枠状の支持部材6の外周部6aが素子搭載基板2の
外周部2aと同じ大きさに形成されている。The support member 6 is formed in a rectangular frame shape (see FIG. 2) with a vertical section, and as shown in FIG.
The outer peripheral portion 6 a of the frame-shaped support member 6 is formed to have the same size as the outer peripheral portion 2 a of the element mounting substrate 2.
【0032】さらに、本実施の形態においては、素子搭
載基板2を製造する際に、支持部材6が素子搭載基板2
と一体に形成されている場合を説明する。Further, in the present embodiment, when manufacturing the element mounting board 2, the support member 6
The case where it is integrally formed will be described.
【0033】つまり、支持部材6の外形形状を素子搭載
基板2の外周部2aにほぼ沿った枠状に形成し、この枠
状の支持部材6を、予め、素子搭載基板2の製造工程に
おいて、素子搭載基板2と一体に形成する。That is, the outer shape of the support member 6 is formed in a frame shape substantially along the outer peripheral portion 2a of the element mounting substrate 2, and the frame-shaped support member 6 is previously formed in the manufacturing process of the element mounting substrate 2. It is formed integrally with the element mounting board 2.
【0034】また、本実施の形態の半導体装置は、その
装置本体部3において半導体チップ1の電極形成面1a
と反対側の背面(本実施の形態では表面1bのことであ
り、以降、表面1bと呼ぶ)にアルミニウムなどによっ
て形成された放熱部材9が取り付けられている。In the semiconductor device of the present embodiment, the electrode forming surface 1a of the semiconductor chip 1 in the device body 3 is provided.
A heat dissipating member 9 made of aluminum or the like is attached to the back surface opposite to (the surface 1b in the present embodiment, hereinafter referred to as the surface 1b).
【0035】なお、本実施の形態の半導体装置に取り付
けられた放熱部材9は、その平面的な大きさが素子搭載
基板2と同じ程度のものである。The heat dissipating member 9 attached to the semiconductor device of the present embodiment has the same planar size as the element mounting board 2.
【0036】また、前記半導体装置において、半導体チ
ップ1からの信号は、素子搭載基板2内で拡大、伝搬さ
れ、その後、プリント基板5に伝えられる。In the semiconductor device, a signal from the semiconductor chip 1 is expanded and propagated in the element mounting board 2 and then transmitted to the printed board 5.
【0037】次に、本実施の形態の半導体装置の実装方
法について説明する。Next, a method of mounting the semiconductor device according to the present embodiment will be described.
【0038】なお、本実施の形態では、枠状の支持部材
6が素子搭載基板2に一体で設けられ、かつ装置本体部
3のプリント基板5への実装後に支持部材6とプリント
基板5との間に間隙aが形成される場合を説明する。In the present embodiment, the frame-shaped support member 6 is provided integrally with the element mounting board 2, and after the apparatus main body 3 is mounted on the printed board 5, the support member 6 and the printed board 5 A case where a gap a is formed between the two will be described.
【0039】まず、図3に示すように、半導体装置の装
置本体部3を実装した後のはんだバンプ4の高さHより
低く形成され、かつはんだバンプ4のはんだより熱膨張
係数の大きな材料(本実施の形態ではガラスエポキシ樹
脂)によって形成された高さhの支持部材6を有する素
子搭載基板2を準備する(H>h)。First, as shown in FIG. 3, a material which is formed to be lower than the height H of the solder bump 4 after mounting the device body 3 of the semiconductor device and has a larger coefficient of thermal expansion than the solder of the solder bump 4 ( In the present embodiment, an element mounting substrate 2 having a supporting member 6 having a height h formed of glass epoxy resin) is prepared (H> h).
【0040】ここで、本実施の形態では、枠状の支持部
材6が素子搭載基板2に一体で設けられている場合であ
るため、素子搭載基板2を製造する際に、多層基板の形
成方法を利用して枠状の支持部材6(図2参照)も素子
搭載基板2に一体で形成する。Here, in this embodiment, since the frame-shaped support member 6 is provided integrally with the element mounting substrate 2, when manufacturing the element mounting substrate 2, a method of forming a multilayer substrate is used. The frame-shaped support member 6 (see FIG. 2) is also formed integrally with the element mounting substrate 2 by utilizing the above.
【0041】なお、枠状の支持部材6を素子搭載基板2
と一体でなく、別ピースとして形成し、素子搭載基板2
に後から接合する際には、素子搭載基板2の外周部2a
と枠状の支持部材6の外周部6aとの位置を合わせ、か
つ接着剤によって素子搭載基板2に枠状の支持部材6を
取り付ける。It should be noted that the frame-shaped supporting member 6 is
And not as an integral part, but as a separate piece
When bonding is performed later, the outer peripheral portion 2a of the element mounting substrate 2 is used.
The frame-shaped support member 6 is attached to the element mounting board 2 with an adhesive by aligning the position with the outer peripheral portion 6a of the frame-shaped support member 6.
【0042】これにより、高さhの支持部材6を設けた
素子搭載基板2を準備できる。Thus, the element mounting board 2 provided with the supporting member 6 having the height h can be prepared.
【0043】その後、図1に示すように、素子搭載基板
2に半導体チップ1を搭載し、かつ放熱部材9を半導体
チップ1に取り付けて装置本体部3を形成する。Thereafter, as shown in FIG. 1, the semiconductor chip 1 is mounted on the element mounting board 2 and the heat radiating member 9 is attached to the semiconductor chip 1 to form the device main body 3.
【0044】チップマウントの際には、CCBバンプ7
を用いて半導体チップ1を素子搭載基板2にCCBバン
プ接続する。When mounting the chip, the CCB bump 7
The semiconductor chip 1 is connected to the element mounting board 2 by CCB bumping.
【0045】これにより、チップマウントが行われ、半
導体チップ1と素子搭載基板2とが電気的に接続され
る。Thus, chip mounting is performed, and the semiconductor chip 1 and the element mounting board 2 are electrically connected.
【0046】続いて、封止樹脂8をCCBバンプ7の接
合部および半導体チップ1の周囲に塗布(供給)して半
導体チップ1とCCBバンプ7の接合部とを封止樹脂8
によって保護する。Subsequently, a sealing resin 8 is applied (supplied) to the joint between the CCB bumps 7 and the periphery of the semiconductor chip 1 so that the joint between the semiconductor chip 1 and the CCB bumps 7 is sealed.
Protect by.
【0047】その後、エポキシ系の接着剤などを用いて
半導体チップ1の背面すなわち表面1bに放熱部材9を
取り付ける。Thereafter, the heat radiating member 9 is attached to the back surface, that is, the front surface 1b of the semiconductor chip 1 by using an epoxy adhesive or the like.
【0048】さらに、プリント基板5上の所定箇所上に
はんだバンプ4を供給し、続いて、図3(a)に示すよ
うに、支持部材6とプリント基板5との間に所定の空隙
(間隙aより若干大きい程度の空隙)を形成して、半導
体チップ1(図1参照)が搭載された素子搭載基板2を
備える装置本体部3をプリント基板5上にはんだバンプ
4を介して配置する。Further, the solder bumps 4 are supplied on predetermined positions on the printed circuit board 5, and then, as shown in FIG. A space slightly larger than a) is formed, and the device main body 3 including the element mounting board 2 on which the semiconductor chip 1 (see FIG. 1) is mounted is arranged on the printed board 5 via the solder bumps 4.
【0049】この際、素子搭載基板2の所定のバンプ搭
載電極2bと、プリント基板5の所定のバンプ搭載電極
5aとをはんだバンプ4を介して両者を対応させた位置
に配置する。At this time, the predetermined bump mounting electrode 2b of the element mounting board 2 and the predetermined bump mounting electrode 5a of the printed board 5 are arranged at positions corresponding to each other via the solder bumps 4.
【0050】その後、所定温度、例えば、200〜24
0℃の高温雰囲気が形成されたリフロー炉(図示せず)
に、図3(a)に示す状態の装置本体部3と素子搭載基
板2とを搬入し、これらを前記リフロー炉に通す。Thereafter, at a predetermined temperature, for example, 200 to 24
Reflow furnace (not shown) with high temperature atmosphere of 0 ° C
Then, the apparatus body 3 and the element mounting substrate 2 in the state shown in FIG. 3A are carried in, and they are passed through the reflow furnace.
【0051】続いて、前記リフロー炉において、はんだ
バンプ4が加熱されて溶融すると、放熱部材9の重量や
素子搭載基板2自身の重量によって、装置本体部3が僅
かに下降する。Subsequently, when the solder bumps 4 are heated and melted in the reflow furnace, the device main body 3 is slightly lowered due to the weight of the heat radiation member 9 and the weight of the element mounting board 2 itself.
【0052】この際、支持部材6の熱膨張係数は、はん
だバンプ4の熱膨張係数より大きいため、支持部材6も
熱膨張している。At this time, since the thermal expansion coefficient of the support member 6 is larger than the thermal expansion coefficient of the solder bump 4, the support member 6 is also thermally expanded.
【0053】そこで、はんだバンプ4が溶融して装置本
体部3が下降すると、図3(b)に示すように、支持部
材6がプリント基板5に接触し、支持部材6によって装
置本体部3を支持することができる。Then, when the solder bumps 4 melt and the apparatus main body 3 descends, as shown in FIG. 3B, the support member 6 comes into contact with the printed circuit board 5, and the support body 6 causes the apparatus main body 3 to move. Can be supported.
【0054】その結果、装置本体部3は支持部材6によ
って支えられるため、これ以上下降することはない。し
たがって、はんだバンプ4溶融時のバンプ潰れの発生を
防ぐことができる。As a result, since the apparatus main body 3 is supported by the support member 6, it does not descend further. Therefore, the occurrence of bump crushing when the solder bumps 4 are melted can be prevented.
【0055】言い換えると、はんだバンプ4の接続高さ
(図3(b)におけるはんだバンプ4の高さ)は、支持
部材6の高さhより低くなることはない。In other words, the connection height of the solder bump 4 (the height of the solder bump 4 in FIG. 3B) does not become lower than the height h of the support member 6.
【0056】これにより、支持部材6によって装置本体
部3を支持しながら、はんだバンプ4によって素子搭載
基板2とプリント基板5とを電気的に接続する。Thus, the device mounting board 2 and the printed board 5 are electrically connected by the solder bumps 4 while supporting the apparatus main body 3 by the support member 6.
【0057】その後、前記リフロー炉の外に前記半導体
装置を搬出する。Thereafter, the semiconductor device is carried out of the reflow furnace.
【0058】所定時間経過後、はんだバンプ4は冷えて
常温に戻り硬化する。After a lapse of a predetermined time, the solder bump 4 cools down to room temperature and hardens.
【0059】さらに、図3(c)に示すように、はんだ
バンプ4の硬化にともなって支持部材6も冷えて収縮す
る。Further, as shown in FIG. 3C, as the solder bumps 4 are hardened, the support member 6 also cools and contracts.
【0060】この時、ガラスエポキシ樹脂からなる支持
部材6は、はんだより熱膨張係数が大きく、予め、装置
本体部3実装後のはんだバンプ4の高さより低くなるよ
うに形成されたものであるため、高さhまで収縮し、こ
れによって、支持部材6とプリント基板5との間には間
隙aが形成される。At this time, the support member 6 made of glass epoxy resin is formed so as to have a larger coefficient of thermal expansion than solder and to be lower than the height of the solder bumps 4 after the device main body 3 is mounted. , To a height h, whereby a gap a is formed between the support member 6 and the printed board 5.
【0061】その結果、支持部材6とプリント基板5と
の間に間隙aを形成した状態で、装置本体部3をプリン
ト基板5上にはんだバンプ4を介して実装でき、これに
より、装置本体部3とプリント基板5とがはんだバンプ
4によって電気的に接続される。As a result, the device body 3 can be mounted on the printed circuit board 5 via the solder bumps 4 with the gap a formed between the support member 6 and the printed circuit board 5. 3 and the printed board 5 are electrically connected by the solder bumps 4.
【0062】なお、間隙aが形成されていることによ
り、はんだバンプ4は装置本体部3自身からの荷重以外
のストレスを受けることはなく、自由度を維持した状態
でバンプ接合している。Since the gap a is formed, the solder bumps 4 are not subjected to any stress other than the load from the device main body 3 itself, and are bonded to each other with the degree of freedom maintained.
【0063】本実施の形態の半導体装置およびその実装
方法によれば、以下のような作用効果が得られる。According to the semiconductor device of this embodiment and the method of mounting the same, the following operation and effect can be obtained.
【0064】すなわち、前記半導体装置の装置本体部3
をプリント基板5に実装する際、はんだバンプ4の溶融
時に装置本体部3を支持する支持部材6を有しているこ
とにより、装置本体部3の重量が増えてもはんだバンプ
4溶融時のはんだバンプ4の高さを支持部材6によって
制御して装置本体部3をプリント基板5に実装できる。That is, the device main body 3 of the semiconductor device
When the solder bumps 4 are melted, the supporting members 6 that support the device body 3 when the solder bumps 4 are melted are provided even when the weight of the device body 3 increases. The apparatus main body 3 can be mounted on the printed circuit board 5 by controlling the height of the bumps 4 with the support member 6.
【0065】これにより、はんだバンプ4溶融時のバン
プ潰れを防止でき、その結果、はんだバンプ4同士のシ
ョートを防ぐことができるとともに、はんだバンプ4の
接続信頼性を向上できる。As a result, bump crushing when the solder bumps 4 are melted can be prevented. As a result, short-circuiting between the solder bumps 4 can be prevented, and connection reliability of the solder bumps 4 can be improved.
【0066】また、はんだバンプ4溶融時に装置本体部
3を支持部材6によって支持することにより、装置本体
部3の重量が増えてもはんだバンプ4を潰すことなく、
装置本体部3を支持することができる。Further, by supporting the apparatus main body 3 by the supporting member 6 when the solder bumps 4 are melted, the solder bumps 4 are not crushed even if the weight of the apparatus main body 3 increases.
The device main body 3 can be supported.
【0067】これにより、半導体チップ1に大きな放熱
部材9(例えば、図6に示す放熱部材9)を取り付ける
ことが可能になり、半導体チップ1の放熱性を向上でき
るとともに、装置本体部3を備えた半導体装置の高性能
化を図ることができる。As a result, a large heat radiating member 9 (for example, the heat radiating member 9 shown in FIG. 6) can be attached to the semiconductor chip 1, so that the heat radiating property of the semiconductor chip 1 can be improved and the device main body 3 is provided. The performance of the semiconductor device can be improved.
【0068】さらに、支持部材6によってはんだバンプ
4の高さを制御して装置本体部3を実装することによ
り、実装時のはんだバンプ4の高さ(ここでは、高さH
のこと)を確保することができる。Further, the height of the solder bumps 4 is controlled by the support member 6 to mount the apparatus main body 3, whereby the height of the solder bumps 4 at the time of mounting (here, the height H
) Can be secured.
【0069】これにより、はんだバンプ4の高さが設計
値より低くなることを防げるため、その結果、はんだバ
ンプ4の接続寿命を延ばすことができる。As a result, the height of the solder bumps 4 can be prevented from being lower than the design value, so that the connection life of the solder bumps 4 can be extended.
【0070】また、この支持部材6が、はんだより熱膨
張係数の大きな材料(本実施の形態ではガラスエポキシ
樹脂)によって形成されかつ装置本体部3実装後のはん
だバンプ4の高さより低くなるように形成されているこ
とにより、はんだバンプ4の硬化とともに支持部材6が
冷めて収縮した際に、支持部材6とプリント基板5との
間に間隙aを形成することができる。The supporting member 6 is formed of a material having a larger coefficient of thermal expansion than the solder (in this embodiment, glass epoxy resin), and is lower than the height of the solder bumps 4 after the device main body 3 is mounted. Due to the formation, when the support member 6 cools and shrinks as the solder bumps 4 cure, a gap a can be formed between the support member 6 and the printed board 5.
【0071】これにより、装置本体部3実装後、支持部
材6に起因する応力がはんだバンプ4に対して働くこと
を防げる。つまり、はんだバンプ4は、このはんだバン
プ4が本来有しているバンプ高さ方向の自由度を拘束さ
れることがない。As a result, it is possible to prevent the stress caused by the support member 6 from acting on the solder bumps 4 after mounting the device main body 3. That is, the solder bumps 4 are not restricted in the degree of freedom in the bump height direction which the solder bumps 4 originally have.
【0072】したがって、はんだバンプ4は、その接続
に悪影響を与えられないため、はんだバンプ4の接続寿
命を延ばすことができ、かつ、はんだバンプ4の接続信
頼性を向上できる。Accordingly, since the solder bumps 4 do not adversely affect the connection, the connection life of the solder bumps 4 can be extended, and the connection reliability of the solder bumps 4 can be improved.
【0073】また、支持部材6が装置本体部3の素子搭
載基板2と一体に形成されていることにより、素子搭載
基板2を多層基板として形成する際に、支持部材6も一
緒に形成できるため、装置本体部3における支持部材6
の取り付けを簡略化することができる。Further, since the supporting member 6 is formed integrally with the element mounting substrate 2 of the apparatus main body 3, the supporting member 6 can be formed together when the element mounting substrate 2 is formed as a multilayer substrate. , Support member 6 in device body 3
Can be simplified.
【0074】さらに、支持部材6が枠状に形成され、か
つこの枠状の支持部材6の外周部6aが素子搭載基板2
の外周部2aと同じ大きさに形成されていることによ
り、支持部材6を素子搭載基板2に取り付ける際の位置
決めを簡略化することができる。Further, the supporting member 6 is formed in a frame shape, and the outer peripheral portion 6a of the frame-shaped supporting member 6 is
Is formed to have the same size as the outer peripheral portion 2a, the positioning at the time of attaching the support member 6 to the element mounting substrate 2 can be simplified.
【0075】これにより、前記同様、装置本体部3にお
ける支持部材6の取り付けを簡略化することができる。Thus, the mounting of the support member 6 on the apparatus main body 3 can be simplified as described above.
【0076】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記発明の実施の形態に限定されるものではなく、その
要旨を逸脱しない範囲で種々変更可能であることは言う
までもない。Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.
【0077】例えば、前記実施の形態で説明した半導体
装置においては、支持部材6が枠状でかつ素子搭載基板
2と一体に形成される場合について説明したが、図4ま
たは図5に示す他の実施の形態の支持部材6の設置状態
のように、素子搭載基板2の4つの角部2cのそれぞれ
に(図4参照)、もしくは、素子搭載基板2の4つの辺
の中央付近のそれぞれに(図5参照)、高さhの4つの
支持部材6を取り付けてもよい。For example, in the semiconductor device described in the above embodiment, the case where the supporting member 6 is frame-shaped and formed integrally with the element mounting substrate 2 has been described. As in the installation state of the support member 6 according to the embodiment, each of the four corners 2c of the element mounting substrate 2 (see FIG. 4) or each near the center of the four sides of the element mounting substrate 2 (see FIG. 5), and four support members 6 having a height h may be attached.
【0078】これによっても前記実施の形態で説明した
作用効果と同様の作用効果が得られる。According to this, the same operation and effect as those described in the above embodiment can be obtained.
【0079】また、前記実施の形態の半導体装置におい
ては、図1に示すように、放熱部材9が素子搭載基板2
と同じ程度の大きさの場合について説明したが、図6に
示す他の実施の形態の半導体装置のように素子搭載基板
2よりも大きな放熱部材9を取り付けた半導体装置であ
ってもよい。Further, in the semiconductor device of the above embodiment, as shown in FIG.
Although the case where the size is about the same as that described above, a semiconductor device to which a heat dissipating member 9 larger than the element mounting substrate 2 is attached as in the semiconductor device according to another embodiment shown in FIG.
【0080】この半導体装置においても、素子搭載基板
2に支持部材6が設けられているため、図1に示した半
導体装置と同様の作用効果が得られ、かつ、前記半導体
装置における放熱効果をさらに向上でき、その結果、前
記半導体装置の性能を向上できる。Also in this semiconductor device, since the supporting member 6 is provided on the element mounting substrate 2, the same operation and effect as those of the semiconductor device shown in FIG. 1 are obtained, and the heat radiation effect of the semiconductor device is further improved. As a result, the performance of the semiconductor device can be improved.
【0081】また、前記実施の形態および図4〜図6に
示す他の実施の形態においては、支持部材6が素子搭載
基板2に設けられる場合について説明したが、図7に示
す他の実施の形態の半導体装置のように、支持部材6は
マザーボード10(実装基板)に設けられていてもよ
い。In the above embodiment and the other embodiments shown in FIGS. 4 to 6, the case where the supporting member 6 is provided on the element mounting board 2 has been described. However, in the other embodiment shown in FIG. The support member 6 may be provided on the motherboard 10 (mounting substrate) as in the semiconductor device of the embodiment.
【0082】すなわち、予め、支持部材6が所定箇所に
設けられたマザーボード10を準備し、その後、前記実
施の形態の半導体装置の実装方法と同様の方法で装置本
体部3をマザーボード10に実装して半導体装置を製造
する。That is, a motherboard 10 provided with a support member 6 at a predetermined position is prepared in advance, and then the device main body 3 is mounted on the motherboard 10 by the same method as the semiconductor device mounting method of the above-described embodiment. To manufacture a semiconductor device.
【0083】なお、図7に示す他の実施の形態の半導体
装置の場合、支持部材6が実装基板であるマザーボード
10に設けられていることにより、装置本体部3の実装
後には、支持部材6と素子搭載基板2との間に間隙a
(図3(c)参照)が形成される。In the case of the semiconductor device according to another embodiment shown in FIG. 7, since the support member 6 is provided on the motherboard 10 which is a mounting substrate, the support member 6 is mounted after the device body 3 is mounted. A between the device and the substrate 2
(See FIG. 3C).
【0084】これにより、図7に示す半導体装置によっ
ても、前記実施の形態で説明した作用効果と同様の作用
効果が得られる。As a result, the same function and effect as those described in the above embodiment can be obtained by the semiconductor device shown in FIG.
【0085】また、支持部材6は、前記実施の形態およ
び前記他の実施の形態で説明したものに限らず、はんだ
バンプ4のはんだより熱膨張係数が大きく、かつ、予
め、装置本体部3実装後のはんだバンプ4の高さより低
くなるように形成されたものであれば、その形状、設置
数および設置位置は、特に限定されるものではない。The support member 6 is not limited to those described in the above embodiment and the other embodiments. The support member 6 has a larger coefficient of thermal expansion than the solder of the solder bump 4, and is mounted on the device body 3 in advance. The shape, the number of installations, and the installation positions are not particularly limited as long as they are formed so as to be lower than the height of the later solder bump 4.
【0086】例えば、支持部材6の形状については、円
柱、角柱、あるいは、球などであってもよい。For example, the shape of the support member 6 may be a cylinder, a prism, a sphere, or the like.
【0087】さらに、支持部材6の材料についてもガラ
スエポキシ樹脂以外のものであってもよい。Further, the material of the support member 6 may be other than glass epoxy resin.
【0088】また、素子搭載基板2についても、その材
料は、ガラスエポキシ樹脂に限定されるものではなく、
例えば、アルミナやセラミックなどであってもよい。Further, the material of the element mounting board 2 is not limited to glass epoxy resin, either.
For example, alumina or ceramic may be used.
【0089】さらに、前記実施の形態あるいは他の実施
の形態の半導体装置においては、半導体チップ1の封止
(保護)が封止樹脂8による樹脂封止の場合につい説明
したが、前記封止は、樹脂封止に限らず、キャップなど
を用いた封止であってもよい。Further, in the semiconductor device according to the above embodiment or another embodiment, the case where the semiconductor chip 1 is sealed (protected) with the sealing resin 8 is described. The present invention is not limited to resin sealing, but may be sealing using a cap or the like.
【0090】また、半導体チップ1と素子搭載基板2と
の電気的接続は、CCBバンプ接続に限らず、素子搭載
基板2に半導体チップ1をその表裏を反転させて取り付
け、その後、ワイヤボンドによって行うワイヤボンディ
ング接続であってもよい。The electrical connection between the semiconductor chip 1 and the element mounting substrate 2 is not limited to the CCB bump connection, but the semiconductor chip 1 is mounted on the element mounting substrate 2 with its front and back inverted, and thereafter, wire bonding is performed. Wire bonding connection may be used.
【0091】[0091]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.
【0092】(1).半導体装置の装置本体部を実装基
板に実装する際、はんだバンプの溶融時に装置本体部を
支持する支持部材を有していることにより、はんだバン
プ溶融時のバンプ潰れを防止できる。その結果、はんだ
バンプ同士のショートを防ぐことができるとともに、は
んだバンプの接続信頼性を向上できる。(1). When the device main body of the semiconductor device is mounted on the mounting board, the support member that supports the device main body when the solder bump is melted can prevent bump crushing when the solder bump melts. As a result, a short circuit between the solder bumps can be prevented, and the connection reliability of the solder bumps can be improved.
【0093】(2).はんだバンプ溶融時に装置本体部
を支持部材によって支持することにより、装置本体部の
重量が増えてもはんだバンプを潰すことなく、装置本体
部を支持することができる。これにより、半導体素子に
大きな放熱部材を取り付けることが可能になり、半導体
素子の放熱性を向上できるとともに、半導体装置の高性
能化を図ることができる。(2). By supporting the apparatus main body by the supporting member when the solder bumps are melted, the apparatus main body can be supported without crushing the solder bumps even if the weight of the apparatus main body increases. This makes it possible to attach a large heat radiation member to the semiconductor element, thereby improving the heat radiation of the semiconductor element and improving the performance of the semiconductor device.
【0094】(3).支持部材によってはんだバンプの
高さを制御して装置本体部を実装することにより、実装
時のはんだバンプの高さを確保することができる。これ
により、はんだバンプの高さが低くなることを防げるた
め、その結果、はんだバンプの接続寿命を延ばすことが
できる。(3). By mounting the device body by controlling the height of the solder bumps by the support member, the height of the solder bumps during mounting can be ensured. As a result, the height of the solder bump can be prevented from being reduced, and as a result, the connection life of the solder bump can be extended.
【0095】(4).支持部材が、はんだより熱膨張係
数の大きな材料によって形成されかつ装置本体部実装後
のはんだバンプの高さより低くなるように形成されてい
ることにより、装置本体部実装後、支持部材に起因する
応力がはんだバンプに対して働くことを防げる。したが
って、はんだバンプは、その接続に悪影響を与えられな
いため、はんだバンプの接続寿命を延ばすことができ、
かつ、はんだバンプの接続信頼性を向上できる。(4). Since the supporting member is formed of a material having a larger coefficient of thermal expansion than solder and is formed to be lower than the height of the solder bump after mounting the device main body, the stress caused by the supporting member after mounting the device main body. Prevents working on solder bumps. Therefore, since the solder bump does not adversely affect the connection, the connection life of the solder bump can be extended,
In addition, the connection reliability of the solder bump can be improved.
【図1】本発明による半導体装置の構造の実施の形態の
一例を示す断面図である。FIG. 1 is a sectional view showing an example of an embodiment of a structure of a semiconductor device according to the present invention.
【図2】本発明の半導体装置の素子搭載基板における支
持部材の設置状態の実施の形態の一例を示す底面図であ
る。FIG. 2 is a bottom view showing an example of an embodiment in which a support member is installed on an element mounting substrate of the semiconductor device of the present invention.
【図3】(a),(b),(c)は本発明の半導体装置の実
装方法の実施の形態の一例を示す拡大部分断面図であ
る。FIGS. 3A, 3B, and 3C are enlarged partial cross-sectional views illustrating an example of an embodiment of a method of mounting a semiconductor device according to the present invention.
【図4】本発明の他の実施の形態である半導体装置の素
子搭載基板における支持部材の設置状態を示す底面図で
ある。FIG. 4 is a bottom view showing an installation state of a support member on an element mounting board of a semiconductor device according to another embodiment of the present invention.
【図5】本発明の他の実施の形態である半導体装置の素
子搭載基板における支持部材の設置状態を示す底面図で
ある。FIG. 5 is a bottom view showing an installation state of a support member on an element mounting board of a semiconductor device according to another embodiment of the present invention.
【図6】本発明の他の実施の形態である半導体装置の構
造を示す断面図である。FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device according to another embodiment of the present invention.
【図7】本発明の他の実施の形態である半導体装置の構
造を示す断面図である。FIG. 7 is a cross-sectional view illustrating a structure of a semiconductor device according to another embodiment of the present invention.
1 半導体チップ(半導体素子) 1a 電極形成面 1b 表面 2 素子搭載基板 2a 外周部 2b バンプ搭載電極 2c 角部 3 装置本体部 4 はんだバンプ 5 プリント基板(実装基板) 5a バンプ搭載電極 6 支持部材 6a 外周部 7 CCBバンプ 8 封止樹脂 9 放熱部材 10 マザーボード(実装基板) H 装置本体部実装後のはんだバンプの高さ h 支持部材の高さ a 間隙 DESCRIPTION OF SYMBOLS 1 Semiconductor chip (semiconductor element) 1a Electrode formation surface 1b Surface 2 Element mounting board 2a Perimeter 2b Bump mounting electrode 2c Corner 3 Device main body 4 Solder bump 5 Printed board (mounting board) 5a Bump mounting electrode 6 Supporting member 6a Outer circumference Part 7 CCB bump 8 Sealing resin 9 Heat dissipating member 10 Mother board (mounting board) H Height of solder bump after mounting device body h Height of supporting member a Gap
Claims (8)
装された半導体装置であって、 半導体素子が搭載された前記素子搭載基板を備える装置
本体部と、 前記装置本体部を前記はんだバンプを介して実装する実
装基板と、 前記はんだバンプを形成するはんだより熱膨張係数の大
きな材料によって形成され、かつ前記装置本体部実装後
の前記はんだバンプの高さより低く形成された支持部材
とを有し、 前記装置本体部を前記はんだバンプを介して前記実装基
板に実装する際の前記はんだバンプの溶融時に、前記支
持部材が前記素子搭載基板と前記実装基板とに接触して
前記装置本体部を支持することを特徴とする半導体装
置。1. A semiconductor device in which an element mounting board is mounted via solder bumps, wherein the apparatus main body includes the element mounting board on which a semiconductor element is mounted, and the device main body is connected via the solder bumps. And a support member formed of a material having a larger coefficient of thermal expansion than the solder forming the solder bumps, and formed lower than the height of the solder bumps after mounting the device main body, When the solder bumps are melted when the device body is mounted on the mounting board via the solder bumps, the support member contacts the element mounting board and the mounting board to support the device body. A semiconductor device characterized by the above-mentioned.
記支持部材が前記装置本体部の前記素子搭載基板に設け
られ、かつ前記装置本体部の前記実装基板への実装後に
前記支持部材と前記実装基板との間に間隙が形成されて
いることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the support member is provided on the element mounting board of the device main body, and the support member is mounted on the device main body after the device main body is mounted on the mounting board. A semiconductor device, wherein a gap is formed between the semiconductor device and the mounting substrate.
記支持部材が前記実装基板に設けられ、かつ前記装置本
体部の前記実装基板への実装後に前記支持部材と前記素
子搭載基板との間に間隙が形成されていることを特徴と
する半導体装置。3. The semiconductor device according to claim 1, wherein the support member is provided on the mounting board, and the support member and the element mounting board are connected to each other after the device body is mounted on the mounting board. A semiconductor device, wherein a gap is formed between the semiconductor devices.
って、前記支持部材が前記装置本体部の前記素子搭載基
板と一体に形成され、かつ前記装置本体部の前記実装基
板への実装後に前記支持部材と前記実装基板との間に間
隙が形成されていることを特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein the support member is formed integrally with the element mounting board of the device main body, and after the device main body is mounted on the mounting substrate. A semiconductor device, wherein a gap is formed between the support member and the mounting substrate.
装置であって、前記支持部材が枠状に形成され、かつこ
の枠状の外周部が前記素子搭載基板の外周部と同じ大き
さに形成されていることを特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein said support member is formed in a frame shape, and said frame-shaped outer peripheral portion has the same size as the outer peripheral portion of said element mounting substrate. A semiconductor device characterized by being formed in the above.
導体装置であって、前記装置本体部において前記半導体
素子の電極形成面と反対側の背面に放熱部材が取り付け
られていることを特徴とする半導体装置。6. The semiconductor device according to claim 1, wherein a heat radiating member is attached to a rear surface of the device main body opposite to an electrode forming surface of the semiconductor element. A semiconductor device characterized by the above-mentioned.
方法であって、 前記半導体装置の装置本体部を実装した後のはんだバン
プの高さより低く形成され、かつ前記はんだバンプのは
んだより熱膨張係数の大きな材料によって形成された支
持部材を有する素子搭載基板または実装基板を準備する
工程と、 前記素子搭載基板に半導体素子を搭載して前記装置本体
部を形成する工程と、 前記支持部材と前記実装基板または前記素子搭載基板と
の間に間隙を形成して、前記半導体素子が搭載された前
記素子搭載基板を備える前記装置本体部を前記実装基板
上に前記はんだバンプを介して配置する工程と、 前記はんだバンプを溶融し、前記支持部材によって前記
装置本体部を支持しながら前記はんだバンプによって前
記素子搭載基板と前記実装基板とを電気的に接続する工
程と、 前記はんだバンプを硬化させるとともに前記支持部材を
収縮させて、前記支持部材と前記実装基板または前記素
子搭載基板との間に間隙を形成した状態で、前記装置本
体部を前記実装基板上に前記はんだバンプを介して実装
する工程とを有することを特徴とする半導体装置の実装
方法。7. A method of mounting a semiconductor device having an element mounting board, wherein the semiconductor device is formed to have a height lower than a height of a solder bump after mounting a device main body of the semiconductor device, and is thermally expanded more than solder of the solder bump. A step of preparing an element mounting board or a mounting board having a support member formed of a material having a large coefficient; a step of mounting a semiconductor element on the element mounting board to form the device main body; Forming a gap between the mounting board or the element mounting board, and arranging the device main body including the element mounting board on which the semiconductor element is mounted via the solder bumps on the mounting board; and Melting the solder bumps and supporting the device main body by the support member while the element mounting board and the mounting board by the solder bumps; Electrically connecting the device body; and curing the solder bumps and contracting the support member to form a gap between the support member and the mounting board or the element mounting board. Mounting a portion on the mounting board via the solder bumps.
方法であって、 前記半導体装置の装置本体部を実装した後のはんだバン
プの高さより低く形成され、かつ前記はんだバンプのは
んだより熱膨張係数の大きな材料によって形成された支
持部材を有する素子搭載基板を準備する工程と、 前記素子搭載基板に半導体素子を搭載して前記装置本体
部を形成する工程と、 前記支持部材と前記実装基板との間に間隙を形成して、
前記半導体素子が搭載された前記素子搭載基板を備える
前記装置本体部を前記実装基板上に前記はんだバンプを
介して配置する工程と、 前記はんだバンプを溶融し、前記支持部材によって前記
装置本体部を支持しながら前記はんだバンプによって前
記素子搭載基板と前記実装基板とを電気的に接続する工
程と、 前記はんだバンプを硬化させるとともに前記支持部材を
収縮させて、前記支持部材と前記実装基板との間に間隙
を形成した状態で、前記装置本体部を前記実装基板上に
前記はんだバンプを介して実装する工程とを有すること
を特徴とする半導体装置の実装方法。8. A method of mounting a semiconductor device having an element mounting substrate, wherein the semiconductor device is formed to have a height lower than a height of a solder bump after mounting a device main body of the semiconductor device, and is thermally expanded more than solder of the solder bump. A step of preparing an element mounting substrate having a supporting member formed of a material having a large coefficient; a step of mounting a semiconductor element on the element mounting substrate to form the device main body; and the supporting member and the mounting substrate. Form a gap between
Arranging the device main body including the element mounting board on which the semiconductor element is mounted via the solder bumps on the mounting board; melting the solder bumps; and supporting the device main body by the support member. Electrically connecting the element mounting board and the mounting board by the solder bumps while supporting, and hardening the solder bumps and shrinking the support member, so that the space between the support member and the mounting board is reduced. Mounting the device body on the mounting board via the solder bumps in a state where a gap is formed in the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19699497A JPH1140608A (en) | 1997-07-23 | 1997-07-23 | Semiconductor device and its mounting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19699497A JPH1140608A (en) | 1997-07-23 | 1997-07-23 | Semiconductor device and its mounting method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH1140608A true JPH1140608A (en) | 1999-02-12 |
Family
ID=16367069
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19699497A Pending JPH1140608A (en) | 1997-07-23 | 1997-07-23 | Semiconductor device and its mounting method |
Country Status (1)
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JP (1) | JPH1140608A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6946732B2 (en) * | 2000-06-08 | 2005-09-20 | Micron Technology, Inc. | Stabilizers for flip-chip type semiconductor devices and semiconductor device components and assemblies including the same |
US8101459B2 (en) | 2001-08-24 | 2012-01-24 | Micron Technology, Inc. | Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween |
WO2013148927A1 (en) * | 2012-03-30 | 2013-10-03 | Advanced Micro Devices, Inc. | Universal interconnect footprint for bonding semiconductor substrates |
JP2013222833A (en) * | 2012-04-17 | 2013-10-28 | Toshiba Corp | Electronic component and electronic apparatus |
WO2022172673A1 (en) * | 2021-02-09 | 2022-08-18 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device and electronic device |
-
1997
- 1997-07-23 JP JP19699497A patent/JPH1140608A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6946732B2 (en) * | 2000-06-08 | 2005-09-20 | Micron Technology, Inc. | Stabilizers for flip-chip type semiconductor devices and semiconductor device components and assemblies including the same |
US7041533B1 (en) | 2000-06-08 | 2006-05-09 | Micron Technology, Inc. | Stereolithographic method for fabricating stabilizers for semiconductor devices |
US8101459B2 (en) | 2001-08-24 | 2012-01-24 | Micron Technology, Inc. | Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween |
WO2013148927A1 (en) * | 2012-03-30 | 2013-10-03 | Advanced Micro Devices, Inc. | Universal interconnect footprint for bonding semiconductor substrates |
JP2013222833A (en) * | 2012-04-17 | 2013-10-28 | Toshiba Corp | Electronic component and electronic apparatus |
WO2022172673A1 (en) * | 2021-02-09 | 2022-08-18 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device and electronic device |
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