JP2015076511A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of positioning a substrate with high speed, with high accuracy and with ease.SOLUTION: A semiconductor device 100 comprises: a substrate 4 including an insulation layer 42, a circuit layer 41 and a heat dissipation layer 43 having a rectangular plane shape of a plane size smaller than that of the insulation layer 42; a base 6; a solder 5 under the substrate for connecting the heat dissipation layer 43 and the base 6; and positioning wires 9 provided on a surface the same with a surface of the base 6 to which the substrate 4 is fixed via the solder 5 under the substrate. The positioning wires 9 are arranged in at least two regions, respectively, which are regions sandwiched by the insulation layer 42 and the base 6 and extend along two sides orthogonal to each other of a rectangular plane shape of the heat dissipation layer 43, respectively.

Description

  The present invention relates to a semiconductor device capable of positioning a substrate easily at high speed, with high accuracy and suitable for mass production.

  Semiconductor devices typified by power semiconductor devices are widely used for control of electronic equipment such as high-power motors and generators and for power conversion. An example of such a semiconductor device is an IGBT (Insulated Gate Bipolar Transistor) module.

  In recent years, the demand for semiconductor devices as power control devices mounted on power generation systems such as wind power, railways, electric vehicles, hybrid vehicles, and the like has been increasing. Therefore, a structure and a manufacturing method that are easy to assemble and are suitable for mass production are required. In order to meet this requirement, techniques described in Patent Documents 1 to 8 are known as techniques for providing a semiconductor device that can be easily assembled.

JP 2013-38224 A JP 2013-115297 A JP 2009-188327 A JP 2008-243877 A JP-A-2-266557 US Pat. No. 5,497,289 US Patent Application Publication No. 2003/0151128 US Patent Application Publication No. 2009/0039498

  When soldering a substrate onto a base in an assembling process of a semiconductor device, the substrate is usually positioned by providing a positioning member such as a jig on the base. However, the preparation of jigs and their attachment and removal may require a lot of time and manufacturing costs. It is conceivable to provide unevenness on the surface of the base without using a jig and substitute it as a positioning member. However, in order to process the unevenness with high accuracy, a large processing cost may be required.

  An object of the present invention is to provide a semiconductor device capable of positioning a substrate at high speed, high accuracy and easily suitable for mass production.

  In order to achieve the above object, in the semiconductor device of the present invention, an electronic component (for example, substrate 4) including a semiconductor chip is disposed on a base via solder (for example, solder under substrate 5), and the solder is reflow-heated. A soldering and soldering semiconductor device comprising a positioning wire for positioning the placement of solder and electronic components on a base, and placing the solder and electronic components in accordance with the positioning wire, after reflow heating The electronic component is sealed with a sealant.

  The electronic component has an insulating layer, a circuit layer having a smaller plane dimension than the insulating layer and formed on one surface of the insulating layer, and a rectangular planar shape having a smaller plane dimension than the insulating layer. A heat dissipation layer formed on the other surface of the insulating layer, and the positioning wire is a portion of the other surface of the insulating layer other than the portion in contact with the heat dissipation layer (for example, the surface 42a). And a portion of the surface to which the base substrate is fixed, which is sandwiched between portions other than the portion in contact with the solder, and at least two regions along at least two sides orthogonal to each other of the rectangular planar shape of the heat dissipation layer It is characterized by being arranged one by one.

  According to the present invention, it is possible to provide a semiconductor device capable of positioning a substrate easily at high speed, high accuracy and suitable for mass production.

1A is a semiconductor device according to a first embodiment, FIG. 3A is a top view, and FIG. 3 is a flowchart showing a method for manufacturing a semiconductor device. It is explanatory drawing which shows the manufacturing method of a semiconductor device. It is a top view which shows the example of arrangement | positioning of the positioning wire in a semiconductor device. It is sectional drawing which shows the example of arrangement | positioning of the positioning wire in a semiconductor device. It is a semiconductor device which concerns on 2nd Embodiment, (a) is a side view, (b) is a perspective view of the wire for positioning. It is a semiconductor device which concerns on 3rd Embodiment, (a) is a perspective view, (b) is a top view, (c) is a perspective view of the positioning wire. It is a top view which shows the other example of arrangement | positioning of the positioning wire in a semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[1. First Embodiment]
<Configuration>
1A and 1B show a semiconductor device according to the first embodiment, in which FIG. 1A is a top view and FIG. 1B is a cross-sectional view. FIG. 1A is a top view of the semiconductor device 100 according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. In FIG. 1A, the sealant 8 shown in FIG. 1B is omitted. The semiconductor device 100 includes an IGBT chip 1, a diode chip 2, a solder under chip 3, a substrate 4 (electronic component), a solder under substrate 5, a base 6, a case 7, a sealant 8, a wiring wire 10, and a positioning wire 9. Is provided.

  The substrate 4 (electronic component) is composed of three layers: a circuit layer 41, an insulating layer 42, and a heat dissipation layer 43. The circuit layer 41 has a smaller planar dimension than the insulating layer 42, and is formed on one surface of the insulating layer 42. The heat dissipation layer 43 has a smaller planar dimension than the insulating layer 42 and is formed on the surface of the insulating layer 42 opposite to the surface on which the circuit layer 41 is formed. The IGBT chip 1 and the diode chip 2 are each connected to the circuit layer 41 via the under-chip solder 3. The heat dissipation layer 43 is connected to the base 6 via the under-substrate solder 5. The wiring wire 10 is connected to the upper surfaces of the IGBT chip 1, the diode chip 2, and the circuit layer 41.

  The positioning wire 9 is connected to the upper surface of the base 6, and is sandwiched between the base 6 and a portion (for example, the surface 42 a) other than the portion in contact with the heat dissipation layer 43 in the surface on the heat dissipation layer 43 side of the insulating layer 42. Arranged in the area. Although the details will be described later, the present invention is characterized in that the positioning wire 9 is provided, and the positioning of the substrate 4 and the under-substrate solder 5 is performed using the positioning wire 9.

  The case 7 is installed on the upper surface of the base 6 so as to surround the substrate 4. A region surrounded by the case 7 and the base 6 is filled with a sealant 8.

  The circuit layer 41 and the wiring wire 10 are made of a metal such as aluminum or copper. The wiring wire 10 is a wire having a diameter of several tens to several hundreds of μm, and the optimum diameter and number depend on the energization amount necessary for each device. The IGBT chip 1 and the diode chip 2 are connected to the circuit layer 41 by the wiring wire 10 to constitute electric wiring for power conversion and control.

  The insulating layer 42 is made of a material having low electrical conductivity such as silicon nitride, aluminum nitride, or alumina. The insulating layer 42 electrically separates the heat dissipation layer 43 or the base 6 from the circuit layer 41.

  The heat dissipation layer 43 and the base 6 are made of a metal having high thermal conductivity such as aluminum and copper, and dissipate heat generated during the operation of the IGBT chip 1 and the diode chip 2. The thickness of the heat dissipation layer 43 and the under-substrate solder 5 is several hundred μm.

  The positioning wire 9 is a wire made of a metal such as aluminum or copper, and has a diameter larger than the thickness of the under-substrate solder 5 and smaller than the total thickness of the heat dissipation layer 43 and the under-substrate solder 5 and several tens of μm to several hundred μm.

  The positioning wire 9 and the wiring wire 10 need not have the same material and cross-sectional shape, and even if they are not the same, the effects of the present invention can be sufficiently obtained. However, if the material and the cross-sectional shape are the same, the manufacturing cost can be reduced to the extent that the wire member and the manufacturing apparatus can be shared.

  The case 7 is made of a resin such as PBT (PolyButylene Terephthalate) or PPS (PolyPhenylene Sulfide). The sealant 8 is made of an insulating member such as silicon gel.

<Manufacturing method>
FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device. FIG. 3 is an explanatory view showing a method of manufacturing a semiconductor device, wherein (a) to (e) are steps for manufacturing a substrate 4 (electronic component), and (f) to (h) are based on the substrate 4. 6 is a mounting process. The manufacturing method of the semiconductor device 100 will be described as appropriate with reference to FIG.

(Step S1): First, on the substrate 4 shown in FIG. 3A, a carbon jig 11 having a hole 12 having a width several hundred μm larger than the planar dimensions of the IGBT chip 1 and the diode chip 2 which are semiconductor chips is provided. Mount and mount (see FIG. 3B).

(Step S2): Along the hole 12, the under-chip solder 3, the IGBT chip 1 which is a semiconductor chip, and the diode chip 2 are placed on the upper surface of the circuit layer 41 (see FIG. 3C). And the IGBT chip 1 and the diode chip 2 are fixed to the upper surface of the circuit layer 41 via the under-chip solder 3 by heating the whole in a reflow furnace.

(Step S3): After the reflow, the carbon jig 11 is removed (see FIG. 3D).

(Step S4): Next, the wiring wire 10 is connected to the upper surfaces of the IGBT chip 1, the diode chip 2, and the circuit layer 3 (see FIG. 3E). Ultrasonic bonding is used as a connection method. Ultrasonic bonding is a technique in which a tool is placed on a connecting portion and connected by applying ultrasonic vibration and pressure simultaneously. Many devices that can be connected at high speed with high positional accuracy have been developed for high-density electrical wiring.

(Step S5): Next, the positioning wire 9 is attached to the upper surface of the base 6 (see FIG. 3F). As an attachment method, ultrasonic bonding similar to that of the wiring wire 10 is used.

(Step S6): Next, the sheet-like under-substrate solder 5 is placed on the upper surface of the base 6, and the substrate 4 is placed on the under-substrate solder 5 (see FIG. 3G). At this time, it is possible to position the under-substrate solder 5 and the substrate 4 by arranging the side-surface of the under-substrate solder 5 and the heat radiation layer 43 so that the side surfaces of the positioning layer 9 are aligned (matched). And the board | substrate 4 is fixed to the base 6 through the solder 5 under a board | substrate by heating these whole with a reflow furnace.

(Step S7): Next, the case 7 is bonded and fixed to the upper surface of the base 6 with an adhesive or the like, and the space surrounded by the case 7 and the base 6 is filled with the sealant 8 (FIG. 3 (h)). reference). Thus, the semiconductor device 100 is manufactured.

<Effect>
4A and 4B are top views showing examples of positioning wire arrangements in a semiconductor device. FIG. 4A shows a case of four positioning wires, FIG. 4B shows a case of three positioning wires, and FIG. 4C shows a positioning wire. In the case of two wires, (d) is a modification of the three positioning wires. 4A to 4D are top views of the semiconductor device 100. FIG. However, the case 7 and the sealant 8 are omitted. The positioning of the substrate 4 and the under-substrate solder 5 by the positioning wire 9 will be described with reference to FIG.

  At least two positioning wires 9 are arranged in directions orthogonal to each other. 4 may be sufficient as shown to Fig.4 (a), 3 may be sufficient as shown in FIG.4 (b), and 2 may be sufficient as shown in FIG.4 (c). As long as at least two wires are perpendicular to each other, two or more positioning wires 9 may be provided on the same line as shown in FIG.

  If the positioning wires 9 are arranged along the four sides of the heat dissipation layer 43 as shown in FIG. 4A, the positional deviation of the under-substrate solder 5 and the heat dissipation layer 43 hardly occurs during reflow, and positioning accuracy is improved. . If the number of positioning wires 9 is small as shown in FIG. 4B, the time for wire connection is shortened. If the number of positioning wires 9 is small as shown in FIG. Shortened. As shown in FIGS. 4B, 4C, and 4D, when the positioning wire 9 does not surround all four sides of the heat dissipation layer 43, the under-substrate solder 5 and the heat dissipation layer 43 are attached. It becomes easy.

  In the conventional manufacturing method, a jig such as carbon is generally used for positioning, but a lot of manufacturing time and cost may be required to prepare, attach, and remove the jig. On the other hand, since the ultrasonic connection device is used to connect the positioning wire 9 to the upper surface of the base 6, it can be installed at high speed with high positional accuracy. Furthermore, since the positioning wire 9 is made of metal, it has high heat resistance and is suitable for a positioning member in high-temperature reflow. Since the positioning wire 9 is made of metal, there is no fear that it will melt and flow when heated in reflow and the positioning accuracy will decrease, and there is also a concern that it will melt and generate gas etc., which will cause corrosion in the furnace. No.

  FIG. 5 is a cross-sectional view illustrating an arrangement example of positioning wires in the semiconductor device. The positioning wire 9 of the semiconductor device 100 is in a region sandwiched between the lower surface (for example, the surface 42 a) of the insulating layer 42 and the base 6, and includes the IGBT chip 1, the diode chip 2, the circuit layer 41, and the wiring wire 10. Separated from electrical wiring. Even when a high voltage acts on the electrical wiring, electrical insulation can be ensured by shortening the width L of the heat dissipation layer 43 and the under-substrate solder 5.

  When the width L is shortened, the distance between the end portion of the insulating layer 42 and the positioning wire 9 increases, and the creeping insulation distance between the circuit layer 41 and the positioning wire 9 sandwiching the insulating layer 42 increases. Insulation is sufficiently secured. Therefore, even if the positioning wire 9 is installed on the upper surface of the base 6 after assembling, the electric wiring is not hindered. Therefore, it is not necessary to remove the positioning wire 9, and the manufacturing time can be shortened. Even when the width L is slightly shortened to ensure insulation, the connection between the substrate 4 and the base 6 immediately below the IGBT chip 1 and the diode chip 2 is maintained, so that sufficient heat dissipation can be ensured.

  As described above, according to the first embodiment, it is possible to provide the semiconductor device 100 capable of positioning the substrate 4 easily at high speed, high accuracy, and suitable for mass production.

[2. Second Embodiment]
One of the features of the second embodiment is that the positioning wire 9 is provided with a mountain-shaped portion 92 (FIG. 6B).
<Configuration>
6A and 6B show a semiconductor device according to the second embodiment, in which FIG. 6A is a side view and FIG. 6B is a perspective view of a positioning wire. A semiconductor device 200 according to the second embodiment will be described with reference to FIG. Note that members similar to those of the semiconductor device 100 illustrated in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  6A is a side view of the semiconductor device 200, and FIG. 6B is a perspective view of the positioning wire 9 a of the semiconductor device 200. The semiconductor device 200 includes a positioning wire 9a. Each of the positioning wires 9a includes two or more connecting portions 91 and one or more chevron portions 92 as shown in FIG. 6 (b). The connecting portions 91 at both ends are substantially on the same line, and the positioning wire 9 a is ultrasonically bonded to the base 6 at the connecting portion 91. In the chevron 92, the wire is bent into a chevron. Such a wire shape is a general shape when an electronic wiring is formed by the wiring wire 10 and can be formed with high accuracy and high speed by a normal ultrasonic connection device. The chevron height 93 is equal to the sum of the target thickness of the under-substrate solder 5 and the thickness of the heat dissipation layer 43.

<Effect>
Usually, when positioning with a jig such as carbon, the under-substrate solder 5 may become thin due to the inclination of the substrate 4 during reflow or the like. On the other hand, in the semiconductor device 200, when the surface 42a of the insulating layer 42 and the chevron 92 are in contact with each other, the substrate 4 does not move downward any further. Therefore, the thickness of the lower substrate solder 5 is near the positioning wire 9a. Is kept above the target value.

  By maintaining the thickness of the under-substrate solder 5 at or above the target value, the thermal fatigue life of the under-substrate solder 5 is improved. Generally, a semiconductor device becomes hot due to chip heat generation during operation, and is cooled to an environmental temperature when stopped. Therefore, thermal stress acts between members having different thermal expansion coefficients. For example, the circuit layer 41 and the heat dissipation layer 43 are made of copper, the insulating layer 42 is made of silicon nitride, and the thicknesses of the circuit layer 41, the insulating layer 42, and the heat dissipation layer 43 are 0.5 mm, 0.32 mm, and 0.5 mm, respectively. In this case, the thermal expansion coefficient of the substrate 4 as a whole is about 11 ppm / K. On the other hand, when the base 6 is made of copper, the coefficient of thermal expansion is about 17 ppm / K.

  Thus, the thermal expansion coefficients of the substrate 4 and the base 6 are greatly different. Therefore, when the temperature change as described above acts, a difference occurs in the amount of thermal deformation between the substrate 4 and the base 6, and a shear load is applied to the under-substrate solder 5, which is a connecting member between the two. If the under-substrate solder 5 is thin, the shear strain acting on the under-substrate solder 5 may increase, and a crack may easily progress inside the under-substrate solder 5. That is, the fatigue life against repeated temperature changes may be reduced. When a crack progresses inside the under-substrate solder 5, a path for dissipating heat generated during the operation of the IGBT chip 1 and the diode chip 2 from the base 6 side is obstructed, so that the temperature of the semiconductor device 200 rises and eventually May lead to functional degradation.

  In the second embodiment, in addition to obtaining the same effect as in the first embodiment, the thickness of the under-substrate solder 5 is kept at a target value or more by providing the positioning wire 9 with the chevron 92. Be drunk. This has the advantage that the thermal fatigue life of the under-substrate solder 5 is improved.

[3. Third Embodiment]
The third embodiment is characterized in that the positioning wire 9b (FIG. 7A) is arranged at the corner of the under-substrate solder 5.
<Configuration>
7A and 7B show a semiconductor device according to the third embodiment, in which FIG. 7A is a perspective view, FIG. 7B is a top view, and FIG. 7C is a perspective view of a positioning wire. A semiconductor device 300 according to the third embodiment will be described with reference to FIG. Note that members similar to those of the semiconductor device 100 illustrated in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 7A is a perspective view of the semiconductor device 300, and shows an exploded view of one substrate 4 and the under-substrate solder 5 in order to make the position of the positioning wire 9b easier to see. Case 7 and sealant 8 are omitted. FIG. 7B is a top view of the semiconductor device 300. Only the positioning wire 9b, the under-substrate solder 5, and the base 6 are shown, and the other members are omitted. FIG. 7C shows the positioning wire 9 b of the semiconductor device 300.

  As shown in FIG. 7 (c), the positioning wire 9b includes two or more connecting portions 91 and one or more chevron like the positioning wire 9a (see FIG. 6 (b)) of the second embodiment. The connecting portion 91 is ultrasonically connected to the base 6. The chevron height 93 is equal to the sum of the target thickness of the under-substrate solder 5 and the thickness of the heat dissipation layer 43. In the positioning wire 9b, at least two or more connection portions 91 are arranged so as to be orthogonal to each other.

  The corners of the under-substrate solder 5 and the heat dissipation layer 43 are chamfered. The positioning wires 9b are arranged at at least two corners of the under-substrate solder 5 so that at least two connection portions 91 are substantially parallel to two orthogonal sides of the under-substrate solder 5, respectively.

  7A and 7B show an example in which positioning wires 9b are arranged at all four corners of one substrate 4, but the positioning wires 9b are at least at one corner. The substrate 4 and the under-substrate solder 5 can be positioned.

  FIG. 8 is a top view showing another arrangement example of the positioning wires in the semiconductor device. In the top view of the semiconductor device 300a, only the positioning wire 9a, the under-substrate solder 5, and the base 6 are shown, and other members are omitted. As the positioning wire of the semiconductor device 300a, the positioning wire 9a shown in FIG. 6B may be used. In this case, the positioning wire 9a is arranged in a direction substantially parallel to the chamfered portion at each of the four corner portions of the substrate 4 and the under-substrate solder 5.

  As described above, when the positioning wire 9b is arranged as shown in FIG. 7B, there are many contact portions between the positioning wire 9b, the under-substrate solder 5, and the heat radiation layer 43, so that the positional deviation is less likely to occur. On the other hand, when the positioning wire 9a is arranged as shown in FIG. 8, since there are few contact portions between the positioning wire 9a and the under-substrate solder 5 and the heat dissipation layer 43, the under-substrate solder 5 and the substrate 4 can be attached. It becomes easy.

<Effect>
In the third embodiment, like the second embodiment, the thickness of the under-substrate solder 5 after reflow can be maintained at a target value or more near the positioning wire 9b (or 9a) by the chevron 92, It is possible to reduce the shear load on the under-substrate solder 5 due to temperature change.

  In the semiconductor device 300, the positioning wire 9b (or 9a) is disposed at the corner of the under-substrate solder 5, so that the shear load near the corner of the under-substrate solder 5 is reduced. Normally, the thermal deformation difference between the substrate 4 and the base 6 is maximized on the diagonal line of the substrate 4, so that the thermal strain of the under-substrate solder 5 is maximized at the corners. Therefore, the corner portion tends to be a starting point of a crack generated inside the under-substrate solder 5.

  By using the third embodiment, the shear load at the corner that is most likely to start the crack is reduced, so that the thermal fatigue life of the under-substrate solder 5 is further improved.

[4. Example of change]
In addition to the above-described three embodiments, the above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. For example, the number of substrates 4 is not limited to the above embodiment. The same applies to the case where an arbitrary number of substrates 4 are arranged on the upper surface of the base 6. The shape of the base 6 is not limited to a flat plate. As long as heat can be efficiently dissipated, it can have any shape such as a shape having irregularities such as fins on the lower surface side.

  The shape of the circuit layer 41 is not limited to the above embodiment, and can be similarly applied to a shape constituting an arbitrary electric wiring. Similarly, the arrangement and the number of each of the IGBT chip 1, the diode chip 2, and the wiring wire 10 may be arbitrarily set.

  As described above, the semiconductor device 100 according to the first embodiment (see FIG. 1) includes the insulating layer 42, the circuit layer 41, and the heat dissipation layer 43 having a rectangular planar shape having a smaller plane dimension than the insulating layer 42. The substrate 4 includes the base 4, the base 6, and the under-substrate solder 5 that connects the heat dissipation layer 43 and the base 6, and the same surface as the surface of the base 6 on which the substrate 4 is fixed via the under-substrate solder 5. The positioning wire 9 is provided on the surface, and the positioning wire 9 is a region sandwiched between the insulating layer 42 and the base 6, and is located along each of at least two sides orthogonal to each other of the rectangular planar shape of the heat dissipation layer 43. At least one is arranged in each region. Thus, it is possible to provide a semiconductor device capable of positioning a substrate (electronic component) that is suitable for mass production at high speed, high accuracy, and easy.

1 IGBT chip (semiconductor chip)
2 Diode chip (semiconductor chip)
3 Under-chip solder 4 Substrate (electronic component)
41 Circuit layer 42 Insulating layer 42a Surface 43 Heat radiation layer 5 Substrate solder (solder)
6 Base 7 Case 8 Sealant 9, 9a, 9b Positioning wire 91 Connection portion 92 Mountain portion 93 Mountain portion height 10 Wiring wire 11 Carbon jig 12 Hole 100, 200, 300, 300a Semiconductor device

Claims (7)

A semiconductor device in which an electronic component including a semiconductor chip is disposed on a base via solder, and the solder is soldered by reflow heating,
A positioning wire for positioning the placement of the solder and the electronic component on the base;
The semiconductor device, wherein the solder and the electronic component are arranged in accordance with the positioning wire, and the electronic component is sealed with a sealant after the reflow heating. The electronic component has an insulating layer, a circuit layer having a smaller planar dimension than the insulating layer and formed on one surface of the insulating layer, and a rectangular planar shape having a smaller planar dimension than the insulating layer. And a heat dissipation layer formed on the other surface of the insulating layer.
The positioning wire is sandwiched between a portion of the other surface of the insulating layer other than the portion in contact with the heat dissipation layer and a portion of the surface of the base to which the substrate is fixed other than the portion in contact with the solder. 2. The semiconductor device according to claim 1, wherein at least one region is disposed in each of the two regions along each of at least two sides orthogonal to each other of the rectangular planar shape of the heat dissipation layer. The semiconductor device includes a wiring wire that is disposed on at least one surface of the circuit layer and the semiconductor chip and forms a part of electrical wiring on the circuit layer;
The semiconductor device according to claim 2, wherein the positioning wire and the wiring wire are made of an equivalent metal material and have an equivalent cross-sectional shape. The semiconductor device according to claim 3, wherein a diameter of the positioning wire is larger than a thickness of the solder. The positioning wire has at least two connecting portions connected to the base, and has a mountain-shaped portion bent in a mountain shape between the at least two connecting portions;
5. The semiconductor device according to claim 1, wherein a mountain-shaped portion of the positioning wire is disposed substantially perpendicular to the base. A method of manufacturing a semiconductor device in which an electronic component including a semiconductor chip is disposed on a base via solder, and the solder is soldered by reflow heating,
Arranging a positioning wire for positioning the solder and the electronic component on the base; and
Arranging the solder and the electronic component in accordance with the positioning wire;
Sealing the electronic component with a sealant after the reflow heating. A method for manufacturing a semiconductor device, comprising: The electronic component has an insulating layer, a circuit layer having a smaller planar dimension than the insulating layer and formed on one surface of the insulating layer, and a rectangular planar shape having a smaller planar dimension than the insulating layer. And a heat dissipation layer formed on the other surface of the insulating layer.
The step of arranging the positioning wire includes a portion other than a portion in contact with the heat dissipation layer of the other surface of the insulating layer, and a portion other than a portion in contact with the solder of the surface to which the substrate of the base is fixed. 7. The step of being arranged at least one in each of two regions along each of at least two sides orthogonal to each other of the rectangular planar shape of the heat dissipation layer. The manufacturing method of the semiconductor device as described in 2. above.

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