JP2012531751A - パッシベートされたシリコンナノワイヤーの製造方法およびこれにより得られるデバイス - Google Patents
パッシベートされたシリコンナノワイヤーの製造方法およびこれにより得られるデバイス Download PDFInfo
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Abstract
Description
本出願は、2009年6月26日出願の米国仮特許出願第61/220,980号の優先権を主張し、その全開示を本明細書に参照により組み入れる。本出願は、2010年2月24日出願の米国特許出願第12/712,097号「高アスペクト比プローブの製造方法ならびに高アスペクト比ナノピラーおよびマイクロピラーの変形方法」および2010年2月24日出願の米国特許出願第12/711,992号「高アスペクト比マイクロピラーおよびナノピラーの製造方法」にも関連し得、同様にそれらの全開示を本明細書に参照により組み入れる。
米国政府は、米国国防高等研究計画局により交付された補助金第HR0011−01−1−0054号および米国国立科学財団により交付された補助金第DMR0520565号に基づき、本発明において特定の権利を有する。
本開示はシリコンナノワイヤーに関する。またとくに、パッシベートされたシリコンナノワイヤーの製造方法およびこれにより得られるデバイスに関する。
Claims (32)
- 1つ以上のナノスケールピラーを備えるステップ;
該1つ以上のナノスケールピラーを絶縁体で覆うステップ;
第1導体層を該絶縁体上に配置するステップ;
該第1導体層の一部を誘電体で覆うステップ;
該第1導体層および該絶縁体の端部を除去し、これにより該1つ以上のナノスケールピラーの一部を電気的にアクセス可能にするステップ:ならびに
第2導体層を該誘電体上に配置し、該第2導体層を該1つ以上のナノスケールピラーの該電気的にアクセス可能な部分に接触させるステップ
を含む、電子構造体の製造方法。 - 前記1つ以上のナノスケールピラーが基板上にある、請求項1に記載の方法。
- 前記基板上の前記ナノスケールピラーの反対の面が導電背面接点で覆われる、請求項2に記載の方法。
- 前記絶縁体が酸化物絶縁体である、請求項1〜3のいずれか1項に記載の方法。
- 前記第1導体層が前記電子構造体のゲートの役割を果たす、請求項1〜4のいずれか1項に記載の方法。
- 前記電子構造体が1つ以上の金属−酸化物−半導体(MOS)構造、該1つ以上のMOS構造の該金属の役割を果たす前記第1導体層、該1つ以上のMOS構造の該酸化物の役割を果たす前記絶縁体、および該1つ以上のMOS構造の該半導体の役割を果たす前記ナノスケールピラーを備える、請求項1〜5のいずれか1項に記載の方法。
- 前記1つ以上のMOS構造が垂直に配向されたMOS構造であり、前記1つ以上のMOS構造の前記金属、酸化物、および半導体のそれぞれが垂直方向に延在する、請求項6に記載の方法。
- 前記電子構造体が1つ以上の電界効果トランジスタ(FET)を備える、請求項1〜7のいずれか1項の記載の方法。
- ゲート材料が前記1つ以上のナノスケールピラーのバンドギャップエネルギーと一致するプラズモン共鳴を示すように選択される、請求項5〜8のいずれか1項に記載の方法。
- 前記1つ以上のナノスケールピラーが発光ナノスケールピラーを含む、請求項1〜9のいずれか1項に記載の方法。
- 前記光が可視光である、請求項10に記載の方法。
- 前記ナノスケールピラーが光電子スイッチの役割を果たす、請求項1〜11のいずれか1項に記載の方法。
- 前記1つ以上のナノスケールピラーが前記1つ以上のFETのソースまたはドレインの役割を果たす、請求項8に記載の方法。
- 1つ以上のナノスケールピラーを備えるステップ;
該1つ以上のナノスケールピラーを絶縁体で覆うステップ;
該絶縁体を誘電体で覆うステップ;
該絶縁体の端部を除去し、これにより該1つ以上のナノスケールピラーの一部を電気的にアクセス可能にするステップ:ならびに
導体層を該誘電体上に配置し、該導体層を該1つ以上のナノスケールピラーの該電気的にアクセス可能な部分に接触させるステップ
を含む、電子構造体の製造方法。 - 1つ以上のナノスケールピラーを備えるステップ;
該1つ以上のナノスケールピラーを絶縁体で覆うステップ;
該ナノスケールピラーに接触する該絶縁体部分を除去するステップ;
残りの絶縁体部分および該ナノスケールピラーの露出部分を第1導体層で覆うステップ;
該導体層を誘電体で覆うステップ;
該第1導体層の端部を除去し、これにより該1つ以上のナノスケールピラーの一部を電気的にアクセス可能にするステップ:ならびに
第2導体層を該誘電体上に配置し、該第2導体層を該1つ以上のナノスケールピラーの該電気的にアクセス可能な部分に接触させるステップ
を含む、電子構造体の製造方法。 - 前記第1導体層が前記電子構造体のゲートの役割を果たす、請求項15に記載の方法。
- 前記電子構造体が1つ以上の金属−半導体(MES)構造、該1つ以上のMES構造の該金属の役割を果たす前記第1導体層および該1つ以上のMES構造の該半導体の役割を果たす前記ナノスケールピラーを備える、請求項15または16のいずれか1項に記載の方法。
- 前記1つ以上のMES構造が垂直に配向されたMES構造であり、前記1つ以上のMES構造の前記金属および半導体のそれぞれが垂直方向に延在する、請求項15〜17のいずれか1項に記載の方法。
- 前記電子構造体が1つ以上の電界効果トランジスタ(FET)を備える、請求項15〜18のいずれか1項の記載の方法。
- 平面に実質的に垂直な複数の絶縁体で覆われた半導体ナノスケールピラー構造;および
該絶縁体で覆われた半導体ナノスケールピラー構造上を覆った導体層
を備える、電子構造体。 - 前記複数のナノスケールピラー構造が基板上にある、請求項20に記載の構造体。
- 前記半導体ナノスケールピラー構造および前記基板がシリコンでできている、請求項21に記載の構造体。
- 導電背面接点が前記基板の背面上、前記ナノスケールピラー構造の反対側を覆った、請求項20または21のいずれか1項に記載の構造体。
- 前記導体層および前記絶縁体層がその端部を欠き、前記ナノスケールピラー構造の端部が電気的にアクセス可能であり;
前記構造体が:
前記平面上を覆った誘電体材料;ならびに
前記誘電体材料および前記ナノスケールピラー構造の前記アクセス可能な部分を覆ったさらなる導体層をさらに含むが、前記導体層と該さらなる導体層との間に直接接触が存在しない、請求項20〜23のいずれか1項に記載の構造体。 - 前記構造体が金属−酸化物−半導体(MOS)構造体である、請求項20〜24のいずれか1項に記載の構造体。
- 前記構造体が電界効果トランジスタ(FET)である、請求項20〜25のいずれか1項に記載の構造体。
- 前記導体層が前記FETのゲートである、請求項26に記載の構造体。
- 前記複数のナノスケールピラーが基板上にあり、前記基板および前記さらなる導体層がFETのソースおよびドレインまたはそれぞれドレインおよびソースである、請求項26または27のいずれか1項に記載の構造体。
- 絶縁体で覆われた半導体基板;
平面に実質的に垂直な、該基板上の複数のナノスケールピラー構造;および
該絶縁体および該ナノスケールピラー構造を覆う導体層
を備える、電子構造体であって、
該導体層がその端部を欠き、該ナノスケールピラー構造の端部が電気的にアクセス可能である、電子構造体。 - 平面上を覆った誘電体材料;および
該誘電体材料および前記ナノスケールピラー構造の前記アクセス可能な部分上を覆ったさらなる導体層をさらに備え、前記導体層と該さらなる導体層との間に直接接触が存在しない、請求項29に記載の構造体。 - 前記構造体が金属−半導体(MES)構造体である、請求項29または30のいずれか1項に記載の構造体。
- 前記構造体がMESFETである、請求項29〜31のいずれか1項に記載の構造体。
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PCT/US2010/039702 WO2010151604A2 (en) | 2009-06-26 | 2010-06-23 | Methods for fabricating passivated silicon nanowires and devices thus obtained |
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US8080468B2 (en) | 2011-12-20 |
EP2446467A2 (en) | 2012-05-02 |
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US8569741B2 (en) | 2013-10-29 |
US20110031470A1 (en) | 2011-02-10 |
US20120273762A1 (en) | 2012-11-01 |
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