CN111415996B - 核壳式结构GaN结型场效应管器件及其制备方法 - Google Patents

核壳式结构GaN结型场效应管器件及其制备方法 Download PDF

Info

Publication number
CN111415996B
CN111415996B CN202010405321.5A CN202010405321A CN111415996B CN 111415996 B CN111415996 B CN 111415996B CN 202010405321 A CN202010405321 A CN 202010405321A CN 111415996 B CN111415996 B CN 111415996B
Authority
CN
China
Prior art keywords
gan
layer
heavily doped
core
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010405321.5A
Other languages
English (en)
Other versions
CN111415996A (zh
Inventor
邵鹏飞
郭慧
陈敦军
谢自力
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing Nanda Optoelectronic Engineering Research Institute Co ltd
Original Assignee
Nanjing Nanda Optoelectronic Engineering Research Institute Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing Nanda Optoelectronic Engineering Research Institute Co ltd filed Critical Nanjing Nanda Optoelectronic Engineering Research Institute Co ltd
Priority to CN202010405321.5A priority Critical patent/CN111415996B/zh
Publication of CN111415996A publication Critical patent/CN111415996A/zh
Application granted granted Critical
Publication of CN111415996B publication Critical patent/CN111415996B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083Vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/0676Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66893Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H01L29/66909Vertical transistors, e.g. tecnetrons
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66893Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66924Unipolar field-effect transistors with a PN junction gate, i.e. JFET with an active layer made of a group 13/15 material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开了一种核壳式结构GaN结型场效应管器件及其制备方法。该方法首先利用MBE/MOCVD技术在蓝宝石衬底生长第二重掺n‑GaN层,作为后续的漏端欧姆接触层,再继续外延核壳式纳米柱状p‑n结,内层n‑GaN为沟道层,最后再外延一层重掺的n‑GaN作为源端欧姆接触层。器件结构生长完后再利用刻蚀和电极蒸发工艺形成源漏极和栅极,得到GaN‑JFET器件;核壳式p‑n结结构因沟道被环形包夹,其内部电场分布更均匀,栅对沟道具有更强的控制能力。

Description

核壳式结构GaN结型场效应管器件及其制备方法
技术领域
本发明涉及一种核壳式结构GaN结型场效应管器件,属于半导体器件领域。
背景技术
结型场效应晶体管是构成互补晶体管逻辑电路、电流感测放大器、模数转换器驱动器、光电二极管跨阻放大器等电路或装置中的核心器件,这些电路或装置在电力传输、交通运输、消费电子等领域有重要应用。GaN基场效应晶体管因具有工作频率高、导通电阻低、功率密度高、耐击穿电压高等优势,在可变电阻和功放领域具有重要应用前景。传统的结型场效应晶体管(JFET)需要利用再生长或离子注入工艺来实现p-n结,制备工艺较为复杂。
发明内容
本发明描述了设计和制造一种核壳式p-n结结构GaN结型场效应管(JFET)的方法。核壳结构内层的n型纳米柱沟道被外层p型GaN所包围,通过p型GaN层上的栅电极即可控制n型纳米柱沟道电流,实现具有核壳式结构的结型场效应晶体管。
本发明的目的在于设计和制造一种核壳式p-n结结构GaN结型场效应管(JFET)。
本发明的目的通过以下技术方案实现:
一种核壳式结构GaN结型场效应管器件,其结构包括:
一衬底层;
一生长于衬底层上的半绝缘GaN层;
一生长于半绝缘GaN层上的第一重掺n-GaN层,作为后续的漏端欧姆接触层;
一生长于重掺n-GaN层上的n-GaN纳米柱沟道层;
纳米柱状n-GaN以外的重掺n-GaN层上生长有图形化掩膜Si3N4层;
以及生长于掩膜Si3N4层上的p-GaN,所述p-GaN为环形,包裹住纳米柱状n-GaN,p-GaN与n-GaN纳米柱沟道层形成核壳式的p-n结;
还包括外延在环状p-GaN顶部的Si3N4层和外延在n-GaN纳米柱沟道层顶部的第二重掺n-GaN层,第二重掺n-GaN层作为源端欧姆接触层;
源电极和漏电极,分别设置在第二重掺n-GaN层和第一重掺n-GaN层的表面;
栅电极,环绕环状p-GaN设置且与环状p-GaN侧壁表面接触,形成环状结构的栅电极。
优选的,所述衬底层为蓝宝石衬底、Si衬底或SiC衬底。
优选的,所述半绝缘GaN层高度为2-5μm。
优选的,所述第一重掺n-GaN层厚度为300-400nm,图形化掩膜Si3N4层厚度80-100nm。
优选的,n-GaN纳米柱沟道层的直径为200-300nm,沟道长度0.8-1μm;p-GaN顶部低于n-GaN纳米柱沟道层顶部,p-GaN的厚度为100-200nm,长度600-700nm,掺杂浓度为1*1018-1*1019cm-3,控制沟道宽度,使其沟道在零偏下处于耗尽状态。
优选的,第二重掺n-GaN层厚度为300-400nm,在环状p-GaN上沉积的Si3N4层厚度80-100nm。
优选的,所述源电极和漏电极为Ti/Al/Ni/Au多层金属,厚度为30/150/50/150nm,栅电极为Ni/Au多层金属,厚度为50/100nm。
本发明还公开了上述的核壳式结构GaN结型场效应管器件的制备方法,其步骤包括:
(1)MOCVD法在衬底表面沉积半绝缘GaN层、第一重掺n-GaN层和Si3N4掩膜层,在掩膜Si3N4层上留有供n-GaN纳米柱生长的空间;
(2)MBE法在第一重掺n-GaN层上生长核壳式纳米柱状p-n结,内层n-GaN纳米柱为沟道层,外层为环状p-GaN,形成核壳式p-n结;
(3)采用掩模选区工艺,使用MBE系统在n-GaN纳米柱沟道层上再生长第二重掺n-GaN层;采用光刻、ICP刻蚀和PECVD在环状p-GaN和第二重掺n-GaN接触端刻蚀掉p-GaN,沉积Si3N4层;
(4)采用光刻、ICP刻蚀的方法在器件一端显露出第一重掺n-GaN层,用电子束蒸镀的方法分别在第二重掺n-GaN层和第一重掺n-GaN层的表面制作Ti/Al/Ni/Au源漏极金属电极,在p-GaN侧壁表面制作环形结构的Ni/Au栅金属电极。
优选的,步骤(1)中生长半绝缘GaN的方法:三甲基镓和NH3分别作为Ga源和N源,载气为H2或者N2,生长温度为1000-1100℃,生长时间3-5h;重掺n-GaN层的生长方法:温度950-1050℃,硅掺杂浓度为1*1019cm-3,生长时间25-30min;利用PECVD和光刻技术在重掺n-GaN层上生长图形化的Si3N4掩膜层;
步骤(2)中生长核壳式纳米柱状p-n结的方法:①n-GaN纳米柱生长:金属镓和N2分别作为Ga源和N源,生长温度为890-930℃,plasma功率450W,氮气流0.7sccm,硅掺杂浓度为1*1018cm-3,富N条件下生长,生长时间3-4h;②环状p-GaN外壳生长:金属镓和N2分别作为Ga源和N源,生长温度为890-930℃,plasma功率450W,氮气流0.7sccm,镁掺杂浓度为1*1018cm-3,富Ga条件下生长,生长时间3-4h;
步骤(3)中n-GaN沟道上外延生长重掺的n-GaN层生长方法:金属镓和N2分别作为Ga源和N源,生长温度为890-930℃,plasma功率450W,氮气流0.7sccm,硅掺杂浓度为1*1019cm-3,生长时间1-2h;
步骤(4)中用电子束蒸镀的方法分别在第二重掺n-GaN层和第一重掺n-GaN层的表面制作Ti/Al/Ni/Au源漏金属电极,在p-GaN侧壁表面制作环形结构的Ni/Au栅金属电极,并在快速热退火炉中850℃30s。
本发明的核壳式p-n结纳米柱状结构可以直接通过控制生长模式来制备得到,并且n型沟道被p型层环形包夹,其内部电场分布更均匀,栅对沟道电流具有更强的控制能力。本发明提供了一种具有高度栅控能力的核壳式结构GaN结型场效应管,而传统的结型场效应晶体管其栅对沟道的控制都是平面的,显然不如环状包夹式结构对沟道的控制能力。核壳式p-n结结构GaN结型场效应管不仅栅电极对沟道的控制能力强,而且沟道具有更好的电场均匀性,有利于提升器件的可靠性。
附图说明
图1是实施例1步骤(1)中得到的重掺n-GaN和图形化Si3N4外延片结构示意图。
图2是实施例1步骤(2)中得到的核壳式纳米柱状p-n结外延片结构示意图。
图3是实施例1步骤(3)中得到的n-GaN纳米柱状沟道层顶端外延重掺n-GaN外延片结构示意图。
图4是实施例1步骤(4)中得到的核壳式结构GaN结型场效应管结构示意图。
图5为图3中的核壳式结构GaN结型场效应管标注了各方向尺寸的示意图。
具体实施方法
以下是结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
实施例1
如图1-4所示,一种核壳式结构GaN-JFET器件的制备方法,其步骤包括:
(1)MOCVD法在蓝宝石衬底1表面沉积半绝缘GaN层2和第一重掺n-GaN层3,如图1所示;半绝缘GaN的生长方法:三甲基镓和NH3分别作为Ga源和N源,载气为H2或者N2,生长温度为1000-1100℃,生长时间3-5h。重掺n-GaN层的生长方法:温度950-1050℃,硅掺杂浓度为1*1019cm-3,生长时间25-30min。利用PECVD和光刻技术在重掺n-GaN层上生长图形化的Si3N4掩膜层4,通过光刻图形化后生长的Si3N4膜上形成规律的孔洞,孔洞里面通过MBE生长n-GaN纳米柱;
(2)MBE法在第一重掺n-GaN层上、Si3N4膜上的孔洞中外延核壳式纳米柱状p-n结,内层n-GaN为沟道层5,外层为p-GaN层6,如图2所示;核壳式纳米柱状p-n结生长方法:①n-GaN纳米柱生长:金属镓和N2分别作为Ga源和N源,生长温度为890-930℃,plasma功率450W,氮气流0.7sccm,硅掺杂浓度为1*1018cm-3,富N条件下生长,生长时间3-4h;②p-GaN纳米柱外壳生长:金属镓和N2分别作为Ga源和N源,生长温度为890-930℃,plasma功率450W,氮气流0.7sccm,镁掺杂浓度为1*1018cm-3,富Ga条件下生长,生长时间3-4h;
(3)采用掩模选区工艺,使用MBE系统在n-GaN沟道上外延生长第二重掺n-GaN层7;①n-GaN沟道上外延生长第二重掺n-GaN层的生长方法:金属镓和N2分别作为Ga源和N源,生长温度为890-930℃,plasma功率450W,氮气流0.7sccm,硅掺杂浓度为1*1019cm-3,富N条件下生长,生长时间1-2h;②采用光刻,ICP刻蚀和PECVD在环状p-GaN和第二重掺n-GaN接触端刻蚀掉p-GaN,沉积Si3N4层8,如图3所示;
(4)用电子束蒸镀的方法在n-GaN沟道层顶面的第二重掺n-GaN层7表面和n-GaN沟道层底面的第一重掺n-GaN层3表面制作Ti/Al/Ni/Au 30/150/50/150nm多层金属,并在快速热退火炉中850℃退火30s,形成源合金电极9和漏合金电极10,在p-GaN表面制作环形结构的Ni/Au 50/100nm栅金属电极11,制得如图4所示的核壳式结构GaN-JFET器件。
实施例2
本核壳式结构GaN-JFET器件,其结构包括:
一蓝宝石衬底层;
一生长于衬底层上的半绝缘GaN层,厚度为2μm;
一生长于半绝缘GaN层上的第一重掺n-GaN层,其厚度为300nm,生长于重掺n-GaN层上的图形化Si3N4层,其厚度为100nm,生长于第一重掺n-GaN层上的n-GaN纳米柱沟道层,其直径为200nm,高度为800nm,n-GaN硅掺杂浓度为1*1018cm-3,生长于n-GaN纳米柱沟道层外侧的p-GaN纳米圆环,p-GaN与n-GaN沟道层形成核壳式的p-n结,p-GaN厚度150nm,高度为600nm,p-GaN的掺杂浓度为1*1018cm-3
还包括n-GaN纳米柱沟道上的第二重掺n-GaN层,其厚度为300nm,纳米柱上端第二重掺n-GaN层和p-GaN层之间的Si3N4层,其厚度为100nm;
源电极和漏电极,分别设置在纳米柱顶层第二重掺n-GaN层和底层第一重掺n-GaN层的表面;所述源电极和漏电极为Ti/Al/Ni/Au多层金属,厚度为30/150/50/150nm;
环形结构的栅电极,覆盖p-GaN的柱状表面。栅电极为Ni/Au多层金属,厚度为50/100nm。
实施例3
本核壳式结构GaN结型场效应管器件,其结构包括:
一SiC衬底层;
一生长于衬底层上的半绝缘GaN层,厚度为5μm;
一生长于半绝缘GaN层上的第一重掺n-GaN层,其厚度为300nm,生长于重掺n-GaN层上的图形化Si3N4层,其厚度为100nm,生长于第一重掺n-GaN层上的n-GaN纳米柱沟道层,其直径为200nm,高度为800nm,n-GaN硅掺杂浓度为1*1018cm-3,生长于n-GaN纳米柱沟道层外侧的p-GaN纳米圆环,p-GaN与n-GaN沟道层形成核壳式的p-n结,p-GaN厚度150nm,高度为600nm,p-GaN的掺杂浓度为1*1018cm-3
还包括n-GaN纳米柱沟道上的第二重掺n-GaN层,其厚度为300nm,纳米柱上端第二重掺n-GaN层和p-GaN层之间的Si3N4层,其厚度为100nm;
源电极和漏电极,分别设置在纳米柱顶层第二重掺n-GaN层和底层第一重掺n-GaN层的表面;所述源电极和漏电极为Ti/Al/Ni/Au多层金属,厚度为30/150/50/150nm;
环形结构的栅电极,覆盖p-GaN的柱状表面。栅电极为Ni/Au多层金属,厚度为50/100nm。
实施例4
本核壳式结构GaN结型场效应管器件,其结构包括:
一Si衬底层;
一生长于衬底层上的半绝缘GaN层,厚度为4μm;
一生长于半绝缘GaN层上的第一重掺n-GaN层,其厚度为300nm,生长于重掺n-GaN层上的图形化Si3N4层,其厚度为100nm,生长于第一重掺n-GaN层上的n-GaN纳米柱沟道层,其直径为200nm,高度为800nm,n-GaN硅掺杂浓度为1*1018cm-3,生长于n-GaN纳米柱沟道层外侧的p-GaN纳米圆环,p-GaN与n-GaN沟道层形成核壳式的p-n结,p-GaN厚度150nm,高度为600nm,p-GaN的掺杂浓度为1*1018cm-3
还包括n-GaN纳米柱沟道上的第二重掺n-GaN层,其厚度为300nm,纳米柱上端第二重掺n-GaN层和p-GaN层之间的Si3N4层,其厚度为100nm;
源电极和漏电极,分别设置在纳米柱顶层第二重掺n-GaN层和底层第一重掺n-GaN层的表面;所述源电极和漏电极为Ti/Al/Ni/Au多层金属,厚度为30/150/50/150nm;
环形结构的栅电极,覆盖p-GaN的柱状表面。栅电极为Ni/Au多层金属,厚度为50/100nm。
上述实施例为本发明较佳的实施方式,但本发明的实施方式并不受上述实施例的限制,其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化,均应为等效的置换方式,都包含在本发明的保护范围之内。

Claims (8)

1.一种核壳式结构GaN结型场效应管器件,其结构包括:
一衬底层;
一生长于衬底层上的半绝缘GaN层;
一生长于半绝缘GaN层上的第一重掺n-GaN层;
一生长于重掺n-GaN层上的n-GaN纳米柱沟道层;
纳米柱状n-GaN以外的重掺n-GaN层上生长有图形化掩膜Si3N4层;
以及生长于掩膜Si3N4层上的p-GaN,所述p-GaN为环形,包裹住纳米柱状n-GaN,p-GaN与n-GaN纳米柱沟道层形成核壳式的p-n结;
还包括外延在环状p-GaN顶部的Si3N4层和外延在n-GaN纳米柱沟道层顶部的第二重掺n-GaN层;
源电极和漏电极,分别设置在第二重掺n-GaN层和第一重掺n-GaN层的表面;
栅电极,环绕环状p-GaN设置且与环状p-GaN侧壁表面接触,形成环状结构的栅电极;
n-GaN纳米柱沟道层的直径为200-300nm,沟道长度0.8-1μm;p-GaN顶部低于n-GaN纳米柱沟道层顶部,p-GaN的厚度为100-200nm,长度600-700nm,掺杂浓度为1*1018-1*1019cm-3,控制n-GaN纳米柱沟道层的直径,使其沟道在零偏下处于耗尽状态。
2.根据权利要求1所述的核壳式结构GaN结型场效应管器件,其特征在于:所述衬底层为蓝宝石衬底、Si衬底或SiC衬底。
3.根据权利要求1所述的核壳式结构GaN结型场效应管器件,其特征在于:所述半绝缘GaN层高度为2-5μm。
4.根据权利要求1所述的核壳式结构GaN结型场效应管器件,其特征在于:所述第一重掺n-GaN层厚度为300-400nm,图形化掩膜Si3N4层厚度80-100nm。
5.根据权利要求4所述的核壳式结构GaN结型场效应管器件,其特征在于:第二重掺n-GaN层厚度为300-400nm,在环状p-GaN上沉积的Si3N4层厚度80-100nm。
6.根据权利要求5所述的核壳式结构GaN结型场效应管器件,其特征在于:所述源电极和漏电极为Ti/Al/Ni/Au多层金属,厚度为30/150/50/150nm,栅电极为Ni/Au多层金属,厚度为50/100nm。
7.权利要求1-6中任一项所述的核壳式结构GaN结型场效应管器件的制备方法,其步骤包括:
(1)MOCVD法在衬底表面沉积半绝缘GaN层、第一重掺n-GaN层和Si3N4掩膜层,在掩膜Si3N4层上留有供n-GaN纳米柱生长的空间;
(2)MBE法在第一重掺n-GaN层上生长核壳式纳米柱状p-n结,内层n-GaN纳米柱为沟道层,外层为环状p-GaN,形成核壳式p-n结;
(3)采用掩模选区工艺,使用MBE系统在n-GaN纳米柱沟道层上再生长第二重掺n-GaN层;采用光刻、ICP刻蚀和PECVD在环状p-GaN和第二重掺n-GaN接触端刻蚀掉p-GaN,沉积Si3N4层;
(4)采用光刻、ICP刻蚀的方法在器件一端显露出第一重掺n-GaN层,用电子束蒸镀的方法分别在第二重掺n-GaN层和第一重掺n-GaN层的表面制作Ti/Al/Ni/Au源漏极金属电极,在p-GaN侧壁表面制作环形结构的Ni/Au栅金属电极。
8.根据权利要求7所述的核壳式结构GaN结型场效应管器件的制备方法,其特征在于:
步骤(1)中生长半绝缘GaN的方法:三甲基镓和NH3分别作为Ga源和N源,载气为H2或者N2,生长温度为1000-1100℃,生长时间3-5h;重掺n-GaN层的生长方法:温度950-1050℃,硅掺杂浓度为1*1019cm-3,生长时间25-30min;利用PECVD和光刻技术在重掺n-GaN层上生长图形化的Si3N4掩膜层;
步骤(2)中生长核壳式纳米柱状p-n结的方法:①n-GaN纳米柱生长:金属镓和N2分别作为Ga源和N源,生长温度为890-930℃,plasma功率450W,氮气流0.7sccm,硅掺杂浓度为1*1018cm-3,富N条件下生长,生长时间3-4h;②环状p-GaN外壳生长:金属镓和N2分别作为Ga源和N源,生长温度为890-930℃,plasma功率450W,氮气流0.7sccm,镁掺杂浓度为1*1018cm-3,富Ga条件下生长,生长时间3-4h;
步骤(3)中n-GaN沟道上外延生长重掺的n-GaN层生长方法:金属镓和N2分别作为Ga源和N源,生长温度为890-930℃,plasma功率450W,氮气流0.7sccm,硅掺杂浓度为1*1019cm-3,生长时间1-2h;
步骤(4)中用电子束蒸镀的方法分别在第二重掺n-GaN层和第一重掺n-GaN层的表面制作Ti/Al/Ni/Au源漏金属电极,在p-GaN侧壁表面制作环形结构的Ni/Au栅金属电极,并在快速热退火炉中850℃30s。
CN202010405321.5A 2020-05-14 2020-05-14 核壳式结构GaN结型场效应管器件及其制备方法 Active CN111415996B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010405321.5A CN111415996B (zh) 2020-05-14 2020-05-14 核壳式结构GaN结型场效应管器件及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010405321.5A CN111415996B (zh) 2020-05-14 2020-05-14 核壳式结构GaN结型场效应管器件及其制备方法

Publications (2)

Publication Number Publication Date
CN111415996A CN111415996A (zh) 2020-07-14
CN111415996B true CN111415996B (zh) 2024-01-23

Family

ID=71493764

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010405321.5A Active CN111415996B (zh) 2020-05-14 2020-05-14 核壳式结构GaN结型场效应管器件及其制备方法

Country Status (1)

Country Link
CN (1) CN111415996B (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104157686A (zh) * 2014-08-11 2014-11-19 北京大学 一种环栅场效应晶体管及其制备方法
CN106298934A (zh) * 2016-08-11 2017-01-04 北京大学 一种鞘层沟道结构的垂直纳米线器件及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120092091A (ko) * 2009-06-26 2012-08-20 캘리포니아 인스티튜트 오브 테크놀로지 페시베이팅된 실리콘 나노와이어들을 제조하기 위한 방법들 및 그에 따라 획득된 디바이스들
US10504889B1 (en) * 2018-07-17 2019-12-10 International Business Machines Corporation Integrating a junction field effect transistor into a vertical field effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104157686A (zh) * 2014-08-11 2014-11-19 北京大学 一种环栅场效应晶体管及其制备方法
CN106298934A (zh) * 2016-08-11 2017-01-04 北京大学 一种鞘层沟道结构的垂直纳米线器件及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
O. Benner 等.Junction field-effect transistor based on GaAs core-shell nanowires.2013 International Conference on Indium Phosphide and Related Materials (IPRM).2013,1-2. *

Also Published As

Publication number Publication date
CN111415996A (zh) 2020-07-14

Similar Documents

Publication Publication Date Title
JP5652827B2 (ja) トンネル電界効果トランジスタおよびその製造方法
US9634114B2 (en) Tunnel field-effect transistor, method for manufacturing same, and switch element
US10381489B2 (en) Tunnel field effect trasnsistor
JP5593050B2 (ja) 半導体基板、電子デバイス、および半導体基板の製造方法
JP5575447B2 (ja) 半導体基板、電子デバイス、および半導体基板の製造方法
WO2018010545A1 (zh) 一种异质结终端的碳化硅功率器件及其制备方法
US6765242B1 (en) Npn double heterostructure bipolar transistor with ingaasn base region
CN109037326A (zh) 一种具有p型埋层结构的增强型hemt器件及其制备方法
JP5597379B2 (ja) 半導体基板、電子デバイス、および半導体基板の製造方法
CN112635544A (zh) 具有偶极子层的增强型AlGaN-GaN垂直型超结HEMT及其制备方法
CN109950323A (zh) 极化超结的ⅲ族氮化物二极管器件及其制作方法
CN106449775A (zh) 一种GaN基混合PIN肖特基二极管及其制备方法
CN113113480A (zh) 具有p-GaN盖帽层的HEMT器件及制备方法
CN110634747A (zh) 利用MBE再生长p-GaN的单栅结构GaN-JFET器件的方法
CN111415996B (zh) 核壳式结构GaN结型场效应管器件及其制备方法
CN114883407B (zh) 基于Fin-FET栅结构HEMT及其制作方法
JP2007103727A (ja) 炭化珪素半導体装置及びその製造方法
JP4228250B2 (ja) 化合物半導体装置
CN113299734B (zh) 一种氮化镓晶体管器件及其制备方法
CN106449406B (zh) 一种垂直结构GaN基增强型场效应晶体管及其制造方法
CN212182338U (zh) 半导体结构
CN111211176B (zh) 一种氮化镓基异质结集成器件结构及制造方法
CN110634943B (zh) 利用MBE再生长的横向结构GaN基JFET器件及其制备方法
CN115274845B (zh) 一种凹陷式Fin-MESFET栅结构HEMT及制作方法
WO2022208868A1 (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant