JP2012501446A - 集積化エネルギー貯蔵デバイスを有する集積回路のための方法および装置 - Google Patents
集積化エネルギー貯蔵デバイスを有する集積回路のための方法および装置 Download PDFInfo
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Abstract
Description
[0035]一般に、集積電力コンデンサCpは、付加的な金属層および誘電体層を回路製造プロセスに追加することによって実現されうる。集積電力コンデンサは、ある用途ではその静電容量値に大きな精度を必要としないので、低コストのリソグラフィプロセスが、付加的な層のコストを低減するために使用されうる。いくつかの場合では、集積電力コンデンサの電極を回路上に設置する前に、集積回路の表面を平坦化するためにCMP(化学機械研磨)などのプロセスを使用することが望ましいであろう。CMPステップは、より薄い誘電体厚さの層を可能にし、そのことが結果としてデバイスの静電容量の増加またはより小さい面積における同じ静電容量を可能にする。
[0042]第1の金属層116が基板116の上に配置され、第1の絶縁層120と第2の絶縁層122との間に挟まれた任意選択の第2の層118が、第1の金属層116を覆って配置される。第1の金属層116および第2の金属層118により、例えば、デバイス層112のための相互接続および配線を行う。第1の絶縁層120および第2の絶縁層122は、例えば、層間誘電体および/またはパッシベーション層として設けることができる。
[0050]本明細書で使用されるように、ダイという用語は基板を指し、これは、絶縁体上の半導体もしくは半導体層でよく、例えばSOI基板であり、その関連する回路または電子デバイス素子を備える。ダイ上の回路は、例えばダイオードおよびトランジスタである半導体デバイスと、例えば抵抗器、インダクタまたはコンデンサである受動デバイスを含むことができる。
[0059]第1および第2のオンチップ電力コンデンサがそれぞれの基板の上に示されているが、他の実施形態では、1つまたは複数のオンチップコンデンサがそれぞれの基板の下にあることを理解されたい。一般に、オンチップコンデンサを形成する導電層は、それぞれの基板と概して平行である。コンデンサの形状は変わりうることを理解されたい。例えば、図6Cに示された別の実施形態では、1つの導電層、または複数の導電層を加工して、オンチップの互いにかみ合わせた電力コンデンサを形成することができる。一実施形態では、単一の導電層をパターニングして、オンチップの互いにかみ合わせたコンデンサを形成する。別の実施形態では、複数の導電層をパターニングして、1つまたは複数のオンチップの互いにかみ合わせたコンデンサを形成することができる。コンデンサを形成するために使用される誘電材料の特性は、コンデンサのインピーダンスを考慮したものであることを理解されたい。
[0067]例えば、図8Aおよび図8Bは、オンチップ電力コンデンサを備えた複数のダイを有するフリップチップ構成を示す。集積回路700は、リードフレーム704上に配置された第1のダイすなわち基板702を含む。第1のオンチップ電力コンデンサ706は、第1のダイ702の一部分の上に形成される。第1のダイ内に、任意選択のセンサ素子707を形成することができる。
[0070]上記のように、第1のダイ702および第2のダイ708は、同じ材料として、または異なる材料として提供することができる。例示的な材料は、Si、GaAs、InP、InSb、InGaAsP、SiGe、セラミック、およびガラスを含む。さらに、第1および第2のダイ内の感知素子は同じ種類のデバイス、または異なる種類のデバイスとすることができる。例示的なセンサ素子は、ホール効果、磁気抵抗、巨大磁気抵抗(GMR)、異方性磁気抵抗(AMR)、およびトンネル磁気抵抗(TMR)を含む。それぞれのオンチップコンデンサ706、714は、上記で論じたように、所望のインピーダンスを実現するようにサイズ変更することができる。
Claims (28)
- センサ出力を供給するためのセンサと、
前記センサ出力を受け、IC出力信号を供給するように基板上に少なくとも部分的に形成された集積回路モジュールと、
スイッチ素子を介して電圧供給信号を受けるための電圧入力、および前記IC出力信号を受けるための信号入力、および電圧出力信号を供給するための出力を有する出力回路と、
前記電圧供給信号の遮断の間に電力を供給するために前記出力回路の前記電圧入力に結合された集積電力貯蔵素子と、を備え、
前記電力貯蔵素子は、前記基板に概して平行な少なくとも1つの層を含む、
集積回路。 - 前記少なくとも1つの層は、
前記基板に概して平行な第1および第2の導電層と、
前記第1および前記第2の導電層ならびに誘電体層がコンデンサを形成するように、前記第1および前記第2の導電層の間に配置された誘電体層と
を含み、前記集積電力貯蔵素子は前記コンデンサを備える、請求項1に記載の集積回路。 - 前記コンデンサは互いにかみ合わせた構造を含む、請求項2に記載の集積回路。
- 前記集積電力貯蔵素子は、インダクタを形成するために少なくとも1つの層内に形成されたコイルを含む、請求項1に記載の集積回路。
- 供給電圧を受け、安定化された出力電圧を前記出力回路に供給するための電圧安定器をさらに含む、請求項1に記載の集積回路。
- 前記第1および前記第2の導電層内の渦電流を低減するために、磁界センサに隣接した前記第1および前記第2の導電層のうちの少なくとも一方の中にスロットが形成される、請求項2に記載の集積回路。
- 前記スロットは、前記第1の導電層内に第1のスロットを、かつ前記第2の導電層内に第2のスロットを含み、前記第1および前記第2のスロットが異なる形状を有する、請求項6に記載の集積回路。
- 前記スロットは、前記第1の導電層内に第1のスロットを、かつ前記第2の導電層内に第2のスロットを含み、前記第1および前記第2のスロットが実質的に類似した形状を有する、請求項6に記載の集積回路。
- 前記センサはホール素子を含む、請求項1に記載の集積回路。
- 前記センサは磁気抵抗素子を含む、請求項1に記載の集積回路。
- 前記コンデンサは、前記基板の少なくとも30パーセントの領域と重なり合う、請求項2に記載の集積回路。
- 前記コンデンサは、約1.0mm2の中に約50pFから約500pFまでの静電容量をもたらす、請求項2に記載の集積回路。
- 前記静電容量は、約150pFから約400pFまでの静電容量をもたらす、請求項2に記載の集積回路。
- センサ出力を供給するセンサを設けるステップと、
前記センサ出力を受け、IC出力信号を供給するように基板上に少なくとも部分的に形成された集積回路モジュールを設けるステップと
スイッチ素子を介して電圧供給信号を受けるための電圧入力、および前記IC出力信号を受けるための信号入力、および電圧出力信号を供給するための出力を有する出力回路を設けるステップと、
前記電圧供給信号の遮断の間に電力を供給するために前記出力回路の前記電圧入力に結合された集積電力貯蔵素子を設けるステップと、
を含み、前記電力貯蔵素子が、前記基板に概して平行な少なくとも1つの層を含む、方法。 - 前記少なくとも1つの層は、
前記基板に概して平行な第1および第2の導電層と、
前記第1および前記第2の導電層ならびに誘電体層がコンデンサを形成するように、前記第1および前記第2の導電層の間に配置された誘電体層と
を含み、前記集積電力貯蔵素子が前記コンデンサを備える、請求項14に記載の方法。 - 前記コンデンサは少なくとも部分的に互いにかみ合わされる、請求項15に記載の方法。
- 前記集積電力貯蔵素子は、インダクタを形成するために少なくとも1つの層内に形成されたコイルを含む、請求項14に記載の方法。
- 供給電圧を受け、安定化された出力電圧を前記出力回路に供給するための電圧安定器をさらに含む、請求項14に記載の方法。
- 前記第1および前記第2の導電層内の渦電流を低減するために、磁界センサに隣接した前記第1および前記第2の導電層のうちの少なくとも一方の中にスロットが形成される、請求項15に記載の方法。
- 前記スロットは、前記第1の導電層内に第1のスロットを、かつ前記第2の導電層内に第2のスロットを含み、前記第1および前記第2のスロットが異なる形状を有する、請求項19に記載の方法。
- 前記スロットは、前記第1の導電層内に第1のスロットを、かつ前記第2の導電層内に第2のスロットを含み、前記第1および前記第2のスロットが実質的に類似した形状を有する、請求項19に記載の方法。
- 前記センサはホール素子を含む、請求項14に記載の方法。
- 前記センサは磁気抵抗素子を含む、請求項14に記載の方法。
- 前記コンデンサは、前記基板の少なくとも30パーセントの領域と重なり合う、請求項15に記載の方法。
- 前記コンデンサは、約1.0mm2の中に約150pFから約400pFまでの静電容量をもたらす、請求項15に記載の方法。
- センサ出力を供給するセンサと、
前記センサ出力を受け、IC出力信号を供給するように基板上に少なくとも部分的に形成された集積回路モジュールと、
スイッチ素子を介して電圧供給信号を受けるための電圧入力、および前記IC出力信号を受けるための信号入力、および電圧出力信号を供給するための出力を有する出力回路と、
前記電圧供給信号の遮断の間に電力を供給するための前記出力回路の前記電圧入力に結合された集積電力貯蔵素子と、を備え、
前記電力貯蔵素子は、前記基板に概して平行な少なくとも1つの層を含む、
車両。 - 前記少なくとも1つの層は、
前記基板に概して平行な第1および第2の導電層と、
前記第1および前記第2の導電層ならびに誘電体層がコンデンサを形成するように、前記第1および前記第2の導電層の間に配置された誘電体層と、を含み、
前記集積電力貯蔵素子が前記コンデンサを備える、請求項26に記載の車両。 - 前記集積電力貯蔵素子は、インダクタを形成するために少なくとも1つの層内に形成されたコイルを含む、請求項26に記載の車両。
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PCT/US2009/054254 WO2010027658A2 (en) | 2008-08-26 | 2009-08-19 | Methods and apparatus for integrated circuit having integrated energy storage device |
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Also Published As
Publication number | Publication date |
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WO2010027658A3 (en) | 2010-08-05 |
US20100052424A1 (en) | 2010-03-04 |
WO2010027658A2 (en) | 2010-03-11 |
CN102132405A (zh) | 2011-07-20 |
DE112009002077T5 (de) | 2011-07-07 |
JP5497763B2 (ja) | 2014-05-21 |
CN102132405B (zh) | 2014-04-23 |
DE112009002077B4 (de) | 2022-01-05 |
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