JP2012244173A - ポリシリコン活性層を含む薄膜トランジスタ及びその製造方法とアレイ基板 - Google Patents
ポリシリコン活性層を含む薄膜トランジスタ及びその製造方法とアレイ基板 Download PDFInfo
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
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- 125000003118 aryl group Chemical group 0.000 description 1
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- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
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- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
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- 239000011733 molybdenum Substances 0.000 description 1
- -1 nickel Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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Abstract
【解決手段】前記製造方法は、基板にアモルファスシリコン層を堆積するとともに、前記アモルファスシリコン層に対してパターニングを行うことで、ソース領域とドレイン領域とチャンネル領域とを含む活性層を形成するステップと、前記ソース領域及び前記ドレイン領域に誘起金属を堆積するステップと、前記誘起金属が堆積された前記活性層に対して第1の熱処理を行い、前記活性層が前記誘起金属の作用によって結晶化されるステップと、前記ソース領域及び前記ドレイン領域に、前記誘起金属を集めるための第1の不純物をドープするステップと、ドープされた前記活性層に対して第2の熱処理を行い、前記第1の不純物が前記チャンネル領域に残された誘起金属に対して吸収するステップと、を備える。
【選択図】図3E
Description
ステップ301:基板にバッファ層を堆積する。
図3Aを参照すると、予め洗浄したガラス基板などの透明基板401に、PECVD(プラズマ化学気相成長法)や、LPCVD(低圧化学気相成長法)や、APCVD(常圧化学気相成長法)や、ECR−CVD(電子サイクロトロン化学気相堆積法)又はスパッタリングなどの方法によってバッファ層402を形成して、ガラスに含有されている不純物が活性層へ拡散侵入することを防止し、これによってTFT素子の閾値電圧及びリーク電流などの特性が影響されることを防止する。
Claims (15)
- 基板にアモルファスシリコン層を堆積するとともに、前記アモルファスシリコン層に対してパターニングを行うことで、ソース領域とドレイン領域とチャンネル領域とを含む活性層を形成するステップと、
前記ソース領域及び前記ドレイン領域に誘起金属を堆積するステップと、
前記誘起金属が堆積された前記活性層に対して第1の熱処理を行い、前記活性層が前記誘起金属の作用によって結晶化されるステップと、
前記ソース領域及び前記ドレイン領域に、前記誘起金属を集めるための第1の不純物をドープするステップと、
ドープされた前記活性層に対して第2の熱処理を行い、前記第1の不純物が前記チャンネル領域に残された誘起金属に対して吸収するステップと、
を備えることを特徴とするポリシリコン活性層を含む薄膜トランジスタの製造方法。 - 前記第1の熱処理後であって、前記第2の熱処理前において、前記ソース領域及び前記ドレイン領域に、前記ソース領域及び前記ドレイン領域の導電タイプを確定するための第2の不純物をドープするステップをさらに備え、前記第2の熱処理は前記第2の不純物を活性化することを特徴とする請求項1に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- 前記第1の不純物は、リン、窒素又は窒素・酸素混合物であることを特徴とする請求項2に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- 前記第2の熱処理の温度は300−600℃であり、処理時間は1−3時間であることを特徴とする請求項3に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- 前記誘起金属はニッケル、銅、金、銀、アルミニウム、コバルト又はクロムであることを特徴とする請求項4に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- 堆積された前記誘起金属の厚さは10−200Åであることを特徴とする請求項1から5のいずれか1項に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- 前記第1の熱処理の温度は400−600℃であり、処理時間は0.1−50時間であることを特徴とする請求項1から6のいずれか1項に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- ドープされた前記第2の不純物のドーズ量は、ドープされた前記第1の不純物のドーズ量の2−3倍であることを特徴とする請求項2に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- 前記第1の熱処理を行う際、前記誘起金属に覆われた前記ソース領域及び前記ドレイン領域において金属誘起結晶化が発生し、前記チャンネル領域において金属誘起横方向結晶化が発生することを特徴とする請求項1から8のいずれか1項に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- 前記アモルファスシリコン層を堆積する前に前記基板にバッファ層を形成し、前記バッファ層に前記アモルファスシリコン層を堆積することを特徴とする請求項1から9のいずれか1項ポリシリコン活性層を含む薄膜トランジスタの製造方法。
- 前記第1の不純物及び前記第2の不純物をドープする前に、前記活性層にゲート絶縁層及びゲート電極のパターンを形成し、
前記第1の不純物及び前記第2の不純物を、前記ゲート絶縁層及びゲート電極のパターンをマスクとして、前記ソース領域及び前記ドレイン領域にドープすることを特徴とする請求項2に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。 - 前記アモルファスシリコン層を堆積する前に、前記基板にゲート電極及びゲート絶縁層を形成し、前記アモルファスシリコン層を、前記ゲート電極及び前記ゲート絶縁層が形成された基板に堆積することを特徴とする請求項1に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- イオン注入を採用して、前記ソース領域及び前記ドレイン領域に前記第1の不純物及び第2の不純物をドープし、前記イオン注入エネルギーが40−100KeVであることを特徴とする請求項2に記載のポリシリコン活性層を含む薄膜トランジスタの製造方法。
- 請求項1から13のいずれか1項に記載の製造方法で制作されることを特徴とするポリシリコン活性層を含む薄膜トランジスタ。
- 請求項14に記載の薄膜トランジスタを備えることを特徴とするアレイ基板。
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CN201110124783.0A CN102709184B (zh) | 2011-05-13 | 2011-05-13 | 含有多晶硅有源层的薄膜晶体管、其制造方法及阵列基板 |
CN201110124783.0 | 2011-05-13 |
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CN102709184B (zh) * | 2011-05-13 | 2016-08-17 | 京东方科技集团股份有限公司 | 含有多晶硅有源层的薄膜晶体管、其制造方法及阵列基板 |
CN102945789B (zh) | 2012-11-22 | 2015-07-22 | 京东方科技集团股份有限公司 | 低温多晶硅薄膜制备方法、薄膜晶体管及其制备方法 |
CN102956649A (zh) * | 2012-11-26 | 2013-03-06 | 京东方科技集团股份有限公司 | 阵列基板、阵列基板制作方法及显示装置 |
CN104576753B (zh) * | 2014-12-29 | 2018-06-26 | 昆山国显光电有限公司 | 一种低温多晶硅薄膜晶体管及其制造方法 |
JP7085352B2 (ja) * | 2018-01-15 | 2022-06-16 | 株式会社ジャパンディスプレイ | 表示装置 |
CN109449210B (zh) * | 2018-09-19 | 2022-06-10 | 云谷(固安)科技有限公司 | 阵列基板及显示器件 |
CN109473485B (zh) * | 2018-12-29 | 2023-07-04 | 重庆伟特森电子科技有限公司 | 碳化硅二极管及其制备方法 |
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US20120289007A1 (en) | 2012-11-15 |
CN102709184A (zh) | 2012-10-03 |
US9059214B2 (en) | 2015-06-16 |
KR101498136B1 (ko) | 2015-03-03 |
EP2523216A1 (en) | 2012-11-14 |
KR20120127318A (ko) | 2012-11-21 |
EP2523216B1 (en) | 2019-12-18 |
CN102709184B (zh) | 2016-08-17 |
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