JP2012191436A - 受信信号処理装置 - Google Patents
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- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
- H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
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- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
- H03G3/3068—Circuits generating control signals for both R.F. and I.F. stages
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H03F2200/336—A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
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- H03F2200/507—A switch being used for switching on or off a supply or supplying circuit in an IC-block amplifier circuit
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- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45212—Indexing scheme relating to differential amplifiers the differential amplifier being designed to have a reduced offset
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- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45352—Indexing scheme relating to differential amplifiers the AAC comprising a combination of a plurality of transistors, e.g. Darlington coupled transistors
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- H03F2203/45702—Indexing scheme relating to differential amplifiers the LC comprising two resistors
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- H03F2203/7215—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the input of the amplifier
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- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
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- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
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- H03F2203/7231—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into cascade or not, by choosing between amplifiers by one or more switch(es)
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- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7236—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
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Abstract
【解決手段】受信信号処理装置は、高周波の受信信号に局部発振信号を合成して周波数変換するミキサ部と、多段に構成された複数の利得可変増幅器を含む増幅部と、増幅部により増幅されたアナログ信号をデジタル信号に変換する変換部と、各利得可変増幅器の後段に設けられたスイッチと、利得可変増幅器の出力が後段の利得可変増幅器を迂回して変換部に入力される経路の開閉を設定する迂回スイッチ部と、各利得可変増幅器の出力が後段の利得可変増幅器を介さずに変換部に入力するために、スイッチ及び迂回スイッチ部を制御するスイッチ制御部と、受信信号が補正対象の利得可変増幅器に入力されず、補正対象の利得可変増幅器の出力が後段の利得可変増幅器を介さずに変換部に入力される場合に、補正対象の利得可変増幅器に設定される利得に応じてDCオフセットの補正値を設定するDCオフセット制御部とを含む。
【選択図】図1
Description
前記受信信号に所定周波数の局部発振信号を合成して周波数変換するミキサ部と、
多段に構成された複数の利得可変増幅器を含む増幅部と、
前記増幅部により増幅されたアナログ信号をデジタル信号に変換する変換部と、
前記増幅部が含む各利得可変増幅器の後段に設けられたアイソレーションスイッチと、
前記利得可変増幅器の出力が後段の利得可変増幅器を迂回して前記変換部に入力される経路の開閉を設定する迂回スイッチ部と、
各利得可変増幅器の出力が後段の利得可変増幅器を介さずに前記変換部に入力するために、前記アイソレーションスイッチ及び前記迂回スイッチ部を制御するスイッチ制御部と、
前記受信信号が補正対象の利得可変増幅器に入力されず、かつ、前記補正対象の利得可変増幅器の出力が後段の利得可変増幅器を介さずに前記変換部に入力される場合に、前記補正対象の利得可変増幅器に設定される利得に応じて、DCオフセットの補正値を設定するDCオフセット制御部と、を備えた受信信号処理装置を提供する。
図1は、第1の実施形態の受信信号処理装置の一部構成を示すブロック図である。本実施形態の受信信号処理装置は、携帯電話を含む通信機器の受信回路に適用可能である。図1に示す受信信号処理装置は、ダイレクトコンバージョン方式を採用したQPSKを含む直交変調の受信回路である。ただし、図1のLNA103以降の配線は、同相成分及び直交成分を含む。
図5は、第2の実施形態の受信信号処理装置の一部構成を示すブロック図である。第2の実施形態の受信信号処理装置が第1の実施形態の受信信号処理装置と異なる点はVGAの数である。第1の実施形態では受信信号処理装置がVGAを2つ備えるが、第2の実施形態の受信信号処理装置は3つのVGAを含む構成である。なお、アイソレーションスイッチの数及び迂回スイッチ部が有するスイッチの数も、VGAの数と同様に3つである。この点以外は第1の実施形態と同様であり、図5において、図1と同一又は同等の構成要素には同一符号又は相当符号を付して説明を簡略化又は省略する。
103 LNA
105 ミキサ回路
107f,107f1,107f2,107r VGA
109 AD変換回路(ADC)
SWf,SWf1,SWf2,SWr アイソレーションスイッチ
111,211 迂回スイッチ部
113 スイッチ制御部
115 DCオフセット制御部
117 メモリ
201 電源制御部
203 電力検出部
205 変換部
SWb1,SWb2,SWb,SWba,SWbb スイッチ
Claims (4)
- ダイレクトコンバージョン方式を用いて高周波の受信信号をベースバンド帯にダウンコンバートする受信信号処理装置であって、
前記受信信号に所定周波数の局部発振信号を合成して周波数変換するミキサ部と、
多段に構成された複数の利得可変増幅器を含む増幅部と、
前記増幅部により増幅されたアナログ信号をデジタル信号に変換する変換部と、
前記増幅部が含む各利得可変増幅器の後段に設けられたアイソレーションスイッチと、
前記利得可変増幅器の出力が後段の利得可変増幅器を迂回して前記変換部に入力される経路の開閉を設定する迂回スイッチ部と、
各利得可変増幅器の出力が後段の利得可変増幅器を介さずに前記変換部に入力するために、前記アイソレーションスイッチ及び前記迂回スイッチ部を制御するスイッチ制御部と、
前記受信信号が補正対象の利得可変増幅器に入力されず、かつ、前記補正対象の利得可変増幅器の出力が後段の利得可変増幅器を介さずに前記変換部に入力される場合に、前記補正対象の利得可変増幅器に設定される利得に応じて、DCオフセットの補正値を設定するDCオフセット制御部と、
を備えたことを特徴とする受信信号処理装置。 - 請求項1に記載の受信信号処理装置であって、
前記DCオフセット制御部は、
前記補正対象の利得可変増幅器に対して利得を下限から上限まで設定し、各利得における出力の直流成分が所定値以下となる前記DCオフセットの補正値を設定することを特徴とする受信信号処理装置。 - 請求項1又は2に記載の受信信号処理装置であって、
前記DCオフセット制御部は、
前記増幅部の初段の利得可変増幅器から最後段の利得可変増幅器に対して、初段から順に前記DCオフセットの補正値を設定する受信信号処理装置。 - 請求項1〜3のいずれか一項に記載の受信信号処理装置であって、
前記スイッチ制御部が、前記アイソレーションスイッチ及び前記迂回スイッチ部を制御し、前記受信信号が前記補正対象の利得可変増幅器に入力される場合に、
前記DCオフセット制御部は、各利得可変増幅器の利得を制御し、制御された利得に応じた前記DCオフセットの補正値に基づいて、前記受信信号のDCオフセットを補正する受信信号処理装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011053202A JP5660721B2 (ja) | 2011-03-10 | 2011-03-10 | 受信信号処理装置 |
US13/816,076 US8891697B2 (en) | 2011-03-10 | 2012-02-23 | Reception signal processing device |
PCT/JP2012/001256 WO2012120811A1 (ja) | 2011-03-10 | 2012-02-23 | 受信信号処理装置 |
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Application Number | Priority Date | Filing Date | Title |
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JP2011053202A JP5660721B2 (ja) | 2011-03-10 | 2011-03-10 | 受信信号処理装置 |
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Publication Number | Publication Date |
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JP2012191436A true JP2012191436A (ja) | 2012-10-04 |
JP2012191436A5 JP2012191436A5 (ja) | 2014-01-30 |
JP5660721B2 JP5660721B2 (ja) | 2015-01-28 |
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JP2011053202A Expired - Fee Related JP5660721B2 (ja) | 2011-03-10 | 2011-03-10 | 受信信号処理装置 |
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US (1) | US8891697B2 (ja) |
JP (1) | JP5660721B2 (ja) |
WO (1) | WO2012120811A1 (ja) |
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WO2016170622A1 (ja) * | 2015-04-22 | 2016-10-27 | オリンパス株式会社 | 半導体装置 |
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KR102219849B1 (ko) * | 2014-01-03 | 2021-02-24 | 삼성전자주식회사 | 직접 변환 수신기의 직류 전류 오프셋 교정 방법 및 장치 |
WO2018044523A1 (en) * | 2016-08-31 | 2018-03-08 | Apple Inc. | Analog front end with variable gain control for touch applications |
US10382054B2 (en) * | 2017-11-10 | 2019-08-13 | Synaptics Incorporated | Analog front end (AFE) for quantization noise-limited sensor apparatus |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPS5274734A (en) | 1975-12-17 | 1977-06-23 | Aisin Seiki Co Ltd | Fan shroud for radiator of automobile water cool engine |
JPS55130411A (en) | 1979-03-26 | 1980-10-09 | Iseki & Co Ltd | Grain distributor for grain dryer |
JP4319502B2 (ja) | 2003-10-01 | 2009-08-26 | 株式会社ルネサステクノロジ | 通信用半導体集積回路および無線通信システム |
US8010077B2 (en) * | 2008-04-21 | 2011-08-30 | Freescale Semiconductor, Inc. | DC offset calibration in a direct conversion receiver |
JP5334318B2 (ja) * | 2009-11-30 | 2013-11-06 | ルネサスエレクトロニクス株式会社 | 通信用半導体集積回路およびその動作方法 |
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2011
- 2011-03-10 JP JP2011053202A patent/JP5660721B2/ja not_active Expired - Fee Related
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2012
- 2012-02-23 US US13/816,076 patent/US8891697B2/en not_active Expired - Fee Related
- 2012-02-23 WO PCT/JP2012/001256 patent/WO2012120811A1/ja active Application Filing
Patent Citations (6)
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JPS5274734U (ja) * | 1975-12-01 | 1977-06-03 | ||
JPS55130411U (ja) * | 1979-03-12 | 1980-09-16 | ||
JP2003152480A (ja) * | 2001-11-16 | 2003-05-23 | Hitachi Ltd | 通信用半導体集積回路および無線通信システム |
JP2003347873A (ja) * | 2002-05-24 | 2003-12-05 | Hitachi Ltd | 多段アンプのゲイン制御方法及び装置 |
JP2006517765A (ja) * | 2003-02-11 | 2006-07-27 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 臨界的な連続時間用途における自動ゼロ化 |
JP2009239794A (ja) * | 2008-03-28 | 2009-10-15 | Nippon Telegr & Teleph Corp <Ntt> | 多段可変利得増幅器 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016170622A1 (ja) * | 2015-04-22 | 2016-10-27 | オリンパス株式会社 | 半導体装置 |
JPWO2016170622A1 (ja) * | 2015-04-22 | 2018-02-15 | オリンパス株式会社 | 半導体装置 |
US9979364B2 (en) | 2015-04-22 | 2018-05-22 | Olympus Corporation | Semiconductor device with improved variable gain amplification |
Also Published As
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JP5660721B2 (ja) | 2015-01-28 |
WO2012120811A1 (ja) | 2012-09-13 |
US20130136213A1 (en) | 2013-05-30 |
US8891697B2 (en) | 2014-11-18 |
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