JP2012149210A - ダイエクスポーズドフリップチップパッケージ(defcp)のモールドアンダーフィル工程用粘着マスキングテープ - Google Patents
ダイエクスポーズドフリップチップパッケージ(defcp)のモールドアンダーフィル工程用粘着マスキングテープ Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
- H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Adhesive Tapes (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Adhesives Or Adhesive Processes (AREA)
Abstract
信頼性が向上し、汚染を防止できるダイエクスポーズドフリップチップパッケージのモールドアンダーフィル工程用粘着マスキングテープを提供すること。
【解決手段】
本発明は、耐熱基材と、該耐熱基材上に塗布された粘着層とからなるものの、前記耐熱基材は、PENフィルムで、前記耐熱基材の厚さは、25〜50umであることを特徴とするダイエクスポーズドフリップチップパッケージのモールドアンダーフィル工程用粘着マスキングテープを提供する。
【選択図】図1
Description
アクリル樹脂:SAMWON社製、AT5100
熱硬化剤:イソシアネート系(ダウコーティング社製、CE138)
エネルギー線硬化型ウレタン樹脂:脂肪族ポリウレタンアクリレート(日本合成社製、UV7600B80)
エネルギー線硬化型シリコン樹脂:シリコンヘキサアクリレート(CYTEC社製、EB1360)
光開始剤:アルアクリルポスファイン系(CYTEC社製、DAROCUR TPO)
アクリル樹脂(重量平均分子量350,000)100重量部をエチルアセテート600重量部に溶解し、熱硬化剤0.5重量部、エネルギー線硬化型ウレタン樹脂25重量部、エネルギー線硬化型シリコン樹脂10重量部、光開始剤1重量部を混合して1時間撹拌して粘着剤組成物を得た。撹拌が終わった粘着剤組成物を38um厚のポリエチレンナフタレート(PEN)フィルムに塗布し、150℃の乾燥器で約3分間乾燥した。塗布厚は、約6umと確認された。乾燥器を通過した乾燥されたテープは、追加的な架橋構造を形成するためにエネルギー線硬化工程を経るが、本実施例では、紫外線を照射した。UVランプの強度、照射面との距離、照射時間などを適切に調節して、紫外線の光量が約500mJ/cm2になるようにした。粘着剤層内の完全な硬化のために、長波長の紫外線A領域(315〜400nm)のエネルギー線を放出する無電極UVランプを使用し、酸素によるエネルギー線硬化効率の減少を防止するために、窒素雰囲気で紫外線を照射した。
アクリル樹脂100重量部をエチルアセテート600重量部に溶解し、熱硬化剤0.5重量部、光開始剤1重量部を混合して1時間撹拌して粘着剤組成物を得た。撹拌が終わった粘着剤組成物を38um厚のPENフィルムに塗布し、150℃の乾燥器で約3分間乾燥した。塗布厚は、約6umと確認された。
アクリル樹脂100重量部をエチルアセテート600重量部に溶解し熱硬化剤0.5重量部、エネルギー線硬化型ウレタン樹脂25重量部、エネルギー線硬化型シリコン樹脂50重量部、光開始剤1重量部を混合して1時間撹拌して粘着剤組成物を得た。撹拌が終わった粘着剤組成物を38um厚のポリエチレンナフタレート(PEN)フィルムに塗布し、150℃乾燥器で約3分間乾燥した。塗布厚は、約6umと確認された。乾燥されたテープは、実施例1のように紫外線を照射して追加的なエネルギー線硬化を実施した。
実施例1と同じ組成の粘着剤造液を38um厚のPETフィルムに同一条件で製造して粘着層を形成した。
実施例1と同じ組成の粘着剤造液を35um厚のPI(ポリイミド)フィルムに同一条件で製造して粘着層を形成した。
粘着層無しで50um厚のETFEフィルムを使用した。
A2 モールド金型(下)
A3 耐熱基材(PENフィルム)
A4 粘着層
A5 チップ
A6 ソルダーボール(solder ball)
A7 基板(printed circuit board、PCB)
A8 モールド樹脂
Claims (6)
- 耐熱基材と、該耐熱基材上に塗布された粘着層とからなるものの、
前記耐熱基材は、PENフィルムで、前記耐熱基材の厚さは、25〜50umであることを特徴とするダイエクスポーズドフリップチップパッケージのモールドアンダーフィル工程用粘着マスキングテープ。 - 前記耐熱基材の少なくとも一面に帯電防止コーティングされていることを特徴とする請求項1に記載のダイエクスポーズドフリップチップパッケージのモールドアンダーフィル工程用粘着マスキングテープ。
- 前記粘着層は、アクリル樹脂、熱硬化剤、エネルギー線硬化型オリゴマー樹脂及び光開始剤を含み、熱硬化及びエネルギー線により硬化されたことを特徴とする請求項1に記載のダイエクスポーズドフリップチップパッケージのモールドアンダーフィル工程用粘着マスキングテープ。
- 前記アクリル樹脂の重量平均分子量は、100,000〜1,500,000であることを特徴とする請求項3に記載のダイエクスポーズドフリップチップパッケージのモールドアンダーフィル工程用粘着マスキングテープ。
- 前記エネルギー線硬化型オリゴマー樹脂は、ウレタン樹脂とシリコン樹脂との混合物であることを特徴とする請求項3に記載のダイエクスポーズドフリップチップパッケージのモールドアンダーフィル工程用粘着マスキングテープ。
- 前記アクリル樹脂100重量部を基準に前記熱硬化剤0.1〜2重量部、前記エネルギー線硬化型ウレタン樹脂5〜30重量部、前記エネルギー線硬化型シリコン樹脂5〜15重量部を含み、前記エネルギー線硬化型オリゴマー樹脂100重量部を基準に前記光開始剤を1〜10重量部含むことを特徴とする請求項5に記載のダイエクスポーズドフリップチップパッケージのモールドアンダーフィル工程用粘着マスキングテープ。
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JP2014063971A (ja) * | 2012-09-21 | 2014-04-10 | Toray Advanced Materials Korea Inc | モールドアンダーフィル工程のマスキングテープ用粘着剤組成物及びそれを利用したマスキングテープ |
JP2014212239A (ja) * | 2013-04-19 | 2014-11-13 | 株式会社巴川製紙所 | モールド成形用離型シート |
WO2015119042A1 (ja) * | 2014-02-05 | 2015-08-13 | 大日本印刷株式会社 | 粘着剤組成物およびそれを用いた粘着フィルム |
WO2019130539A1 (ja) * | 2017-12-28 | 2019-07-04 | リンテック株式会社 | 粘着シート及び半導体装置の製造方法 |
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KR20100073613A (ko) * | 2008-12-23 | 2010-07-01 | 도레이첨단소재 주식회사 | 반도체 장치용 내열 점착테잎 |
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WO2019130539A1 (ja) * | 2017-12-28 | 2019-07-04 | リンテック株式会社 | 粘着シート及び半導体装置の製造方法 |
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KR101194544B1 (ko) | 2012-10-25 |
TWI504717B (zh) | 2015-10-21 |
KR20120084501A (ko) | 2012-07-30 |
MY159063A (en) | 2016-12-15 |
TW201245384A (en) | 2012-11-16 |
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