JP2012054564A - 接続方法及び接続構造体並びに接続構造体の製造方法 - Google Patents
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- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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Abstract
【解決手段】ガラスパネル11とFPC13とを異方性接続する際、一方の面にFPC13の配線電極13bの配線パターンに応じたパターンの凸部14bが形成されている緩衝材14をFPC13上に配置する。緩衝材14の凸部14bとFPC本体13aの配線電極13bが形成されていない面とを対峙させ、凸部14bがFPC13の配線電極13bの直上方向に位置するように緩衝材14を配置する。
【選択図】図1
Description
ガラスパネルとFPCとを異方性導電フィルムを介して接続し、接続構造体を製造した。ガラスパネルとしては、基板電極が形成されたものを使用した。FPCとしては、ガラスパネルの基板電極に対応する位置に配線電極が形成されたものを使用した。
熱加圧条件において、加圧圧力を5MPaとした以外は、実施例1と同様にして接続構造体を作製した。
緩衝材として、配線電極のライン幅(L):50μm、スペース幅(S):150μm、L/S=50/150のFPCを用いた以外は、実施例1と同様にして接続構造体を作製した。
実施例1の緩衝材本体(FPC本体)とサイズ及び形状が同一の凸部を有しないテフロンフィルム(商品名ニトフロン、日東電工包装システム株式会社製)を緩衝材として用いた以外は、実施例1と同様にして接続構造体を作製した。
熱加圧条件において加圧圧力を5MPaとした以外は、比較例1と同様にして接続構造体を作製した。
実施例1の緩衝材本体(FPC本体)とサイズ及び形状が同一の凸部を有しないシリコンラバーフィルム(商品名サーコンTR、富士分子工業株式会社製)を緩衝材として用いた以外は、実施例1と同様にして接続構造体を作製した。
熱加圧条件において加圧圧力を5MPaとした以外は、比較例3と同様にして接続構造体を作製した。
緩衝材として、配線電極のライン幅(L):150μm、スペース幅(S):50μm、L/S:150/50のFPCを用いた以外は、実施例1と同様にして接続構造体を作製した。
実施例1〜3、比較例1〜5の接続構造体について、30倍実体顕微鏡にて観察し、FPCの電極間部分と異方性導電フィルムとの間に剥離が無いものを○、FPCの電極間部分と異方性導電フィルムとの間に僅かに剥離が生じているが実用上問題ない程度のものを△、全体的に剥離しているものを×として評価した。
実施例1〜3、比較例1〜5の接続構造体について、60℃/95%RH環境下に500時間放置後(エージング後)の導通抵抗値を評価した。導通抵抗値は、デジタルマルチメーターを用いて、4端子法にて電流1mAを流したときの導通抵抗値を測定した。エージング後の導通抵抗値が5Ω未満である場合には導通良好(○)とし、5Ω以上10Ω未満である場合には導通がやや不良(△)とし、10Ω以上である場合には導通不良(×)として評価した。
実施例1〜3、比較例1〜5の接続構造体について、引張試験機(テンシロン、オリエンテック社製)を用いて剥離速度50mm/分で90度(Y軸方向)に引き上げ、接着強度を測定した。接着強度が5N/cm以上である場合には接着強度が高い(○)ものとし、接着強度が5N/cm未満である場合には接着強度が低い(×)ものとして評価した。
Claims (11)
- 基板と電子部品とを異方性接続する接続方法において、
異方性接続部材を介して前記基板上に前記電子部品を仮配置する仮配置工程と、
一方の面に前記電子部品の配線電極の配線パターンに応じたパターンの凸部が形成されている緩衝材を介して前記電子部品を押圧し、前記基板と該電子部品とを圧着接続する接続工程とを有し、
前記緩衝材の前記凸部は、前記電子部品本体の配線電極が形成されていない面と対峙されて前記配線電極の直上方向に位置する接続方法。 - 前記仮配置工程にて仮配置された前記電子部品上に前記緩衝材を配置する緩衝材配置工程を有し、
前記緩衝材配置工程では、前記緩衝材の前記凸部と前記電子部品本体の配線電極が形成されていない面とを対峙させ、該凸部が該電子部品の配線電極の直上方向に位置するように該緩衝材を配置する請求項1記載の接続方法。 - 前記接続工程では、前記緩衝材の上面に熱加圧ツールの加熱した加圧ヘッドを押し当てて前記基板と前記電子部品とを圧着接続する請求項1又は2記載の接続方法。
- 前記電子部品は、フレキシブルプリント基板である請求項1乃至3の何れか1項記載の接続方法。
- 前記凸部のライン幅は、前記配線電極のライン幅以下である請求項1乃至4の何れか1項記載の接続方法。
- 前記凸部のライン幅L、前記配線電極のライン幅L0、隣り合う該凸部のピッチ幅P、及び隣り合う該配線電極のピッチ幅P0において、L=0.5L0〜L0、P=P0である請求項5記載の接続方法。
- 前記凸部のライン幅は、前記配線電極のライン幅と同一である請求項1乃至4の何れか1項記載の接続方法。
- 前記凸部のライン幅L、及び隣り合う該凸部間のスペース幅Sにおいて、L/S=1/3〜1/1である請求項1乃至7の何れか1項記載の接続方法。
- 前記異方性接続部材は、絶縁性の接着剤組成物に導電性粒子が分散されてなる異方性導電部材である請求項1乃至8の何れか1項記載の接続方法。
- 基板と電子部品とが異方性接続されてなる接続構造体において、
異方性接続部材を介して前記基板上に前記電子部品を仮配置する仮配置工程と、
一方の面に前記電子部品の配線電極の配線パターンに応じたパターンの凸部が形成されている緩衝材を介して前記電子部品を押圧し、前記基板と該電子部品とを圧着接続する接続工程とを有し、
前記緩衝材の前記凸部は、前記電子部品本体の配線電極が形成されていない面と対峙されて前記配線電極の直上方向に位置する接続方法によって接続されてなる接続構造体。 - 基板と電子部品とが異方性導電接続されてなる接続構造体の製造方法において、
異方性接続部材を介して前記基板上に前記電子部品を仮配置する仮配置工程と、
一方の面に前記電子部品の配線電極の配線パターンに応じたパターンの凸部が形成されている緩衝材を介して前記電子部品を押圧し、前記基板と該電子部品とを圧着接続する接続工程とを有し、
前記緩衝材の前記凸部は、前記電子部品本体の配線電極が形成されていない面と対峙されて前記配線電極の直上方向に位置する接続構造体の製造方法。
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CN111276419A (zh) * | 2018-12-04 | 2020-06-12 | 中科院微电子研究所昆山分所 | 一种固相键合装置 |
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CN111276419A (zh) * | 2018-12-04 | 2020-06-12 | 中科院微电子研究所昆山分所 | 一种固相键合装置 |
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