JP2011528817A5 - - Google Patents

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Publication number
JP2011528817A5
JP2011528817A5 JP2011500284A JP2011500284A JP2011528817A5 JP 2011528817 A5 JP2011528817 A5 JP 2011528817A5 JP 2011500284 A JP2011500284 A JP 2011500284A JP 2011500284 A JP2011500284 A JP 2011500284A JP 2011528817 A5 JP2011528817 A5 JP 2011528817A5
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JP
Japan
Prior art keywords
instruction
instructions
pipeline
executed
paths
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Application number
JP2011500284A
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English (en)
Japanese (ja)
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JP5646448B2 (ja
JP2011528817A (ja
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Priority claimed from GB0805144A external-priority patent/GB2458487B/en
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Publication of JP2011528817A publication Critical patent/JP2011528817A/ja
Publication of JP2011528817A5 publication Critical patent/JP2011528817A5/ja
Application granted granted Critical
Publication of JP5646448B2 publication Critical patent/JP5646448B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2011500284A 2008-03-19 2009-03-13 パイプラインプロセッサ Active JP5646448B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0805144A GB2458487B (en) 2008-03-19 2008-03-19 Pipeline processors
GB0805144.3 2008-03-19
PCT/GB2009/000693 WO2009115779A1 (en) 2008-03-19 2009-03-13 Pipeline processors

Publications (3)

Publication Number Publication Date
JP2011528817A JP2011528817A (ja) 2011-11-24
JP2011528817A5 true JP2011528817A5 (enExample) 2012-05-10
JP5646448B2 JP5646448B2 (ja) 2014-12-24

Family

ID=39356772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011500284A Active JP5646448B2 (ja) 2008-03-19 2009-03-13 パイプラインプロセッサ

Country Status (5)

Country Link
US (1) US8560813B2 (enExample)
EP (1) EP2255280A1 (enExample)
JP (1) JP5646448B2 (enExample)
GB (1) GB2458487B (enExample)
WO (1) WO2009115779A1 (enExample)

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GB2466984B (en) 2009-01-16 2011-07-27 Imagination Tech Ltd Multi-threaded data processing system
WO2011104823A1 (ja) * 2010-02-23 2011-09-01 富士通株式会社 マルチコアプロセッサシステム、スレッド制御方法、およびスレッド制御プログラム
CN102033737A (zh) * 2010-06-13 2011-04-27 苏州和迈微电子技术有限公司 面向嵌入式系统的多级流水数字信号处理器体系结构
KR101711388B1 (ko) * 2013-01-28 2017-03-02 삼성전자주식회사 파이프라인에서 블럭을 스케줄하는 컴파일 방법 및 장치
US9696992B2 (en) * 2014-12-23 2017-07-04 Intel Corporation Apparatus and method for performing a check to optimize instruction flow
CN109634667B (zh) * 2018-12-11 2023-03-14 中国电子科技集团公司第四十七研究所 一种基于时钟的双速流水线架构微处理器及其实现方法
US11561798B2 (en) 2020-07-30 2023-01-24 International Business Machines Corporation On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer
US11614942B2 (en) 2020-10-20 2023-03-28 Micron Technology, Inc. Reuse in-flight register data in a processor
US11803391B2 (en) * 2020-10-20 2023-10-31 Micron Technology, Inc. Self-scheduling threads in a programmable atomic unit
US11809874B2 (en) * 2022-02-01 2023-11-07 Apple Inc. Conditional instructions distribution and execution on pipelines having different latencies for mispredictions
US12067399B2 (en) 2022-02-01 2024-08-20 Apple Inc. Conditional instructions prediction
US12450068B2 (en) 2023-07-25 2025-10-21 Apple Inc. Biased conditional instruction prediction

Family Cites Families (20)

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JPH0810431B2 (ja) * 1986-07-15 1996-01-31 日本電気株式会社 情報処理装置
JP2503984B2 (ja) * 1986-07-15 1996-06-05 日本電気株式会社 情報処理装置
JP3035828B2 (ja) * 1989-12-28 2000-04-24 甲府日本電気株式会社 情報処理装置
US5598547A (en) * 1990-06-11 1997-01-28 Cray Research, Inc. Vector processor having functional unit paths of differing pipeline lengths
JPH04116726A (ja) * 1990-09-07 1992-04-17 Koufu Nippon Denki Kk 情報処理装置
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
JPH07244588A (ja) * 1994-01-14 1995-09-19 Matsushita Electric Ind Co Ltd データ処理装置
SG75756A1 (en) * 1994-02-28 2000-10-24 Intel Corp Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path
JP3435278B2 (ja) * 1996-02-02 2003-08-11 東芝マイクロエレクトロニクス株式会社 データ処理装置
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US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
US5948098A (en) * 1997-06-30 1999-09-07 Sun Microsystems, Inc. Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines
WO2002019098A1 (en) * 2000-08-30 2002-03-07 Intel Corporation Method and apparatus for a unified risc/dsp pipeline controller for both reduced instruction set computer (risc) control instructions and digital signal processing (dsp) instructions
US7366877B2 (en) * 2003-09-17 2008-04-29 International Business Machines Corporation Speculative instruction issue in a simultaneously multithreaded processor
JP2005209105A (ja) * 2004-01-26 2005-08-04 Matsushita Electric Ind Co Ltd マルチスレッドプロセッサ
US7478225B1 (en) * 2004-06-30 2009-01-13 Sun Microsystems, Inc. Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor
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