JP2011528817A5 - - Google Patents

Download PDF

Info

Publication number
JP2011528817A5
JP2011528817A5 JP2011500284A JP2011500284A JP2011528817A5 JP 2011528817 A5 JP2011528817 A5 JP 2011528817A5 JP 2011500284 A JP2011500284 A JP 2011500284A JP 2011500284 A JP2011500284 A JP 2011500284A JP 2011528817 A5 JP2011528817 A5 JP 2011528817A5
Authority
JP
Japan
Prior art keywords
instruction
instructions
pipeline
executed
paths
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011500284A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011528817A (ja
JP5646448B2 (ja
Filing date
Publication date
Priority claimed from GB0805144A external-priority patent/GB2458487B/en
Application filed filed Critical
Publication of JP2011528817A publication Critical patent/JP2011528817A/ja
Publication of JP2011528817A5 publication Critical patent/JP2011528817A5/ja
Application granted granted Critical
Publication of JP5646448B2 publication Critical patent/JP5646448B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2011500284A 2008-03-19 2009-03-13 パイプラインプロセッサ Active JP5646448B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0805144.3 2008-03-19
GB0805144A GB2458487B (en) 2008-03-19 2008-03-19 Pipeline processors
PCT/GB2009/000693 WO2009115779A1 (en) 2008-03-19 2009-03-13 Pipeline processors

Publications (3)

Publication Number Publication Date
JP2011528817A JP2011528817A (ja) 2011-11-24
JP2011528817A5 true JP2011528817A5 (enExample) 2012-05-10
JP5646448B2 JP5646448B2 (ja) 2014-12-24

Family

ID=39356772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011500284A Active JP5646448B2 (ja) 2008-03-19 2009-03-13 パイプラインプロセッサ

Country Status (5)

Country Link
US (1) US8560813B2 (enExample)
EP (1) EP2255280A1 (enExample)
JP (1) JP5646448B2 (enExample)
GB (1) GB2458487B (enExample)
WO (1) WO2009115779A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2466984B (en) 2009-01-16 2011-07-27 Imagination Tech Ltd Multi-threaded data processing system
JP5408330B2 (ja) * 2010-02-23 2014-02-05 富士通株式会社 マルチコアプロセッサシステム、スレッド制御方法、およびスレッド制御プログラム
CN102033737A (zh) * 2010-06-13 2011-04-27 苏州和迈微电子技术有限公司 面向嵌入式系统的多级流水数字信号处理器体系结构
KR101711388B1 (ko) * 2013-01-28 2017-03-02 삼성전자주식회사 파이프라인에서 블럭을 스케줄하는 컴파일 방법 및 장치
US9696992B2 (en) * 2014-12-23 2017-07-04 Intel Corporation Apparatus and method for performing a check to optimize instruction flow
CN109634667B (zh) * 2018-12-11 2023-03-14 中国电子科技集团公司第四十七研究所 一种基于时钟的双速流水线架构微处理器及其实现方法
US11561798B2 (en) 2020-07-30 2023-01-24 International Business Machines Corporation On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer
US11614942B2 (en) * 2020-10-20 2023-03-28 Micron Technology, Inc. Reuse in-flight register data in a processor
US11803391B2 (en) * 2020-10-20 2023-10-31 Micron Technology, Inc. Self-scheduling threads in a programmable atomic unit
US11809874B2 (en) * 2022-02-01 2023-11-07 Apple Inc. Conditional instructions distribution and execution on pipelines having different latencies for mispredictions
US12067399B2 (en) 2022-02-01 2024-08-20 Apple Inc. Conditional instructions prediction
US12450068B2 (en) 2023-07-25 2025-10-21 Apple Inc. Biased conditional instruction prediction
US12578965B2 (en) 2023-07-25 2026-03-17 Apple Inc. Biased indirect control transfer prediction

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0810431B2 (ja) * 1986-07-15 1996-01-31 日本電気株式会社 情報処理装置
JP2503984B2 (ja) * 1986-07-15 1996-06-05 日本電気株式会社 情報処理装置
JP3035828B2 (ja) * 1989-12-28 2000-04-24 甲府日本電気株式会社 情報処理装置
US5598547A (en) * 1990-06-11 1997-01-28 Cray Research, Inc. Vector processor having functional unit paths of differing pipeline lengths
JPH04116726A (ja) * 1990-09-07 1992-04-17 Koufu Nippon Denki Kk 情報処理装置
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
JPH07244588A (ja) * 1994-01-14 1995-09-19 Matsushita Electric Ind Co Ltd データ処理装置
GB2287108B (en) * 1994-02-28 1998-05-13 Intel Corp Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path
JP3435278B2 (ja) * 1996-02-02 2003-08-11 東芝マイクロエレクトロニクス株式会社 データ処理装置
GB2311882B (en) * 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
US5948098A (en) * 1997-06-30 1999-09-07 Sun Microsystems, Inc. Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines
WO2002019098A1 (en) * 2000-08-30 2002-03-07 Intel Corporation Method and apparatus for a unified risc/dsp pipeline controller for both reduced instruction set computer (risc) control instructions and digital signal processing (dsp) instructions
US7366877B2 (en) * 2003-09-17 2008-04-29 International Business Machines Corporation Speculative instruction issue in a simultaneously multithreaded processor
JP2005209105A (ja) * 2004-01-26 2005-08-04 Matsushita Electric Ind Co Ltd マルチスレッドプロセッサ
US7478225B1 (en) * 2004-06-30 2009-01-13 Sun Microsystems, Inc. Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor
US20060200651A1 (en) * 2005-03-03 2006-09-07 Collopy Thomas K Method and apparatus for power reduction utilizing heterogeneously-multi-pipelined processor
US7415595B2 (en) * 2005-05-24 2008-08-19 Coresonic Ab Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory
US7818550B2 (en) * 2007-07-23 2010-10-19 International Business Machines Corporation Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system
US20090160863A1 (en) * 2007-12-21 2009-06-25 Michael Frank Unified Processor Architecture For Processing General and Graphics Workload

Similar Documents

Publication Publication Date Title
JP2011528817A5 (enExample)
CN101681259B (zh) 用于使用局部条件码寄存器以加速管线处理器中的条件指令执行的系统和方法
JP2012515386A5 (enExample)
RU2012149548A (ru) Команды для выполнения операции с операндом в памяти и последующего сохранения оригинального значения указанного операнда в регистре
JP5666473B2 (ja) マルチスレッド式データ処理システム
CN101957744B (zh) 一种用于微处理器的硬件多线程控制方法及其装置
US8560813B2 (en) Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
WO2006083543A3 (en) Multithreading processor including thread scheduler based on instruction stall likelihood prediction
GB2517877A (en) Controlling an order for processing data elements during vector processing
CN101763251B (zh) 含有译码缓冲装置的多线程的微处理器
JP2014513373A5 (enExample)
JP2012525620A5 (enExample)
JP2010541067A5 (enExample)
TW201714103A (en) Application scheduling in heterogeneous multiprocessor computing platforms for maximal predicted performance gains
WO2013098643A3 (en) Advanced processor architecture
EA201390868A1 (ru) Способ и система для вычислительного ускорения обработки сейсмических данных
JP2010086131A (ja) マルチスレッドプロセッサ及びその割り込み処理方法
TWI639951B (zh) 基於同時多執行緒（ｓｍｔ）的中央處理單元以及用於檢測指令的資料相關性的裝置
JP2014510351A5 (enExample)
WO2015017129A4 (en) Multi-threaded gpu pipeline
CN105094750B (zh) 一种多线程处理器的返回地址预测方法和装置
JP2008299729A (ja) プロセッサ
JP2010257199A5 (ja) プロセッサ
JP2011129130A5 (enExample)
CN104765590B (zh) 一种支持超标量与超长指令字混合架构处理器的分支预测方法