JP2011129130A5 - - Google Patents
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- Publication number
- JP2011129130A5 JP2011129130A5 JP2010283132A JP2010283132A JP2011129130A5 JP 2011129130 A5 JP2011129130 A5 JP 2011129130A5 JP 2010283132 A JP2010283132 A JP 2010283132A JP 2010283132 A JP2010283132 A JP 2010283132A JP 2011129130 A5 JP2011129130 A5 JP 2011129130A5
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- interrupt
- instructions
- processor
- branch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 17
- 238000012545 processing Methods 0.000 claims 17
- 230000000977 initiatory effect Effects 0.000 claims 1
- 238000012958 reprocessing Methods 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/642,970 US8473725B2 (en) | 2009-12-21 | 2009-12-21 | System and method for processing interrupts in a computing system |
| US12/642,970 | 2009-12-21 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011129130A JP2011129130A (ja) | 2011-06-30 |
| JP2011129130A5 true JP2011129130A5 (enExample) | 2014-02-13 |
| JP5485129B2 JP5485129B2 (ja) | 2014-05-07 |
Family
ID=43745712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010283132A Active JP5485129B2 (ja) | 2009-12-21 | 2010-12-20 | コンピュータシステムにおいて割込みを処理するシステムおよび方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8473725B2 (enExample) |
| EP (1) | EP2348399B1 (enExample) |
| JP (1) | JP5485129B2 (enExample) |
| CA (1) | CA2725906C (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9372811B2 (en) * | 2012-12-13 | 2016-06-21 | Arm Limited | Retention priority based cache replacement policy |
| CN103577242B (zh) * | 2013-11-14 | 2016-11-02 | 中国科学院声学研究所 | 针对已调度汇编代码的控制流图重构方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5922070A (en) * | 1994-01-11 | 1999-07-13 | Texas Instruments Incorporated | Pipelined data processing including program counter recycling |
| US5774709A (en) * | 1995-12-06 | 1998-06-30 | Lsi Logic Corporation | Enhanced branch delay slot handling with single exception program counter |
| JP3439033B2 (ja) * | 1996-07-08 | 2003-08-25 | 株式会社日立製作所 | 割り込み制御装置及びプロセッサ |
| US6055628A (en) * | 1997-01-24 | 2000-04-25 | Texas Instruments Incorporated | Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks |
-
2009
- 2009-12-21 US US12/642,970 patent/US8473725B2/en active Active
-
2010
- 2010-12-17 CA CA2725906A patent/CA2725906C/en active Active
- 2010-12-20 JP JP2010283132A patent/JP5485129B2/ja active Active
- 2010-12-21 EP EP10196164.7A patent/EP2348399B1/en active Active
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