CA2725906C - System and method for processing interrupts in a computing system - Google Patents

System and method for processing interrupts in a computing system Download PDF

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Publication number
CA2725906C
CA2725906C CA2725906A CA2725906A CA2725906C CA 2725906 C CA2725906 C CA 2725906C CA 2725906 A CA2725906 A CA 2725906A CA 2725906 A CA2725906 A CA 2725906A CA 2725906 C CA2725906 C CA 2725906C
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CA
Canada
Prior art keywords
instruction
instructions
interrupt
branch
branch instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CA2725906A
Other languages
English (en)
French (fr)
Other versions
CA2725906A1 (en
Inventor
Jacob (Yaakov), Jeffrey Allan (Alon)
Eitan Hai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ceva DSP Ltd
Original Assignee
Ceva DSP Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ceva DSP Ltd filed Critical Ceva DSP Ltd
Publication of CA2725906A1 publication Critical patent/CA2725906A1/en
Application granted granted Critical
Publication of CA2725906C publication Critical patent/CA2725906C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
CA2725906A 2009-12-21 2010-12-17 System and method for processing interrupts in a computing system Active CA2725906C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/642,970 US8473725B2 (en) 2009-12-21 2009-12-21 System and method for processing interrupts in a computing system
US12/642,970 2009-12-21

Publications (2)

Publication Number Publication Date
CA2725906A1 CA2725906A1 (en) 2011-06-21
CA2725906C true CA2725906C (en) 2018-11-27

Family

ID=43745712

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2725906A Active CA2725906C (en) 2009-12-21 2010-12-17 System and method for processing interrupts in a computing system

Country Status (4)

Country Link
US (1) US8473725B2 (enExample)
EP (1) EP2348399B1 (enExample)
JP (1) JP5485129B2 (enExample)
CA (1) CA2725906C (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9372811B2 (en) * 2012-12-13 2016-06-21 Arm Limited Retention priority based cache replacement policy
CN103577242B (zh) * 2013-11-14 2016-11-02 中国科学院声学研究所 针对已调度汇编代码的控制流图重构方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5922070A (en) * 1994-01-11 1999-07-13 Texas Instruments Incorporated Pipelined data processing including program counter recycling
US5774709A (en) * 1995-12-06 1998-06-30 Lsi Logic Corporation Enhanced branch delay slot handling with single exception program counter
JP3439033B2 (ja) * 1996-07-08 2003-08-25 株式会社日立製作所 割り込み制御装置及びプロセッサ
US6055628A (en) * 1997-01-24 2000-04-25 Texas Instruments Incorporated Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks

Also Published As

Publication number Publication date
JP2011129130A (ja) 2011-06-30
EP2348399B1 (en) 2013-08-07
US20110154001A1 (en) 2011-06-23
EP2348399A1 (en) 2011-07-27
JP5485129B2 (ja) 2014-05-07
US8473725B2 (en) 2013-06-25
CA2725906A1 (en) 2011-06-21

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Effective date: 20151208