JP2010541067A5 - - Google Patents

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Publication number
JP2010541067A5
JP2010541067A5 JP2010526984A JP2010526984A JP2010541067A5 JP 2010541067 A5 JP2010541067 A5 JP 2010541067A5 JP 2010526984 A JP2010526984 A JP 2010526984A JP 2010526984 A JP2010526984 A JP 2010526984A JP 2010541067 A5 JP2010541067 A5 JP 2010541067A5
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JP
Japan
Prior art keywords
debug
instruction
instructions
circuit
event
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Application number
JP2010526984A
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English (en)
Japanese (ja)
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JP5419103B2 (ja
JP2010541067A (ja
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Priority claimed from US11/864,292 external-priority patent/US8407457B2/en
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Publication of JP2010541067A publication Critical patent/JP2010541067A/ja
Publication of JP2010541067A5 publication Critical patent/JP2010541067A5/ja
Application granted granted Critical
Publication of JP5419103B2 publication Critical patent/JP5419103B2/ja
Expired - Fee Related legal-status Critical Current
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JP2010526984A 2007-09-28 2008-08-04 デバッグイベントを監視するためのシステム及び方法 Expired - Fee Related JP5419103B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/864,292 US8407457B2 (en) 2007-09-28 2007-09-28 System and method for monitoring debug events
US11/864,292 2007-09-28
PCT/US2008/072109 WO2009045628A1 (en) 2007-09-28 2008-08-04 System and method for monitoring debug events

Publications (3)

Publication Number Publication Date
JP2010541067A JP2010541067A (ja) 2010-12-24
JP2010541067A5 true JP2010541067A5 (enExample) 2011-09-22
JP5419103B2 JP5419103B2 (ja) 2014-02-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010526984A Expired - Fee Related JP5419103B2 (ja) 2007-09-28 2008-08-04 デバッグイベントを監視するためのシステム及び方法

Country Status (4)

Country Link
US (1) US8407457B2 (enExample)
JP (1) JP5419103B2 (enExample)
CN (1) CN101809542B (enExample)
WO (1) WO2009045628A1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9417987B2 (en) * 2008-06-12 2016-08-16 International Business Machines Corporation Advisory warning and workaround indications to user when stopped between load and store conditional instructions while using source level debuggers
CN101826052B (zh) * 2010-05-04 2012-07-04 中国人民解放军国防科学技术大学 Nual执行语义微处理器中保持延时一致性的断点实现方法
DE102011110151B4 (de) 2011-08-16 2018-07-26 Texas Instruments Deutschland Gmbh Halbleitervorrichtung und Verfahren zum Betreiben einer Pipeline-Ausgleichseinrichtung in einer Halbleitervorrichtung
KR101991680B1 (ko) * 2012-01-25 2019-06-21 삼성전자 주식회사 소프트웨어 파이프라인된 프로그램의 하드웨어 디버깅 장치 및 방법
US9170920B2 (en) * 2013-03-26 2015-10-27 International Business Machines Corporation Identifying and tagging breakpoint instructions for facilitation of software debug
US9619214B2 (en) 2014-08-13 2017-04-11 International Business Machines Corporation Compiler optimizations for vector instructions
US10169014B2 (en) 2014-12-19 2019-01-01 International Business Machines Corporation Compiler method for generating instructions for vector operations in a multi-endian instruction set
US9588746B2 (en) 2014-12-19 2017-03-07 International Business Machines Corporation Compiler method for generating instructions for vector operations on a multi-endian processor
US10686539B2 (en) * 2015-05-29 2020-06-16 Avago Technologies International Sales Pte. Limited Flexible debug observation point insertion in pipeline designs
US9880821B2 (en) 2015-08-17 2018-01-30 International Business Machines Corporation Compiler optimizations for vector operations that are reformatting-resistant
US9594668B1 (en) * 2015-09-04 2017-03-14 International Business Machines Corporation Debugger display of vector register contents after compiler optimizations for vector instructions
AU2016362988B2 (en) * 2015-11-30 2022-03-31 Hubbell Incorporated Interrupt exception window protocol on a data communication bus and methods and apparatuses for using same
CN106919487B (zh) * 2015-12-25 2020-08-28 北京忆芯科技有限公司 NVMe门铃处理方法及其装置
CN105760321B (zh) * 2016-02-29 2019-08-13 福州瑞芯微电子股份有限公司 SOC芯片的debug时钟域电路
CN106126360B (zh) * 2016-06-28 2020-08-25 海信视像科技股份有限公司 地址空洞屏蔽方法及装置
CN108460296A (zh) * 2016-12-09 2018-08-28 上海新微技术研发中心有限公司 一种具有调试接口安全机制的soc芯片及方法
US11256605B2 (en) 2017-10-19 2022-02-22 Samsung Electronics Co., Ltd. Nonvolatile memory device
KR102396448B1 (ko) 2017-10-19 2022-05-11 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 동작 방법
US11599445B2 (en) * 2018-06-15 2023-03-07 Board Of Regents, The University Of Texas System Watcher: precise and fully-automatic on-site failure diagnosis
US20250272096A1 (en) * 2024-02-22 2025-08-28 High Tech Technology Limited Enhanced Harvard Architecture Reduced Instruction Set Computer (RISC) with Debug Mode Access of Instruction Memory within a Unified Memory Space

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62239238A (ja) 1986-04-10 1987-10-20 Nec Corp ブレ−ク回路
US5257358A (en) * 1989-04-18 1993-10-26 Nec Electronics, Inc. Method for counting the number of program instruction completed by a microprocessor
JPH06139107A (ja) * 1992-10-30 1994-05-20 Nec Corp ブレイクアドレス検出回路
US5850562A (en) * 1994-06-27 1998-12-15 International Business Machines Corporation Personal computer apparatus and method for monitoring memory locations states for facilitating debugging of post and BIOS code
JP2752592B2 (ja) * 1994-12-28 1998-05-18 日本ヒューレット・パッカード株式会社 マイクロプロセッサ、マイクロプロセッサ−デバッグツール間信号伝送方法及びトレース方法
DE69616917T2 (de) * 1995-08-30 2002-06-06 Motorola, Inc. Datenprozessor mit eingebauter Emulationsschaltung
US5889981A (en) * 1996-05-07 1999-03-30 Lucent Technologies Inc. Apparatus and method for decoding instructions marked with breakpoint codes to select breakpoint action from plurality of breakpoint actions
GB9626401D0 (en) * 1996-12-19 1997-02-05 Sgs Thomson Microelectronics Diagnostic procedures in an integrated circuit device
JP3397230B2 (ja) * 1997-05-28 2003-04-14 松下電器産業株式会社 デバッグシステム
US6356960B1 (en) * 1997-10-29 2002-03-12 Sgs-Thomson Microelectronics Limited Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port
US6016555A (en) * 1997-11-19 2000-01-18 Texas Instruments Incorporated Non-intrusive software breakpoints in a processor instruction execution pipeline
US6321331B1 (en) * 1998-04-22 2001-11-20 Transwitch Corporation Real time debugger interface for embedded systems
DE19835610A1 (de) * 1998-08-06 2000-02-10 Siemens Ag Programmgesteuerte Einheit und Verfahren zum Debuggen derselben
US6389557B1 (en) * 1998-09-16 2002-05-14 Advanced Micro Devices, Inc. Freezing mechanism for debugging
JP2001134461A (ja) * 1999-11-05 2001-05-18 Fujitsu Ltd リセット制御システムおよび方法
US6591378B1 (en) * 2000-02-22 2003-07-08 Motorola, Inc. Debug controller in a data processor and method therefor
JP2002163126A (ja) * 2000-11-28 2002-06-07 Nec Microsystems Ltd デバッグ用ｃｐｕに内蔵のイベント検出回路、イベント検出方法および外部周辺回路
US6829701B2 (en) * 2000-12-15 2004-12-07 Intel Corporation Watchpoint engine for a pipelined processor
US6862694B1 (en) * 2001-10-05 2005-03-01 Hewlett-Packard Development Company, L.P. System and method for setting and executing breakpoints
US7051197B2 (en) * 2002-11-22 2006-05-23 Texas Instruments Incorporated Tracing through reset
US7275148B2 (en) 2003-09-08 2007-09-25 Freescale Semiconductor, Inc. Data processing system using multiple addressing modes for SIMD operations and method thereof
US20050188186A1 (en) * 2004-02-23 2005-08-25 Wolczko Mario I. Obtaining execution path information in an instruction sampling system
US7249285B2 (en) * 2004-03-25 2007-07-24 International Business Machines Corporation Address watch breakpoints in a hardware synchronization range
US7334161B2 (en) * 2004-04-30 2008-02-19 Arm Limited Breakpoint logic unit, debug logic and breakpoint method for a data processing apparatus

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