JP2014510351A5 - - Google Patents
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- Publication number
- JP2014510351A5 JP2014510351A5 JP2014502547A JP2014502547A JP2014510351A5 JP 2014510351 A5 JP2014510351 A5 JP 2014510351A5 JP 2014502547 A JP2014502547 A JP 2014502547A JP 2014502547 A JP2014502547 A JP 2014502547A JP 2014510351 A5 JP2014510351 A5 JP 2014510351A5
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- jkzd
- jknzd
- write mask
- pointer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000009191 jumping Effects 0.000 claims 3
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/078,901 US20120254593A1 (en) | 2011-04-01 | 2011-04-01 | Systems, apparatuses, and methods for jumps using a mask register |
| US13/078,901 | 2011-04-01 | ||
| PCT/US2011/064487 WO2012134561A1 (en) | 2011-04-01 | 2011-12-12 | Systems, apparatuses, and methods for jumps using a mask register |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014510351A JP2014510351A (ja) | 2014-04-24 |
| JP2014510351A5 true JP2014510351A5 (enExample) | 2015-05-21 |
| JP5947879B2 JP5947879B2 (ja) | 2016-07-06 |
Family
ID=46928903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014502547A Active JP5947879B2 (ja) | 2011-04-01 | 2011-12-12 | マスクレジスタを用いてジャンプを行うシステム、装置、および方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US20120254593A1 (enExample) |
| JP (1) | JP5947879B2 (enExample) |
| KR (1) | KR101618669B1 (enExample) |
| CN (1) | CN103718157B (enExample) |
| DE (1) | DE112011105123T5 (enExample) |
| GB (1) | GB2502754B (enExample) |
| TW (1) | TWI467478B (enExample) |
| WO (1) | WO2012134561A1 (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5739055B2 (ja) * | 2011-04-01 | 2015-06-24 | インテル コーポレイション | ベクトルフレンドリ命令フォーマット及びその実行 |
| CN104011670B (zh) | 2011-12-22 | 2016-12-28 | 英特尔公司 | 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令 |
| JP5976930B2 (ja) * | 2012-08-08 | 2016-08-24 | インテル コーポレイション | バーチャルファンクションを無効にするコールのためのサポートを含むisaブリッジング |
| JP6187478B2 (ja) * | 2013-01-11 | 2017-08-30 | 日本電気株式会社 | インデックスキー生成装置及びインデックスキー生成方法並びに検索方法 |
| US9207942B2 (en) * | 2013-03-15 | 2015-12-08 | Intel Corporation | Systems, apparatuses,and methods for zeroing of bits in a data element |
| US9411600B2 (en) * | 2013-12-08 | 2016-08-09 | Intel Corporation | Instructions and logic to provide memory access key protection functionality |
| US9715432B2 (en) * | 2014-12-23 | 2017-07-25 | Intel Corporation | Memory fault suppression via re-execution and hardware FSM |
| CN112083954B (zh) * | 2019-06-13 | 2024-09-06 | 华夏芯(北京)通用处理器技术有限公司 | 一种gpu中显式独立掩码寄存器的掩码操作方法 |
| CN117591184B (zh) * | 2023-12-08 | 2024-05-07 | 超睿科技(长沙)有限公司 | Risc-v向量压缩乱序执行的实现方法及装置 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4084226A (en) * | 1976-09-24 | 1978-04-11 | Sperry Rand Corporation | Virtual address translator |
| JPS57101938A (en) * | 1980-12-18 | 1982-06-24 | Fujitsu Ltd | Operation controlling system by first read of mask |
| JP2928680B2 (ja) * | 1992-03-30 | 1999-08-03 | 株式会社東芝 | 複合条件処理方式 |
| JPH0683858A (ja) * | 1992-06-02 | 1994-03-25 | Nec Corp | ベクトル命令処理装置 |
| JP3565314B2 (ja) * | 1998-12-17 | 2004-09-15 | 富士通株式会社 | 分岐命令実行制御装置 |
| US20100274988A1 (en) * | 2002-02-04 | 2010-10-28 | Mimar Tibet | Flexible vector modes of operation for SIMD processor |
| TWI244035B (en) * | 2004-01-30 | 2005-11-21 | Ip First Llc | A mechanism and a microprocessor apparatus for performing an indirect near jump operation |
| US7409535B2 (en) * | 2005-04-20 | 2008-08-05 | International Business Machines Corporation | Branch target prediction for multi-target branches by identifying a repeated pattern |
| US9529592B2 (en) * | 2007-12-27 | 2016-12-27 | Intel Corporation | Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation |
| TWI379230B (en) * | 2008-11-14 | 2012-12-11 | Realtek Semiconductor Corp | Instruction mode identification apparatus and instruction mode identification method |
| US9952864B2 (en) * | 2009-12-23 | 2018-04-24 | Intel Corporation | System, apparatus, and method for supporting condition codes |
-
2011
- 2011-04-01 US US13/078,901 patent/US20120254593A1/en not_active Abandoned
- 2011-12-12 GB GB1316934.7A patent/GB2502754B/en active Active
- 2011-12-12 DE DE112011105123.9T patent/DE112011105123T5/de not_active Ceased
- 2011-12-12 JP JP2014502547A patent/JP5947879B2/ja active Active
- 2011-12-12 KR KR1020137026009A patent/KR101618669B1/ko active Active
- 2011-12-12 CN CN201180069925.6A patent/CN103718157B/zh not_active Expired - Fee Related
- 2011-12-12 WO PCT/US2011/064487 patent/WO2012134561A1/en not_active Ceased
- 2011-12-14 TW TW100146252A patent/TWI467478B/zh not_active IP Right Cessation
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