JPS57101938A - Operation controlling system by first read of mask - Google Patents

Operation controlling system by first read of mask

Info

Publication number
JPS57101938A
JPS57101938A JP55179215A JP17921580A JPS57101938A JP S57101938 A JPS57101938 A JP S57101938A JP 55179215 A JP55179215 A JP 55179215A JP 17921580 A JP17921580 A JP 17921580A JP S57101938 A JPS57101938 A JP S57101938A
Authority
JP
Japan
Prior art keywords
mask
data
mask data
instruction
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55179215A
Other languages
Japanese (ja)
Inventor
Satoru Kawai
Hideo Miyanaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55179215A priority Critical patent/JPS57101938A/en
Publication of JPS57101938A publication Critical patent/JPS57101938A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Abstract

PURPOSE:To efficiently use a pipe line operator, by immediately generating an end signal showing an end of an instruction, in case when plural mask elements are designating nonexecution of an operation continuously. CONSTITUTION:Operand data is inputted in order to a data pipe line DP, and to a mask pipe MP, a mask data is inputted in order. Both the operand data and mask data are read out from a memory register, and a result of operation is stored in the memory register when the corresponding mask data is on (or off). In this state, in case when the last mask data is present in a stage mi [(i) is one of 1-11] and all the mask data stored in the stages mi through m1 are logical ''0'', an END information signal is sent out to the instruction control part immediately. In this way, a vector instruction of the part is started promptly.
JP55179215A 1980-12-18 1980-12-18 Operation controlling system by first read of mask Pending JPS57101938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55179215A JPS57101938A (en) 1980-12-18 1980-12-18 Operation controlling system by first read of mask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55179215A JPS57101938A (en) 1980-12-18 1980-12-18 Operation controlling system by first read of mask

Publications (1)

Publication Number Publication Date
JPS57101938A true JPS57101938A (en) 1982-06-24

Family

ID=16061942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55179215A Pending JPS57101938A (en) 1980-12-18 1980-12-18 Operation controlling system by first read of mask

Country Status (1)

Country Link
JP (1) JPS57101938A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607531A (en) * 1983-06-25 1985-01-16 Fujitsu Ltd Logical simulation device
JP2014510351A (en) * 2011-04-01 2014-04-24 インテル・コーポレーション System, apparatus, and method for performing jump using mask register

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607531A (en) * 1983-06-25 1985-01-16 Fujitsu Ltd Logical simulation device
JP2014510351A (en) * 2011-04-01 2014-04-24 インテル・コーポレーション System, apparatus, and method for performing jump using mask register

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