CN103718157B - 使用掩码寄存器跳转的系统、装置和方法 - Google Patents

使用掩码寄存器跳转的系统、装置和方法 Download PDF

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Publication number
CN103718157B
CN103718157B CN201180069925.6A CN201180069925A CN103718157B CN 103718157 B CN103718157 B CN 103718157B CN 201180069925 A CN201180069925 A CN 201180069925A CN 103718157 B CN103718157 B CN 103718157B
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CN
China
Prior art keywords
instruction
bit
writemask
register
operand
Prior art date
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Expired - Fee Related
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CN201180069925.6A
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English (en)
Chinese (zh)
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CN103718157A (zh
Inventor
J·C·三额詹
B·托尔
R·C·凡伦天
M·B·吉尔卡尔
A·T·福塞斯
G·Z·克里斯沃斯
E·T·格罗科斯基
D·布拉德福德
L·K·吴
E·乌尔德-阿迈德-瓦尔
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Intel Corp
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Intel Corp
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Publication date
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Publication of CN103718157A publication Critical patent/CN103718157A/zh
Application granted granted Critical
Publication of CN103718157B publication Critical patent/CN103718157B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Complex Calculations (AREA)
CN201180069925.6A 2011-04-01 2011-12-12 使用掩码寄存器跳转的系统、装置和方法 Expired - Fee Related CN103718157B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/078,901 US20120254593A1 (en) 2011-04-01 2011-04-01 Systems, apparatuses, and methods for jumps using a mask register
US13/078,901 2011-04-01
PCT/US2011/064487 WO2012134561A1 (en) 2011-04-01 2011-12-12 Systems, apparatuses, and methods for jumps using a mask register

Publications (2)

Publication Number Publication Date
CN103718157A CN103718157A (zh) 2014-04-09
CN103718157B true CN103718157B (zh) 2017-05-24

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Family Applications (1)

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CN201180069925.6A Expired - Fee Related CN103718157B (zh) 2011-04-01 2011-12-12 使用掩码寄存器跳转的系统、装置和方法

Country Status (8)

Country Link
US (1) US20120254593A1 (enExample)
JP (1) JP5947879B2 (enExample)
KR (1) KR101618669B1 (enExample)
CN (1) CN103718157B (enExample)
DE (1) DE112011105123T5 (enExample)
GB (1) GB2502754B (enExample)
TW (1) TWI467478B (enExample)
WO (1) WO2012134561A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3422178B1 (en) * 2011-04-01 2023-02-15 Intel Corporation Vector friendly instruction format and execution thereof
CN104011670B (zh) 2011-12-22 2016-12-28 英特尔公司 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令
EP2883133A4 (en) * 2012-08-08 2016-03-23 Intel Corp ISA BREAKDOWN WITH SUPPORT FOR VIRTUAL CALL TO OVERRIDING FEATURES
JP6187478B2 (ja) * 2013-01-11 2017-08-30 日本電気株式会社 インデックスキー生成装置及びインデックスキー生成方法並びに検索方法
US9207942B2 (en) * 2013-03-15 2015-12-08 Intel Corporation Systems, apparatuses,and methods for zeroing of bits in a data element
US9411600B2 (en) * 2013-12-08 2016-08-09 Intel Corporation Instructions and logic to provide memory access key protection functionality
US9715432B2 (en) * 2014-12-23 2017-07-25 Intel Corporation Memory fault suppression via re-execution and hardware FSM
CN112083954B (zh) * 2019-06-13 2024-09-06 华夏芯（北京）通用处理器技术有限公司 一种gpu中显式独立掩码寄存器的掩码操作方法
CN117591184B (zh) * 2023-12-08 2024-05-07 超睿科技(长沙)有限公司 Risc-v向量压缩乱序执行的实现方法及装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101488084A (zh) * 2007-12-27 2009-07-22 英特尔公司 执行屏蔽加载和存储操作的指令和逻辑
US20100125720A1 (en) * 2008-11-14 2010-05-20 Jan Sheng-Yuan Instruction mode identification apparatus and method

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US4084226A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
JPS57101938A (en) * 1980-12-18 1982-06-24 Fujitsu Ltd Operation controlling system by first read of mask
JP2928680B2 (ja) * 1992-03-30 1999-08-03 株式会社東芝 複合条件処理方式
JPH0683858A (ja) * 1992-06-02 1994-03-25 Nec Corp ベクトル命令処理装置
JP3565314B2 (ja) * 1998-12-17 2004-09-15 富士通株式会社 分岐命令実行制御装置
US20100274988A1 (en) * 2002-02-04 2010-10-28 Mimar Tibet Flexible vector modes of operation for SIMD processor
TWI244035B (en) * 2004-01-30 2005-11-21 Ip First Llc A mechanism and a microprocessor apparatus for performing an indirect near jump operation
US7409535B2 (en) * 2005-04-20 2008-08-05 International Business Machines Corporation Branch target prediction for multi-target branches by identifying a repeated pattern
US9952864B2 (en) * 2009-12-23 2018-04-24 Intel Corporation System, apparatus, and method for supporting condition codes

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101488084A (zh) * 2007-12-27 2009-07-22 英特尔公司 执行屏蔽加载和存储操作的指令和逻辑
US20100125720A1 (en) * 2008-11-14 2010-05-20 Jan Sheng-Yuan Instruction mode identification apparatus and method

Also Published As

Publication number Publication date
TWI467478B (zh) 2015-01-01
GB2502754A (en) 2013-12-04
US20120254593A1 (en) 2012-10-04
JP5947879B2 (ja) 2016-07-06
KR20130140143A (ko) 2013-12-23
GB2502754B (en) 2020-09-02
DE112011105123T5 (de) 2014-03-06
KR101618669B1 (ko) 2016-05-09
JP2014510351A (ja) 2014-04-24
GB201316934D0 (en) 2013-11-06
WO2012134561A1 (en) 2012-10-04
CN103718157A (zh) 2014-04-09
TW201250585A (en) 2012-12-16

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Granted publication date: 20170524

Termination date: 20191212