DE112011105123T5 - Systeme, Vorrichtungen und Verfahren für Sprünge unter Verwendung eines Maskenregisters - Google Patents

Systeme, Vorrichtungen und Verfahren für Sprünge unter Verwendung eines Maskenregisters Download PDF

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Publication number
DE112011105123T5
DE112011105123T5 DE112011105123.9T DE112011105123T DE112011105123T5 DE 112011105123 T5 DE112011105123 T5 DE 112011105123T5 DE 112011105123 T DE112011105123 T DE 112011105123T DE 112011105123 T5 DE112011105123 T5 DE 112011105123T5
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DE
Germany
Prior art keywords
instruction
pointer
jknzd
field
jkzd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE112011105123.9T
Other languages
German (de)
English (en)
Inventor
Andrew Thomas Forsyth
George Z. Chrysos
Dennis Bradford
Robert C. Valentine
Edward Thomas Grochowski
Lisa K. Wu
Elmoustapha Ould-Ahmed-Vall
Jesus Corbal San Adrian
Bret L. Toll
Milind Baburao Girkar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE112011105123T5 publication Critical patent/DE112011105123T5/de
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Complex Calculations (AREA)
DE112011105123.9T 2011-04-01 2011-12-12 Systeme, Vorrichtungen und Verfahren für Sprünge unter Verwendung eines Maskenregisters Ceased DE112011105123T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/078,901 US20120254593A1 (en) 2011-04-01 2011-04-01 Systems, apparatuses, and methods for jumps using a mask register
US13/078,901 2011-04-01
PCT/US2011/064487 WO2012134561A1 (en) 2011-04-01 2011-12-12 Systems, apparatuses, and methods for jumps using a mask register

Publications (1)

Publication Number Publication Date
DE112011105123T5 true DE112011105123T5 (de) 2014-03-06

Family

ID=46928903

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112011105123.9T Ceased DE112011105123T5 (de) 2011-04-01 2011-12-12 Systeme, Vorrichtungen und Verfahren für Sprünge unter Verwendung eines Maskenregisters

Country Status (8)

Country Link
US (1) US20120254593A1 (enExample)
JP (1) JP5947879B2 (enExample)
KR (1) KR101618669B1 (enExample)
CN (1) CN103718157B (enExample)
DE (1) DE112011105123T5 (enExample)
GB (1) GB2502754B (enExample)
TW (1) TWI467478B (enExample)
WO (1) WO2012134561A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3805921B1 (en) 2011-04-01 2023-09-06 INTEL Corporation Vector friendly instruction format and execution thereof
US10157061B2 (en) 2011-12-22 2018-12-18 Intel Corporation Instructions for storing in general purpose registers one of two scalar constants based on the contents of vector write masks
KR101394780B1 (ko) * 2012-08-08 2014-05-15 인텔 코포레이션 오버라이딩 가상 함수 호출에 대한 지원을 포함하는 ｉｓａ 브릿징
WO2014109109A1 (ja) * 2013-01-11 2014-07-17 日本電気株式会社 インデックスキー生成装置及びインデックスキー生成方法並びに検索方法
US9207942B2 (en) * 2013-03-15 2015-12-08 Intel Corporation Systems, apparatuses,and methods for zeroing of bits in a data element
US9411600B2 (en) * 2013-12-08 2016-08-09 Intel Corporation Instructions and logic to provide memory access key protection functionality
US9715432B2 (en) * 2014-12-23 2017-07-25 Intel Corporation Memory fault suppression via re-execution and hardware FSM
CN112083954B (zh) * 2019-06-13 2024-09-06 华夏芯（北京）通用处理器技术有限公司 一种gpu中显式独立掩码寄存器的掩码操作方法
CN117591184B (zh) * 2023-12-08 2024-05-07 超睿科技(长沙)有限公司 Risc-v向量压缩乱序执行的实现方法及装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4084226A (en) * 1976-09-24 1978-04-11 Sperry Rand Corporation Virtual address translator
JPS57101938A (en) * 1980-12-18 1982-06-24 Fujitsu Ltd Operation controlling system by first read of mask
JP2928680B2 (ja) * 1992-03-30 1999-08-03 株式会社東芝 複合条件処理方式
JPH0683858A (ja) * 1992-06-02 1994-03-25 Nec Corp ベクトル命令処理装置
JP3565314B2 (ja) * 1998-12-17 2004-09-15 富士通株式会社 分岐命令実行制御装置
US20100274988A1 (en) * 2002-02-04 2010-10-28 Mimar Tibet Flexible vector modes of operation for SIMD processor
TWI244035B (en) * 2004-01-30 2005-11-21 Ip First Llc A mechanism and a microprocessor apparatus for performing an indirect near jump operation
US7409535B2 (en) * 2005-04-20 2008-08-05 International Business Machines Corporation Branch target prediction for multi-target branches by identifying a repeated pattern
US9529592B2 (en) * 2007-12-27 2016-12-27 Intel Corporation Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation
TWI379230B (en) * 2008-11-14 2012-12-11 Realtek Semiconductor Corp Instruction mode identification apparatus and instruction mode identification method
US9952864B2 (en) * 2009-12-23 2018-04-24 Intel Corporation System, apparatus, and method for supporting condition codes

Also Published As

Publication number Publication date
KR20130140143A (ko) 2013-12-23
CN103718157B (zh) 2017-05-24
TWI467478B (zh) 2015-01-01
WO2012134561A1 (en) 2012-10-04
GB2502754B (en) 2020-09-02
CN103718157A (zh) 2014-04-09
US20120254593A1 (en) 2012-10-04
GB201316934D0 (en) 2013-11-06
JP2014510351A (ja) 2014-04-24
KR101618669B1 (ko) 2016-05-09
GB2502754A (en) 2013-12-04
TW201250585A (en) 2012-12-16
JP5947879B2 (ja) 2016-07-06

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R002 Refusal decision in examination/registration proceedings
R003 Refusal decision now final