JP2015511358A5 - - Google Patents

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Publication number
JP2015511358A5
JP2015511358A5 JP2014555869A JP2014555869A JP2015511358A5 JP 2015511358 A5 JP2015511358 A5 JP 2015511358A5 JP 2014555869 A JP2014555869 A JP 2014555869A JP 2014555869 A JP2014555869 A JP 2014555869A JP 2015511358 A5 JP2015511358 A5 JP 2015511358A5
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JP
Japan
Prior art keywords
execution mode
processor
alignment
boundary
instruction
Prior art date
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Application number
JP2014555869A
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English (en)
Japanese (ja)
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JP6189866B2 (ja
JP2015511358A (ja
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Publication date
Priority claimed from US13/655,499 external-priority patent/US10055227B2/en
Application filed filed Critical
Publication of JP2015511358A publication Critical patent/JP2015511358A/ja
Publication of JP2015511358A5 publication Critical patent/JP2015511358A5/ja
Application granted granted Critical
Publication of JP6189866B2 publication Critical patent/JP6189866B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2014555869A 2012-02-07 2013-02-07 プロセッサモードを切り替えるための、呼び出される関数のアドレスの最下位ビットの使用 Expired - Fee Related JP6189866B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261595773P 2012-02-07 2012-02-07
US61/595,773 2012-02-07
US13/655,499 2012-10-19
US13/655,499 US10055227B2 (en) 2012-02-07 2012-10-19 Using the least significant bits of a called function's address to switch processor modes
PCT/US2013/025187 WO2013119842A1 (en) 2012-02-07 2013-02-07 Using the least significant bits of a called function's address to switch processor modes

Publications (3)

Publication Number Publication Date
JP2015511358A JP2015511358A (ja) 2015-04-16
JP2015511358A5 true JP2015511358A5 (enExample) 2016-03-03
JP6189866B2 JP6189866B2 (ja) 2017-08-30

Family

ID=48903962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014555869A Expired - Fee Related JP6189866B2 (ja) 2012-02-07 2013-02-07 プロセッサモードを切り替えるための、呼び出される関数のアドレスの最下位ビットの使用

Country Status (6)

Country Link
US (1) US10055227B2 (enExample)
EP (1) EP2812792B1 (enExample)
JP (1) JP6189866B2 (enExample)
KR (1) KR101847889B1 (enExample)
CN (1) CN104106044B (enExample)
WO (1) WO2013119842A1 (enExample)

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KR20160117961A (ko) 2015-04-01 2016-10-11 에스케이케미칼주식회사 이차 전지용 전해액 조성물 및 이를 포함하는 이차 전지
US10152338B2 (en) * 2016-12-14 2018-12-11 International Business Machines Corporation Marking external sibling caller routines
FR3097345B1 (fr) * 2019-06-13 2021-06-25 Stmicroelectronics Grand Ouest Sas Procede de gestion du fonctionnement d’une unite de calcul capable de fonctionner avec des instructions de tailles differentes et circuit integre correspondant
US10802854B2 (en) * 2019-08-30 2020-10-13 Alibaba Group Holding Limited Method and apparatus for interpreting bytecode instruction stream
CN114020330B (zh) * 2021-11-04 2023-11-03 苏州睿芯集成电路科技有限公司 Risc-v处理器验证中模式切换的方法、电子设备以及存储介质

Family Cites Families (21)

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DE4309532C2 (de) 1992-03-25 1996-10-31 Intel Corp Verfahren zum Sichern einer Systemabbildung eines Computersystems auf einer permanenten Speichereinrichtung sowie ein Computersystem
US6496922B1 (en) 1994-10-31 2002-12-17 Sun Microsystems, Inc. Method and apparatus for multiplatform stateless instruction set architecture (ISA) using ISA tags on-the-fly instruction translation
US5867681A (en) 1996-05-23 1999-02-02 Lsi Logic Corporation Microprocessor having register dependent immediate decompression
JP3658101B2 (ja) 1996-09-13 2005-06-08 株式会社ルネサステクノロジ データ処理装置
US6189090B1 (en) * 1997-09-17 2001-02-13 Sony Corporation Digital signal processor with variable width instructions
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
KR100308211B1 (ko) * 1999-03-27 2001-10-29 윤종용 압축 명령을 갖는 마이크로 컴퓨터 시스템
JP3616556B2 (ja) * 1999-06-29 2005-02-02 株式会社東芝 拡張命令を処理する並列プロセッサ
US6449712B1 (en) * 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd ２つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US7093108B2 (en) * 2001-02-01 2006-08-15 Arm Limited Apparatus and method for efficiently incorporating instruction set information with instruction addresses
US20050144427A1 (en) * 2001-10-23 2005-06-30 Ip-First Llc Processor including branch prediction mechanism for far jump and far call instructions
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
US7340588B2 (en) 2003-11-24 2008-03-04 International Business Machines Corporation Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
US20060174089A1 (en) 2005-02-01 2006-08-03 International Business Machines Corporation Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture
US7421568B2 (en) 2005-03-04 2008-09-02 Qualcomm Incorporated Power saving methods and apparatus to selectively enable cache bits based on known processor state
GB2435116B (en) * 2006-02-10 2010-04-07 Imagination Tech Ltd Selecting between instruction sets in a microprocessors
KR101326414B1 (ko) 2006-09-06 2013-11-11 실리콘 하이브 비.브이. 데이터 처리회로
US7711927B2 (en) * 2007-03-14 2010-05-04 Qualcomm Incorporated System, method and software to preload instructions from an instruction set other than one currently executing
US20100312991A1 (en) * 2008-05-08 2010-12-09 Mips Technologies, Inc. Microprocessor with Compact Instruction Set Architecture
US20090282220A1 (en) 2008-05-08 2009-11-12 Mips Technologies, Inc. Microprocessor with Compact Instruction Set Architecture

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