CN104106044B - 使用经调用函数的地址的最低有效位来切换处理器模式 - Google Patents

使用经调用函数的地址的最低有效位来切换处理器模式 Download PDF

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Publication number
CN104106044B
CN104106044B CN201380008133.7A CN201380008133A CN104106044B CN 104106044 B CN104106044 B CN 104106044B CN 201380008133 A CN201380008133 A CN 201380008133A CN 104106044 B CN104106044 B CN 104106044B
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mode
instruction
execution
execution mode
alignment
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Expired - Fee Related
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CN201380008133.7A
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Chinese (zh)
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CN104106044A (zh
Inventor
查尔斯·约瑟夫·塔伯尼
埃里克·詹姆斯·普隆迪克
卢西恩·科德雷斯库
苏雷什·K·文库马汉提
埃万德罗·卡洛斯·梅内塞斯
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
CN201380008133.7A 2012-02-07 2013-02-07 使用经调用函数的地址的最低有效位来切换处理器模式 Expired - Fee Related CN104106044B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261595773P 2012-02-07 2012-02-07
US61/595,773 2012-02-07
US13/655,499 2012-10-19
US13/655,499 US10055227B2 (en) 2012-02-07 2012-10-19 Using the least significant bits of a called function's address to switch processor modes
PCT/US2013/025187 WO2013119842A1 (en) 2012-02-07 2013-02-07 Using the least significant bits of a called function's address to switch processor modes

Publications (2)

Publication Number Publication Date
CN104106044A CN104106044A (zh) 2014-10-15
CN104106044B true CN104106044B (zh) 2017-10-31

Family

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Family Applications (1)

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CN201380008133.7A Expired - Fee Related CN104106044B (zh) 2012-02-07 2013-02-07 使用经调用函数的地址的最低有效位来切换处理器模式

Country Status (6)

Country Link
US (1) US10055227B2 (enExample)
EP (1) EP2812792B1 (enExample)
JP (1) JP6189866B2 (enExample)
KR (1) KR101847889B1 (enExample)
CN (1) CN104106044B (enExample)
WO (1) WO2013119842A1 (enExample)

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KR20160117961A (ko) 2015-04-01 2016-10-11 에스케이케미칼주식회사 이차 전지용 전해액 조성물 및 이를 포함하는 이차 전지
US10152338B2 (en) * 2016-12-14 2018-12-11 International Business Machines Corporation Marking external sibling caller routines
FR3097345B1 (fr) * 2019-06-13 2021-06-25 Stmicroelectronics Grand Ouest Sas Procede de gestion du fonctionnement d’une unite de calcul capable de fonctionner avec des instructions de tailles differentes et circuit integre correspondant
US10802854B2 (en) * 2019-08-30 2020-10-13 Alibaba Group Holding Limited Method and apparatus for interpreting bytecode instruction stream
CN114020330B (zh) * 2021-11-04 2023-11-03 苏州睿芯集成电路科技有限公司 Risc-v处理器验证中模式切换的方法、电子设备以及存储介质

Citations (1)

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US20050262329A1 (en) * 1999-10-01 2005-11-24 Hitachi, Ltd. Processor architecture for executing two different fixed-length instruction sets

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US6496922B1 (en) 1994-10-31 2002-12-17 Sun Microsystems, Inc. Method and apparatus for multiplatform stateless instruction set architecture (ISA) using ISA tags on-the-fly instruction translation
US5867681A (en) 1996-05-23 1999-02-02 Lsi Logic Corporation Microprocessor having register dependent immediate decompression
JP3658101B2 (ja) 1996-09-13 2005-06-08 株式会社ルネサステクノロジ データ処理装置
US6189090B1 (en) * 1997-09-17 2001-02-13 Sony Corporation Digital signal processor with variable width instructions
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
KR100308211B1 (ko) * 1999-03-27 2001-10-29 윤종용 압축 명령을 갖는 마이크로 컴퓨터 시스템
JP3616556B2 (ja) * 1999-06-29 2005-02-02 株式会社東芝 拡張命令を処理する並列プロセッサ
US6449712B1 (en) * 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
US7093108B2 (en) * 2001-02-01 2006-08-15 Arm Limited Apparatus and method for efficiently incorporating instruction set information with instruction addresses
US20050144427A1 (en) * 2001-10-23 2005-06-30 Ip-First Llc Processor including branch prediction mechanism for far jump and far call instructions
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
US7340588B2 (en) 2003-11-24 2008-03-04 International Business Machines Corporation Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
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Also Published As

Publication number Publication date
KR101847889B1 (ko) 2018-04-11
US20130205115A1 (en) 2013-08-08
KR20140123576A (ko) 2014-10-22
WO2013119842A1 (en) 2013-08-15
US10055227B2 (en) 2018-08-21
CN104106044A (zh) 2014-10-15
JP6189866B2 (ja) 2017-08-30
EP2812792A1 (en) 2014-12-17
EP2812792B1 (en) 2017-10-18
JP2015511358A (ja) 2015-04-16

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Granted publication date: 20171031

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