JP2010505195A5 - - Google Patents

Download PDF

Info

Publication number
JP2010505195A5
JP2010505195A5 JP2009530492A JP2009530492A JP2010505195A5 JP 2010505195 A5 JP2010505195 A5 JP 2010505195A5 JP 2009530492 A JP2009530492 A JP 2009530492A JP 2009530492 A JP2009530492 A JP 2009530492A JP 2010505195 A5 JP2010505195 A5 JP 2010505195A5
Authority
JP
Japan
Prior art keywords
cache
data
effective address
display instruction
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009530492A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010505195A (ja
Filing date
Publication date
Priority claimed from US11/536,085 external-priority patent/US7555605B2/en
Application filed filed Critical
Publication of JP2010505195A publication Critical patent/JP2010505195A/ja
Publication of JP2010505195A5 publication Critical patent/JP2010505195A5/ja
Pending legal-status Critical Current

Links

JP2009530492A 2006-09-28 2007-07-19 キャッシュ・メモリ・デバッグ・サポートを有するデータ処理システムおよびそのための方法 Pending JP2010505195A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/536,085 US7555605B2 (en) 2006-09-28 2006-09-28 Data processing system having cache memory debugging support and method therefor
PCT/US2007/073833 WO2008042494A2 (en) 2006-09-28 2007-07-19 Data processing system having cache memory debugging support and method therefor

Publications (2)

Publication Number Publication Date
JP2010505195A JP2010505195A (ja) 2010-02-18
JP2010505195A5 true JP2010505195A5 (enExample) 2010-09-09

Family

ID=39262339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009530492A Pending JP2010505195A (ja) 2006-09-28 2007-07-19 キャッシュ・メモリ・デバッグ・サポートを有するデータ処理システムおよびそのための方法

Country Status (4)

Country Link
US (3) US7555605B2 (enExample)
EP (1) EP2074510A4 (enExample)
JP (1) JP2010505195A (enExample)
WO (1) WO2008042494A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8972671B2 (en) * 2007-05-14 2015-03-03 Freescale Semiconductor, Inc. Method and apparatus for cache transactions in a data processing system
US20090006753A1 (en) * 2007-06-28 2009-01-01 David Arnold Luick Design structure for accessing a cache with an effective address
US20090006754A1 (en) * 2007-06-28 2009-01-01 Luick David A Design structure for l2 cache/nest address translation
US7937530B2 (en) * 2007-06-28 2011-05-03 International Business Machines Corporation Method and apparatus for accessing a cache with an effective address
US20090006803A1 (en) * 2007-06-28 2009-01-01 David Arnold Luick L2 Cache/Nest Address Translation
US8495287B2 (en) 2010-06-24 2013-07-23 International Business Machines Corporation Clock-based debugging for embedded dynamic random access memory element in a processor core
EP2761464B1 (en) 2011-09-30 2018-10-24 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
EP2761480A4 (en) 2011-09-30 2015-06-24 Intel Corp APPARATUS AND METHOD FOR IMPLEMENTING MULTINIVE MEMORY HIERARCHY ON COMMON MEMORY CHANNELS
CN107391397B (zh) 2011-09-30 2021-07-27 英特尔公司 支持近存储器和远存储器访问的存储器通道
EP2761466B1 (en) 2011-09-30 2020-08-05 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy
EP2761467B1 (en) 2011-09-30 2019-10-23 Intel Corporation Generation of far memory access signals based on usage statistic tracking
US10372590B2 (en) 2013-11-22 2019-08-06 International Business Corporation Determining instruction execution history in a debugger
US10268558B2 (en) * 2017-01-13 2019-04-23 Microsoft Technology Licensing, Llc Efficient breakpoint detection via caches
US11740993B2 (en) 2021-08-31 2023-08-29 Apple Inc. Debug trace of cache memory requests

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4635193A (en) * 1984-06-27 1987-01-06 Motorola, Inc. Data processor having selective breakpoint capability with minimal overhead
US5185878A (en) * 1988-01-20 1993-02-09 Advanced Micro Device, Inc. Programmable cache memory as well as system incorporating same and method of operating programmable cache memory
JPH03248244A (ja) * 1990-02-27 1991-11-06 Toshiba Corp キャッシュメモリを備えたプロセッサ
US5341500A (en) * 1991-04-02 1994-08-23 Motorola, Inc. Data processor with combined static and dynamic masking of operand for breakpoint operation
US5317711A (en) * 1991-06-14 1994-05-31 Integrated Device Technology, Inc. Structure and method for monitoring an internal cache
US5636363A (en) 1991-06-14 1997-06-03 Integrated Device Technology, Inc. Hardware control structure and method for off-chip monitoring entries of an on-chip cache
US5375216A (en) * 1992-02-28 1994-12-20 Motorola, Inc. Apparatus and method for optimizing performance of a cache memory in a data processing system
JPH05265799A (ja) * 1992-03-19 1993-10-15 Fujitsu Ltd データ処理装置
JPH05289904A (ja) * 1992-04-09 1993-11-05 Nec Corp キャッシュメモリのデバッグツール
EP0569987A1 (en) * 1992-05-13 1993-11-18 Nec Corporation Microprocessor incorporating cache memory enabling efficient debugging
US5491793A (en) * 1992-07-31 1996-02-13 Fujitsu Limited Debug support in a processor chip
US5732405A (en) * 1992-10-02 1998-03-24 Motorola, Inc. Method and apparatus for performing a cache operation in a data processing system
JP3175757B2 (ja) * 1996-08-13 2001-06-11 日本電気株式会社 デバッグシステム
US5892897A (en) * 1997-02-05 1999-04-06 Motorola, Inc. Method and apparatus for microprocessor debugging
US6044478A (en) 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
JPH1115691A (ja) * 1997-06-27 1999-01-22 Matsushita Electric Ind Co Ltd プロセッサおよびデバッグ装置
US6260131B1 (en) * 1997-11-18 2001-07-10 Intrinsity, Inc. Method and apparatus for TLB memory ordering
US6016555A (en) * 1997-11-19 2000-01-18 Texas Instruments Incorporated Non-intrusive software breakpoints in a processor instruction execution pipeline
US6321331B1 (en) * 1998-04-22 2001-11-20 Transwitch Corporation Real time debugger interface for embedded systems
SE9801678L (sv) * 1998-05-13 1999-11-14 Axis Ab Datorchip och datoranordning med förbättrad avlusningsförmåga
US6532553B1 (en) * 1998-12-08 2003-03-11 Arm Limited Debugging data processing systems
US6321329B1 (en) * 1999-05-19 2001-11-20 Arm Limited Executing debug instructions
US6668339B1 (en) * 1999-07-28 2003-12-23 Mitsubishi Denki Kabushiki Kaisha Microprocessor having a debug interruption function
EP1182566B1 (en) * 2000-08-21 2013-05-15 Texas Instruments France Cache operation based on range of addresses
US6968446B1 (en) * 2001-08-09 2005-11-22 Advanced Micro Devices, Inc. Flags handling for system call instructions
US6862694B1 (en) * 2001-10-05 2005-03-01 Hewlett-Packard Development Company, L.P. System and method for setting and executing breakpoints
US7168067B2 (en) * 2002-02-08 2007-01-23 Agere Systems Inc. Multiprocessor system with cache-based software breakpoints
JP2003263337A (ja) * 2002-03-08 2003-09-19 Seiko Epson Corp デバック機能内蔵型マイクロコンピュータ
US7346744B1 (en) * 2002-11-04 2008-03-18 Newisys, Inc. Methods and apparatus for maintaining remote cluster state information
US7010672B2 (en) * 2002-12-11 2006-03-07 Infineon Technologies Ag Digital processor with programmable breakpoint/watchpoint trigger generation circuit
US7039765B1 (en) * 2002-12-19 2006-05-02 Hewlett-Packard Development Company, L.P. Techniques for cache memory management using read and write operations
US6963963B2 (en) * 2003-03-25 2005-11-08 Freescale Semiconductor, Inc. Multiprocessor system having a shared main memory accessible by all processor units
US6954826B2 (en) 2003-05-21 2005-10-11 Freescale Semiconductor, Inc. Read access and storage circuitry read allocation applicable to a cache
US7434108B2 (en) * 2004-04-30 2008-10-07 Freescale Semiconductor, Inc. Masking within a data processing system having applicability for a development interface
GB2428842A (en) * 2004-05-19 2007-02-07 Arc Int Microprocessor architecture
TWI270769B (en) * 2004-11-15 2007-01-11 Sunplus Technology Co Ltd Trace, debug method and system for a processor
JP2006155098A (ja) * 2004-11-26 2006-06-15 Sanyo Electric Co Ltd マイクロコンピュータの評価方法、マイクロコンピュータの評価システム、マイクロコンピュータ
US20060143396A1 (en) * 2004-12-29 2006-06-29 Mason Cabot Method for programmer-controlled cache line eviction policy
US7840845B2 (en) * 2005-02-18 2010-11-23 Intel Corporation Method and system for setting a breakpoint
JP2006252006A (ja) * 2005-03-09 2006-09-21 Seiko Epson Corp デバッグシステム、半導体集積回路装置、マイクロコンピュータ及び電子機器
US7254678B2 (en) * 2005-03-17 2007-08-07 International Business Machines Corporation Enhanced STCX design to improve subsequent load efficiency
US7299335B2 (en) * 2005-05-27 2007-11-20 Freescale Semiconductor, Inc. Translation information retrieval transparent to processor core
US20070006042A1 (en) * 2005-06-30 2007-01-04 International Business Machines Corporation Software debug support for cache flush with access to external data location(s) through debug port
US7552283B2 (en) * 2006-01-20 2009-06-23 Qualcomm Incorporated Efficient memory hierarchy management
US8352713B2 (en) * 2006-08-09 2013-01-08 Qualcomm Incorporated Debug circuit comparing processor instruction set operating mode

Similar Documents

Publication Publication Date Title
JP2010505195A5 (enExample)
JP5258500B2 (ja) ハードウエアアクセラレータ内のデータ値のクリーニングの制御
TWI431472B (zh) 微處理器之可組態快取
JP5089226B2 (ja) Ｉ／ｏアドレス変換キャッシュ・ミスのソフトウェア・ミス処理用ハードウェア支援エクセプション
JP2005339561A5 (enExample)
CN101558391B (zh) 用于微处理器的可配置高速缓冲存储器
JP2005502120A5 (enExample)
JP2010505195A (ja) キャッシュ・メモリ・デバッグ・サポートを有するデータ処理システムおよびそのための方法
JP2011013864A (ja) 命令制御装置、命令制御方法および演算回路
JP5129023B2 (ja) キャッシュメモリ装置
JP2596712B2 (ja) 近接した分岐命令を含む命令の実行を管理するシステム及び方法
US8255602B2 (en) Effective mixing real-time software with a non-real-time operating system
US9189432B2 (en) Apparatus and method for predicting target storage unit
JP5635311B2 (ja) リンクされているデータストアにおいて、アイテムの保存およびアイテムの上書きを決定するデータ保存プロトコル
US7529889B2 (en) Data processing apparatus and method for performing a cache lookup in an energy efficient manner
JP4621292B2 (ja) キャッシュ制御装置およびキャッシュ制御方法
JP2000056970A5 (enExample)
JP2008529181A5 (enExample)
JP2009258984A (ja) 情報処理装置およびロード制御方法
JP4327237B2 (ja) プリフェッチ制御装置
JP5068552B2 (ja) プリフェッチ方法、及びキャッシュ機構用ユニット
US20060026369A1 (en) Store data control device and store data control method
JP6451475B2 (ja) 演算処理装置、情報処理装置および演算処理装置の制御方法
JP2007272681A (ja) キャッシュメモリ装置及びそのキャッシュラインの入れ替え方法
JP2006221606A (ja) データプロセッサ