JP2010505195A - キャッシュ・メモリ・デバッグ・サポートを有するデータ処理システムおよびそのための方法 - Google Patents

キャッシュ・メモリ・デバッグ・サポートを有するデータ処理システムおよびそのための方法 Download PDF

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JP2010505195A
JP2010505195A JP2009530492A JP2009530492A JP2010505195A JP 2010505195 A JP2010505195 A JP 2010505195A JP 2009530492 A JP2009530492 A JP 2009530492A JP 2009530492 A JP2009530492 A JP 2009530492A JP 2010505195 A JP2010505195 A JP 2010505195A
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effective address
cache
instruction
data
tlb
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JP2009530492A
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Japanese (ja)
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JP2010505195A5 (enExample
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シー． モイヤー、ウィリアム
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NXP USA Inc
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NXP USA Inc
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Publication of JP2010505195A publication Critical patent/JP2010505195A/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
JP2009530492A 2006-09-28 2007-07-19 キャッシュ・メモリ・デバッグ・サポートを有するデータ処理システムおよびそのための方法 Pending JP2010505195A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/536,085 US7555605B2 (en) 2006-09-28 2006-09-28 Data processing system having cache memory debugging support and method therefor
PCT/US2007/073833 WO2008042494A2 (en) 2006-09-28 2007-07-19 Data processing system having cache memory debugging support and method therefor

Publications (2)

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JP2010505195A true JP2010505195A (ja) 2010-02-18
JP2010505195A5 JP2010505195A5 (enExample) 2010-09-09

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JP2009530492A Pending JP2010505195A (ja) 2006-09-28 2007-07-19 キャッシュ・メモリ・デバッグ・サポートを有するデータ処理システムおよびそのための方法

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US (3) US7555605B2 (enExample)
EP (1) EP2074510A4 (enExample)
JP (1) JP2010505195A (enExample)
WO (1) WO2008042494A2 (enExample)

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US20090006753A1 (en) * 2007-06-28 2009-01-01 David Arnold Luick Design structure for accessing a cache with an effective address
US20090006754A1 (en) * 2007-06-28 2009-01-01 Luick David A Design structure for l2 cache/nest address translation
US7937530B2 (en) * 2007-06-28 2011-05-03 International Business Machines Corporation Method and apparatus for accessing a cache with an effective address
US20090006803A1 (en) * 2007-06-28 2009-01-01 David Arnold Luick L2 Cache/Nest Address Translation
US8495287B2 (en) 2010-06-24 2013-07-23 International Business Machines Corporation Clock-based debugging for embedded dynamic random access memory element in a processor core
EP2761464B1 (en) 2011-09-30 2018-10-24 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
EP2761480A4 (en) 2011-09-30 2015-06-24 Intel Corp APPARATUS AND METHOD FOR IMPLEMENTING MULTINIVE MEMORY HIERARCHY ON COMMON MEMORY CHANNELS
CN107391397B (zh) 2011-09-30 2021-07-27 英特尔公司 支持近存储器和远存储器访问的存储器通道
EP2761466B1 (en) 2011-09-30 2020-08-05 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy
EP2761467B1 (en) 2011-09-30 2019-10-23 Intel Corporation Generation of far memory access signals based on usage statistic tracking
US10372590B2 (en) 2013-11-22 2019-08-06 International Business Corporation Determining instruction execution history in a debugger
US10268558B2 (en) * 2017-01-13 2019-04-23 Microsoft Technology Licensing, Llc Efficient breakpoint detection via caches
US11740993B2 (en) 2021-08-31 2023-08-29 Apple Inc. Debug trace of cache memory requests

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JPH05173837A (ja) * 1991-04-02 1993-07-13 Motorola Inc オペランド内の情報のスタティックおよびダイナミック・マスキングを兼ね備えるデータ処理システム
JPH05265799A (ja) * 1992-03-19 1993-10-15 Fujitsu Ltd データ処理装置
JPH1115691A (ja) * 1997-06-27 1999-01-22 Matsushita Electric Ind Co Ltd プロセッサおよびデバッグ装置
JP2006521637A (ja) * 2003-03-25 2006-09-21 フリースケール セミコンダクター インコーポレイテッド データ処理システムにおけるメモリ管理
WO2004107248A2 (en) * 2003-05-21 2004-12-09 Freescale Semiconductor, Inc. Read access and storage circuitry read allocation applicable to a cache
JP2007535760A (ja) * 2004-04-30 2007-12-06 フリースケール セミコンダクター インコーポレイテッド 開発インターフェースに対する適用性を有するデータ処理システム内におけるマスキング
JP2006155098A (ja) * 2004-11-26 2006-06-15 Sanyo Electric Co Ltd マイクロコンピュータの評価方法、マイクロコンピュータの評価システム、マイクロコンピュータ

Also Published As

Publication number Publication date
US20080082720A1 (en) 2008-04-03
EP2074510A4 (en) 2012-06-13
WO2008042494A2 (en) 2008-04-10
US7555605B2 (en) 2009-06-30
WO2008042494A3 (en) 2008-11-27
USRE49305E1 (en) 2022-11-22
USRE47851E1 (en) 2020-02-11
EP2074510A2 (en) 2009-07-01

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