GB2458487B - Pipeline processors - Google Patents

Pipeline processors

Info

Publication number
GB2458487B
GB2458487B GB0805144A GB0805144A GB2458487B GB 2458487 B GB2458487 B GB 2458487B GB 0805144 A GB0805144 A GB 0805144A GB 0805144 A GB0805144 A GB 0805144A GB 2458487 B GB2458487 B GB 2458487B
Authority
GB
United Kingdom
Prior art keywords
pipeline processors
processors
pipeline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0805144A
Other languages
English (en)
Other versions
GB0805144D0 (en
GB2458487A (en
Inventor
Andrew David Webber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imagination Technologies Ltd
Original Assignee
Imagination Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imagination Technologies Ltd filed Critical Imagination Technologies Ltd
Priority to GB0805144A priority Critical patent/GB2458487B/en
Publication of GB0805144D0 publication Critical patent/GB0805144D0/en
Priority to JP2011500284A priority patent/JP5646448B2/ja
Priority to PCT/GB2009/000693 priority patent/WO2009115779A1/en
Priority to EP09722252A priority patent/EP2255280A1/en
Priority to US12/383,118 priority patent/US8560813B2/en
Publication of GB2458487A publication Critical patent/GB2458487A/en
Application granted granted Critical
Publication of GB2458487B publication Critical patent/GB2458487B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3873—Variable length pipelines, e.g. elastic pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
GB0805144A 2008-03-19 2008-03-19 Pipeline processors Expired - Fee Related GB2458487B (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
GB0805144A GB2458487B (en) 2008-03-19 2008-03-19 Pipeline processors
JP2011500284A JP5646448B2 (ja) 2008-03-19 2009-03-13 パイプラインプロセッサ
PCT/GB2009/000693 WO2009115779A1 (en) 2008-03-19 2009-03-13 Pipeline processors
EP09722252A EP2255280A1 (en) 2008-03-19 2009-03-13 Pipeline processors
US12/383,118 US8560813B2 (en) 2008-03-19 2009-03-19 Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0805144A GB2458487B (en) 2008-03-19 2008-03-19 Pipeline processors

Publications (3)

Publication Number Publication Date
GB0805144D0 GB0805144D0 (en) 2008-04-23
GB2458487A GB2458487A (en) 2009-09-23
GB2458487B true GB2458487B (en) 2011-01-19

Family

ID=39356772

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0805144A Expired - Fee Related GB2458487B (en) 2008-03-19 2008-03-19 Pipeline processors

Country Status (5)

Country Link
US (1) US8560813B2 (enExample)
EP (1) EP2255280A1 (enExample)
JP (1) JP5646448B2 (enExample)
GB (1) GB2458487B (enExample)
WO (1) WO2009115779A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2466984B (en) 2009-01-16 2011-07-27 Imagination Tech Ltd Multi-threaded data processing system
JP5408330B2 (ja) * 2010-02-23 2014-02-05 富士通株式会社 マルチコアプロセッサシステム、スレッド制御方法、およびスレッド制御プログラム
CN102033737A (zh) * 2010-06-13 2011-04-27 苏州和迈微电子技术有限公司 面向嵌入式系统的多级流水数字信号处理器体系结构
KR101711388B1 (ko) * 2013-01-28 2017-03-02 삼성전자주식회사 파이프라인에서 블럭을 스케줄하는 컴파일 방법 및 장치
US9696992B2 (en) 2014-12-23 2017-07-04 Intel Corporation Apparatus and method for performing a check to optimize instruction flow
CN109634667B (zh) * 2018-12-11 2023-03-14 中国电子科技集团公司第四十七研究所 一种基于时钟的双速流水线架构微处理器及其实现方法
US11561798B2 (en) 2020-07-30 2023-01-24 International Business Machines Corporation On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer
US11803391B2 (en) * 2020-10-20 2023-10-31 Micron Technology, Inc. Self-scheduling threads in a programmable atomic unit
US11614942B2 (en) 2020-10-20 2023-03-28 Micron Technology, Inc. Reuse in-flight register data in a processor
US12067399B2 (en) 2022-02-01 2024-08-20 Apple Inc. Conditional instructions prediction
US11809874B2 (en) * 2022-02-01 2023-11-07 Apple Inc. Conditional instructions distribution and execution on pipelines having different latencies for mispredictions
US12450068B2 (en) 2023-07-25 2025-10-21 Apple Inc. Biased conditional instruction prediction

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
US5948098A (en) * 1997-06-30 1999-09-07 Sun Microsystems, Inc. Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines
WO2002019098A1 (en) * 2000-08-30 2002-03-07 Intel Corporation Method and apparatus for a unified risc/dsp pipeline controller for both reduced instruction set computer (risc) control instructions and digital signal processing (dsp) instructions
WO2006094196A2 (en) * 2005-03-03 2006-09-08 Qualcomm Incorporated Method and apparatus for power reduction in an heterogeneously- multi-pipelined processor

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2503984B2 (ja) * 1986-07-15 1996-06-05 日本電気株式会社 情報処理装置
JPH0810431B2 (ja) * 1986-07-15 1996-01-31 日本電気株式会社 情報処理装置
JP3035828B2 (ja) * 1989-12-28 2000-04-24 甲府日本電気株式会社 情報処理装置
US5598547A (en) * 1990-06-11 1997-01-28 Cray Research, Inc. Vector processor having functional unit paths of differing pipeline lengths
JPH04116726A (ja) * 1990-09-07 1992-04-17 Koufu Nippon Denki Kk 情報処理装置
JPH07244588A (ja) * 1994-01-14 1995-09-19 Matsushita Electric Ind Co Ltd データ処理装置
GB2287108B (en) * 1994-02-28 1998-05-13 Intel Corp Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path
JP3435278B2 (ja) * 1996-02-02 2003-08-11 東芝マイクロエレクトロニクス株式会社 データ処理装置
GB2311882B (en) * 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
US7366877B2 (en) * 2003-09-17 2008-04-29 International Business Machines Corporation Speculative instruction issue in a simultaneously multithreaded processor
JP2005209105A (ja) * 2004-01-26 2005-08-04 Matsushita Electric Ind Co Ltd マルチスレッドプロセッサ
US7478225B1 (en) * 2004-06-30 2009-01-13 Sun Microsystems, Inc. Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor
US7415595B2 (en) * 2005-05-24 2008-08-19 Coresonic Ab Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory
US7818550B2 (en) * 2007-07-23 2010-10-19 International Business Machines Corporation Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system
US20090160863A1 (en) * 2007-12-21 2009-06-25 Michael Frank Unified Processor Architecture For Processing General and Graphics Workload

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
US5948098A (en) * 1997-06-30 1999-09-07 Sun Microsystems, Inc. Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines
WO2002019098A1 (en) * 2000-08-30 2002-03-07 Intel Corporation Method and apparatus for a unified risc/dsp pipeline controller for both reduced instruction set computer (risc) control instructions and digital signal processing (dsp) instructions
WO2006094196A2 (en) * 2005-03-03 2006-09-08 Qualcomm Incorporated Method and apparatus for power reduction in an heterogeneously- multi-pipelined processor

Also Published As

Publication number Publication date
GB0805144D0 (en) 2008-04-23
GB2458487A (en) 2009-09-23
US20090249037A1 (en) 2009-10-01
JP5646448B2 (ja) 2014-12-24
WO2009115779A1 (en) 2009-09-24
US8560813B2 (en) 2013-10-15
EP2255280A1 (en) 2010-12-01
JP2011528817A (ja) 2011-11-24

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20180327 AND 20180328

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20200319