JP5646448B2 - パイプラインプロセッサ - Google Patents

パイプラインプロセッサ Download PDF

Info

Publication number
JP5646448B2
JP5646448B2 JP2011500284A JP2011500284A JP5646448B2 JP 5646448 B2 JP5646448 B2 JP 5646448B2 JP 2011500284 A JP2011500284 A JP 2011500284A JP 2011500284 A JP2011500284 A JP 2011500284A JP 5646448 B2 JP5646448 B2 JP 5646448B2
Authority
JP
Japan
Prior art keywords
instruction
instructions
pipeline
path
paths
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2011500284A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011528817A (ja
JP2011528817A5 (enExample
Inventor
アンドリュー デイヴィッド ウェバー
アンドリュー デイヴィッド ウェバー
Original Assignee
イマジネイション テクノロジーズ リミテッド
イマジネイション テクノロジーズ リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by イマジネイション テクノロジーズ リミテッド, イマジネイション テクノロジーズ リミテッド filed Critical イマジネイション テクノロジーズ リミテッド
Publication of JP2011528817A publication Critical patent/JP2011528817A/ja
Publication of JP2011528817A5 publication Critical patent/JP2011528817A5/ja
Application granted granted Critical
Publication of JP5646448B2 publication Critical patent/JP5646448B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3873—Variable length pipelines, e.g. elastic pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
JP2011500284A 2008-03-19 2009-03-13 パイプラインプロセッサ Active JP5646448B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0805144.3 2008-03-19
GB0805144A GB2458487B (en) 2008-03-19 2008-03-19 Pipeline processors
PCT/GB2009/000693 WO2009115779A1 (en) 2008-03-19 2009-03-13 Pipeline processors

Publications (3)

Publication Number Publication Date
JP2011528817A JP2011528817A (ja) 2011-11-24
JP2011528817A5 JP2011528817A5 (enExample) 2012-05-10
JP5646448B2 true JP5646448B2 (ja) 2014-12-24

Family

ID=39356772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011500284A Active JP5646448B2 (ja) 2008-03-19 2009-03-13 パイプラインプロセッサ

Country Status (5)

Country Link
US (1) US8560813B2 (enExample)
EP (1) EP2255280A1 (enExample)
JP (1) JP5646448B2 (enExample)
GB (1) GB2458487B (enExample)
WO (1) WO2009115779A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2466984B (en) * 2009-01-16 2011-07-27 Imagination Tech Ltd Multi-threaded data processing system
WO2011104823A1 (ja) * 2010-02-23 2011-09-01 富士通株式会社 マルチコアプロセッサシステム、スレッド制御方法、およびスレッド制御プログラム
CN102033737A (zh) * 2010-06-13 2011-04-27 苏州和迈微电子技术有限公司 面向嵌入式系统的多级流水数字信号处理器体系结构
KR101711388B1 (ko) * 2013-01-28 2017-03-02 삼성전자주식회사 파이프라인에서 블럭을 스케줄하는 컴파일 방법 및 장치
US9696992B2 (en) 2014-12-23 2017-07-04 Intel Corporation Apparatus and method for performing a check to optimize instruction flow
CN109634667B (zh) * 2018-12-11 2023-03-14 中国电子科技集团公司第四十七研究所 一种基于时钟的双速流水线架构微处理器及其实现方法
US11561798B2 (en) 2020-07-30 2023-01-24 International Business Machines Corporation On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer
US11803391B2 (en) * 2020-10-20 2023-10-31 Micron Technology, Inc. Self-scheduling threads in a programmable atomic unit
US11614942B2 (en) * 2020-10-20 2023-03-28 Micron Technology, Inc. Reuse in-flight register data in a processor
US11809874B2 (en) * 2022-02-01 2023-11-07 Apple Inc. Conditional instructions distribution and execution on pipelines having different latencies for mispredictions
US12067399B2 (en) 2022-02-01 2024-08-20 Apple Inc. Conditional instructions prediction
US12450068B2 (en) 2023-07-25 2025-10-21 Apple Inc. Biased conditional instruction prediction

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2503984B2 (ja) * 1986-07-15 1996-06-05 日本電気株式会社 情報処理装置
JPH0810431B2 (ja) * 1986-07-15 1996-01-31 日本電気株式会社 情報処理装置
JP3035828B2 (ja) * 1989-12-28 2000-04-24 甲府日本電気株式会社 情報処理装置
US5598547A (en) * 1990-06-11 1997-01-28 Cray Research, Inc. Vector processor having functional unit paths of differing pipeline lengths
JPH04116726A (ja) * 1990-09-07 1992-04-17 Koufu Nippon Denki Kk 情報処理装置
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
JPH07244588A (ja) * 1994-01-14 1995-09-19 Matsushita Electric Ind Co Ltd データ処理装置
SG75756A1 (en) * 1994-02-28 2000-10-24 Intel Corp Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path
JP3435278B2 (ja) * 1996-02-02 2003-08-11 東芝マイクロエレクトロニクス株式会社 データ処理装置
GB2311882B (en) * 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
US5948098A (en) * 1997-06-30 1999-09-07 Sun Microsystems, Inc. Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines
AU2001285065A1 (en) * 2000-08-30 2002-03-13 Vxtel, Inc. Method and apparatus for a unified risc/dsp pipeline controller for both reducedinstruction set computer (risc) control instructions and digital signal process ing (dsp) instructions
US7366877B2 (en) * 2003-09-17 2008-04-29 International Business Machines Corporation Speculative instruction issue in a simultaneously multithreaded processor
JP2005209105A (ja) * 2004-01-26 2005-08-04 Matsushita Electric Ind Co Ltd マルチスレッドプロセッサ
US7478225B1 (en) * 2004-06-30 2009-01-13 Sun Microsystems, Inc. Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor
US20060200651A1 (en) 2005-03-03 2006-09-07 Collopy Thomas K Method and apparatus for power reduction utilizing heterogeneously-multi-pipelined processor
US7415595B2 (en) * 2005-05-24 2008-08-19 Coresonic Ab Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory
US7818550B2 (en) * 2007-07-23 2010-10-19 International Business Machines Corporation Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system
US20090160863A1 (en) * 2007-12-21 2009-06-25 Michael Frank Unified Processor Architecture For Processing General and Graphics Workload

Also Published As

Publication number Publication date
GB0805144D0 (en) 2008-04-23
EP2255280A1 (en) 2010-12-01
WO2009115779A1 (en) 2009-09-24
JP2011528817A (ja) 2011-11-24
GB2458487B (en) 2011-01-19
GB2458487A (en) 2009-09-23
US8560813B2 (en) 2013-10-15
US20090249037A1 (en) 2009-10-01

Similar Documents

Publication Publication Date Title
JP5646448B2 (ja) パイプラインプロセッサ
CN101542412B (zh) 用于多线程处理器中自动低功率模式调用的装置和方法
JP6095670B2 (ja) コンピュータ・システム内のオペランド活性情報の維持
US9715391B2 (en) Cache memory apparatus
CN108027807B (zh) 基于块的处理器核拓扑寄存器
JP3595504B2 (ja) マルチスレッド式プロセッサにおけるコンピュータ処理方法
US8423750B2 (en) Hardware assist thread for increasing code parallelism
US7360218B2 (en) System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval
JP5666473B2 (ja) マルチスレッド式データ処理システム
US7676808B2 (en) System and method for CPI load balancing in SMT processors
US20110265068A1 (en) Single Thread Performance in an In-Order Multi-Threaded Processor
US20030135716A1 (en) Method of creating a high performance virtual multiprocessor by adding a new dimension to a processor's pipeline
KR20100111700A (ko) 로킹된 오퍼레이션을 수행하기 위한 방법 및 시스템
US7028167B2 (en) Core parallel execution with different optimization characteristics to decrease dynamic execution path
US20030120882A1 (en) Apparatus and method for exiting from a software pipeline loop procedure in a digital signal processor
EP1444571B1 (en) Hidden job start preparation in an instruction-parallel processor system
US20030120900A1 (en) Apparatus and method for a software pipeline loop procedure in a digital signal processor
US20030120905A1 (en) Apparatus and method for executing a nested loop program with a software pipeline loop procedure in a digital signal processor
KR100888675B1 (ko) 임베디드 코어에서 멀티 쓰레드 실행을 위해 확장된프로세서 및 임베디드 코어에서 멀티 쓰레드 실행 방법
JP2003167748A (ja) マルチスレッド計算機
US7328327B2 (en) Technique for reducing traffic in an instruction fetch unit of a chip multiprocessor
CN1826583A (zh) 时间－固定处理器中零开销的分支和循环
JP3541356B2 (ja) 階層型命令を実行する計算機
US20030182511A1 (en) Apparatus and method for resolving an instruction conflict in a software pipeline nested loop procedure in a digital signal processor
JP5573038B2 (ja) マルチスレッドプロセッサ及びプログラム

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120313

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120313

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130912

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130926

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20131226

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140109

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140325

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140409

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140709

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140716

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140918

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141006

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141105

R150 Certificate of patent or registration of utility model

Ref document number: 5646448

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250