JP2012525620A5 - - Google Patents

Download PDF

Info

Publication number
JP2012525620A5
JP2012525620A5 JP2012507809A JP2012507809A JP2012525620A5 JP 2012525620 A5 JP2012525620 A5 JP 2012525620A5 JP 2012507809 A JP2012507809 A JP 2012507809A JP 2012507809 A JP2012507809 A JP 2012507809A JP 2012525620 A5 JP2012525620 A5 JP 2012525620A5
Authority
JP
Japan
Prior art keywords
instruction
instructions
highest priority
determining
available
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012507809A
Other languages
English (en)
Japanese (ja)
Other versions
JP5631976B2 (ja
JP2012525620A (ja
Filing date
Publication date
Priority claimed from GB0907286A external-priority patent/GB2469822B/en
Application filed filed Critical
Publication of JP2012525620A publication Critical patent/JP2012525620A/ja
Publication of JP2012525620A5 publication Critical patent/JP2012525620A5/ja
Application granted granted Critical
Publication of JP5631976B2 publication Critical patent/JP5631976B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2012507809A 2009-04-28 2010-04-27 マルチスレッドマイクロプロセッサにおける命令の発行をスケジュールするための方法及び装置 Active JP5631976B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0907286A GB2469822B (en) 2009-04-28 2009-04-28 Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor
GB0907286.9 2009-04-28
PCT/GB2010/000832 WO2010125336A1 (en) 2009-04-28 2010-04-27 Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor

Publications (3)

Publication Number Publication Date
JP2012525620A JP2012525620A (ja) 2012-10-22
JP2012525620A5 true JP2012525620A5 (enExample) 2013-06-20
JP5631976B2 JP5631976B2 (ja) 2014-11-26

Family

ID=40791924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012507809A Active JP5631976B2 (ja) 2009-04-28 2010-04-27 マルチスレッドマイクロプロセッサにおける命令の発行をスケジュールするための方法及び装置

Country Status (6)

Country Link
US (2) US9189241B2 (enExample)
EP (1) EP2425329B8 (enExample)
JP (1) JP5631976B2 (enExample)
CN (1) CN102414659B (enExample)
GB (1) GB2469822B (enExample)
WO (1) WO2010125336A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102063291B (zh) * 2011-01-13 2013-08-28 上海大学 一种前瞻线程的多级并行执行方法
US20140007087A1 (en) * 2012-06-29 2014-01-02 Mark Scott-Nash Virtual trusted platform module
US9921848B2 (en) 2014-03-27 2018-03-20 International Business Machines Corporation Address expansion and contraction in a multithreading computer system
US9218185B2 (en) 2014-03-27 2015-12-22 International Business Machines Corporation Multithreading capability information retrieval
US9354883B2 (en) 2014-03-27 2016-05-31 International Business Machines Corporation Dynamic enablement of multithreading
US9804846B2 (en) 2014-03-27 2017-10-31 International Business Machines Corporation Thread context preservation in a multithreading computer system
US9594660B2 (en) 2014-03-27 2017-03-14 International Business Machines Corporation Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores
US10102004B2 (en) 2014-03-27 2018-10-16 International Business Machines Corporation Hardware counters to track utilization in a multithreading computer system
US9417876B2 (en) 2014-03-27 2016-08-16 International Business Machines Corporation Thread context restoration in a multithreading computer system
CN108279927B (zh) * 2017-12-26 2020-07-31 芯原微电子(上海)股份有限公司 可调整指令优先级的多通道指令控制方法及系统、控制器
US11314516B2 (en) * 2018-01-19 2022-04-26 Marvell Asia Pte, Ltd. Issuing instructions based on resource conflict constraints in microprocessor
CN108710506B (zh) * 2018-05-31 2021-01-22 北京智行者科技有限公司 车辆的指令处理方法
CN111984387B (zh) * 2020-08-26 2024-06-25 上海兆芯集成电路股份有限公司 用于调度发布队列中指令的方法及处理器
US11656877B2 (en) 2021-03-31 2023-05-23 Advanced Micro Devices, Inc. Wavefront selection and execution
JP7589712B2 (ja) 2022-05-17 2024-11-26 トヨタ自動車株式会社 リソース管理装置、リソース管理方法及びリソース管理用コンピュータプログラム

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0583089B1 (en) * 1992-08-12 2000-01-26 Advanced Micro Devices, Inc. Instruction decoder
JPH08179946A (ja) * 1994-12-26 1996-07-12 Toshiba Corp プロセッサ
GB2311882B (en) 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
US6658447B2 (en) * 1997-07-08 2003-12-02 Intel Corporation Priority based simultaneous multi-threading
JP2001092657A (ja) * 1999-09-22 2001-04-06 Toshiba Corp 中央演算装置、コンパイル方法、及びコンパイルプログラムを記録した記録媒体
US6658551B1 (en) * 2000-03-30 2003-12-02 Agere Systems Inc. Method and apparatus for identifying splittable packets in a multithreaded VLIW processor
GB2372847B (en) * 2001-02-19 2004-12-29 Imagination Tech Ltd Control of priority and instruction rates on a multithreaded processor
US7051195B2 (en) * 2001-10-26 2006-05-23 Hewlett-Packard Development Company, L.P. Method of optimization of CPU and chipset performance by support of optional reads by CPU and chipset
JP3816844B2 (ja) * 2002-07-05 2006-08-30 富士通株式会社 プロセッサ及び命令制御方法
US6950925B1 (en) * 2002-08-28 2005-09-27 Advanced Micro Devices, Inc. Scheduler for use in a microprocessor that supports data-speculative execution
US20040168045A1 (en) * 2003-02-21 2004-08-26 Dale Morris Out-of-order processor executing speculative-load instructions
US20040225870A1 (en) * 2003-05-07 2004-11-11 Srinivasan Srikanth T. Method and apparatus for reducing wrong path execution in a speculative multi-threaded processor
US7366877B2 (en) * 2003-09-17 2008-04-29 International Business Machines Corporation Speculative instruction issue in a simultaneously multithreaded processor
GB2415060B (en) 2004-04-16 2007-02-14 Imagination Tech Ltd Dynamic load balancing
US7237094B2 (en) * 2004-10-14 2007-06-26 International Business Machines Corporation Instruction group formation and mechanism for SMT dispatch
US8756605B2 (en) * 2004-12-17 2014-06-17 Oracle America, Inc. Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline
US7631308B2 (en) * 2005-02-11 2009-12-08 International Business Machines Corporation Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
US7254697B2 (en) * 2005-02-11 2007-08-07 International Business Machines Corporation Method and apparatus for dynamic modification of microprocessor instruction group at dispatch
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法
US20070294693A1 (en) * 2006-06-16 2007-12-20 Microsoft Corporation Scheduling thread execution among a plurality of processors based on evaluation of memory access data
CN100578459C (zh) * 2007-06-12 2010-01-06 华为技术有限公司 线程调度方法及其装置

Similar Documents

Publication Publication Date Title
JP2012525620A5 (enExample)
WO2012087971A3 (en) Descriptor scheduler
TW201714103A (en) Application scheduling in heterogeneous multiprocessor computing platforms for maximal predicted performance gains
GB2495360B (en) Exploiting an architected last-use operand indication in a computer system operand resource pool
JP2011054161A5 (enExample)
HRP20161316T1 (hr) Postupci i sustavi raspoređivanja prekida kod višenitnih procesora
RU2015153212A (ru) Назначение и планирование потоков для нескольких очередей с учетом приоритета
WO2013188460A3 (en) A virtual load store queue having a dynamic dispatch window with a distributed structure
AU2015238662A8 (en) Control area for managing multiple threads in a computer
WO2011103825A3 (zh) 多处理器系统负载均衡的方法和装置
WO2013188705A3 (en) A virtual load store queue having a dynamic dispatch window with a unified structure
GB2485682A (en) Mapping of computer threads onto heterogeneous resources
WO2013184380A3 (en) Scheduling concurrent applications in multithreaded processors
WO2016022308A3 (en) Directed event signaling for multiprocessor systems
GB2520852A (en) Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
EP2862071A4 (en) SELECTIVE CONTROL OF COMMANDS IN A TRANSACTION PROCESSING
AP2015008392A0 (en) Modal workload scheduling in a heterogeneous multiprocessor system on a chip
JP2012150583A5 (enExample)
ATE540353T1 (de) Einteilen von threads in einem prozessor
GB201210975D0 (en) A multi-threaded processor
WO2008108133A1 (ja) タスク群割当方法、タスク群割当装置、タスク群割当プログラム、プロセッサ及びコンピュータ
WO2013126415A3 (en) Method and system for scheduling requests in a portable computing device
GB2520856A (en) Enabling Virtualization of a processor resource
EP3186704B1 (en) Multiple clustered very long instruction word processing core
JP2016508651A5 (enExample)