ATE540353T1 - Einteilen von threads in einem prozessor - Google Patents

Einteilen von threads in einem prozessor

Info

Publication number
ATE540353T1
ATE540353T1 AT08750362T AT08750362T ATE540353T1 AT E540353 T1 ATE540353 T1 AT E540353T1 AT 08750362 T AT08750362 T AT 08750362T AT 08750362 T AT08750362 T AT 08750362T AT E540353 T1 ATE540353 T1 AT E540353T1
Authority
AT
Austria
Prior art keywords
memory access
instruction
processor
threads
division
Prior art date
Application number
AT08750362T
Other languages
English (en)
Inventor
Michael David May
Original Assignee
Xmos Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xmos Ltd filed Critical Xmos Ltd
Application granted granted Critical
Publication of ATE540353T1 publication Critical patent/ATE540353T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
AT08750362T 2007-05-30 2008-05-27 Einteilen von threads in einem prozessor ATE540353T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/755,119 US7958333B2 (en) 2007-05-30 2007-05-30 Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected
PCT/EP2008/056488 WO2008145653A1 (en) 2007-05-30 2008-05-27 Scheduling threads in a processor

Publications (1)

Publication Number Publication Date
ATE540353T1 true ATE540353T1 (de) 2012-01-15

Family

ID=39775524

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08750362T ATE540353T1 (de) 2007-05-30 2008-05-27 Einteilen von threads in einem prozessor

Country Status (7)

Country Link
US (1) US7958333B2 (de)
EP (1) EP2171576B1 (de)
JP (1) JP5382735B2 (de)
KR (1) KR101486025B1 (de)
CN (1) CN101681262B (de)
AT (1) ATE540353T1 (de)
WO (1) WO2008145653A1 (de)

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US8279886B2 (en) * 2004-12-30 2012-10-02 Intel Corporation Dataport and methods thereof
JP5173714B2 (ja) * 2008-09-30 2013-04-03 ルネサスエレクトロニクス株式会社 マルチスレッドプロセッサ及びその割り込み処理方法
JP5173711B2 (ja) * 2008-09-30 2013-04-03 ルネサスエレクトロニクス株式会社 マルチスレッドプロセッサ及びそのハードウェアスレッドのスケジュール方法
US8656408B2 (en) * 2010-09-30 2014-02-18 International Business Machines Corporations Scheduling threads in a processor based on instruction type power consumption
KR101869325B1 (ko) * 2011-12-13 2018-06-21 한국전자통신연구원 이종 멀티코어 환경에서의 코어 배정 장치
US9798548B2 (en) * 2011-12-21 2017-10-24 Nvidia Corporation Methods and apparatus for scheduling instructions using pre-decode data
CN104298552B (zh) * 2013-07-15 2018-06-19 华为技术有限公司 多线程处理器的线程取指调度方法、系统和多线程处理器
CN103634207B (zh) * 2013-12-16 2016-09-14 武汉科技大学 一种静态的关键路径优先的片上网络路由优化方法
CN105182111B (zh) * 2015-08-17 2018-09-28 上海斐讯数据通信技术有限公司 一种移动终端的性能测试方法及系统
US10678544B2 (en) * 2015-09-19 2020-06-09 Microsoft Technology Licensing, Llc Initiating instruction block execution using a register access instruction
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US11977891B2 (en) 2015-09-19 2024-05-07 Microsoft Technology Licensing, Llc Implicit program order
TWI564807B (zh) 2015-11-16 2017-01-01 財團法人工業技術研究院 排程方法及應用其的處理裝置
US9928117B2 (en) * 2015-12-11 2018-03-27 Vivante Corporation Hardware access counters and event generation for coordinating multithreaded processing
DE102016214117A1 (de) * 2016-08-01 2018-02-01 Siemens Aktiengesellschaft Ermitteln einer Ausführungszeit eines Anwenderprogramms
US10437603B2 (en) * 2017-02-20 2019-10-08 Intensivate, Inc. Super-thread processor
US10275250B2 (en) * 2017-03-06 2019-04-30 Arm Limited Defer buffer
GB2569275B (en) * 2017-10-20 2020-06-03 Graphcore Ltd Time deterministic exchange
GB201717303D0 (en) 2017-10-20 2017-12-06 Graphcore Ltd Scheduling tasks in a multi-threaded processor
US11288072B2 (en) * 2019-09-11 2022-03-29 Ceremorphic, Inc. Multi-threaded processor with thread granularity
KR102474053B1 (ko) 2020-06-22 2022-12-06 주식회사 퓨리오사에이아이 뉴럴네트워크 프로세서
KR102474054B1 (ko) * 2020-06-22 2022-12-06 주식회사 퓨리오사에이아이 뉴럴네트워크 프로세서
CN112035902B (zh) * 2020-08-12 2024-03-19 北京数盾信息科技有限公司 一种面向高速高并发应用的加密模组
WO2022126532A1 (zh) * 2020-12-17 2022-06-23 华为技术有限公司 数据处理方法及装置
CN113805817B (zh) * 2021-10-09 2024-09-24 深圳百瑞互联技术有限公司 增强flash存储器随机读写能力的方法、装置、系统及介质
KR20250081199A (ko) * 2023-11-29 2025-06-05 주식회사 퓨리오사에이아이 인터 트랜스포즈가 가능한 패킷 네트워크

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JP2999907B2 (ja) * 1993-07-05 2000-01-17 三洋電機株式会社 マイクロプログラム制御方式の中央処理装置
US5515521A (en) 1994-02-08 1996-05-07 Meridian Semiconductor, Inc. Circuit and method for reducing delays associated with contention interference between code fetches and operand accesses of a microprocessor
JPH09190348A (ja) * 1996-01-09 1997-07-22 Matsushita Electric Ind Co Ltd 命令プリフェッチバッファ制御方法、命令プリフェッチバッファ制御装置、及び命令プリフェッチバッファフラッシュ方法
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6961819B2 (en) 2002-04-26 2005-11-01 Mips Technologies, Inc. Method and apparatus for redirection of operations between interfaces
WO2004044745A1 (ja) * 2002-11-13 2004-05-27 Fujitsu Limited マルチスレッディングプロセッサにおけるスケジューリング方法およびマルチスレッディングプロセッサ
US6983359B2 (en) * 2003-08-13 2006-01-03 Via-Cyrix, Inc. Processor and method for pre-fetching out-of-order instructions
US7310722B2 (en) 2003-12-18 2007-12-18 Nvidia Corporation Across-thread out of order instruction dispatch in a multithreaded graphics processor
US7506140B2 (en) * 2005-02-04 2009-03-17 Mips Technologies, Inc. Return data selector employing barrel-incrementer-based round-robin apparatus
US7478276B2 (en) * 2005-02-10 2009-01-13 International Business Machines Corporation Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
US7734897B2 (en) * 2005-12-21 2010-06-08 Arm Limited Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads

Also Published As

Publication number Publication date
CN101681262B (zh) 2013-02-13
WO2008145653A1 (en) 2008-12-04
US20080301409A1 (en) 2008-12-04
US7958333B2 (en) 2011-06-07
EP2171576B1 (de) 2012-01-04
JP2010528384A (ja) 2010-08-19
CN101681262A (zh) 2010-03-24
KR20100032399A (ko) 2010-03-25
EP2171576A1 (de) 2010-04-07
KR101486025B1 (ko) 2015-01-22
JP5382735B2 (ja) 2014-01-08

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