JP2011528154A5 - - Google Patents

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Publication number
JP2011528154A5
JP2011528154A5 JP2011516837A JP2011516837A JP2011528154A5 JP 2011528154 A5 JP2011528154 A5 JP 2011528154A5 JP 2011516837 A JP2011516837 A JP 2011516837A JP 2011516837 A JP2011516837 A JP 2011516837A JP 2011528154 A5 JP2011528154 A5 JP 2011528154A5
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JP
Japan
Prior art keywords
edge
clock signal
information
target cell
flash memory
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JP2011516837A
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English (en)
Japanese (ja)
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JP5562329B2 (ja
JP2011528154A (ja
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Priority claimed from PCT/US2009/049328 external-priority patent/WO2010002943A1/en
Publication of JP2011528154A publication Critical patent/JP2011528154A/ja
Publication of JP2011528154A5 publication Critical patent/JP2011528154A5/ja
Application granted granted Critical
Publication of JP5562329B2 publication Critical patent/JP5562329B2/ja
Expired - Fee Related legal-status Critical Current
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JP2011516837A 2008-07-01 2009-06-30 フラッシュ・メモリ・コントローラとフラッシュ・メモリ・アレイの間でインタフェースをとるための方法および装置 Expired - Fee Related JP5562329B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US13367508P 2008-07-01 2008-07-01
US61/133,675 2008-07-01
US13392108P 2008-07-07 2008-07-07
US61/133,921 2008-07-07
US13468808P 2008-07-10 2008-07-10
US61/134,688 2008-07-10
PCT/US2009/049328 WO2010002943A1 (en) 2008-07-01 2009-06-30 Methods and apparatus for interfacing between a flash memory controller and a flash memory array

Publications (3)

Publication Number Publication Date
JP2011528154A JP2011528154A (ja) 2011-11-10
JP2011528154A5 true JP2011528154A5 (enExample) 2012-08-16
JP5562329B2 JP5562329B2 (ja) 2014-07-30

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ID=40996674

Family Applications (1)

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JP2011516837A Expired - Fee Related JP5562329B2 (ja) 2008-07-01 2009-06-30 フラッシュ・メモリ・コントローラとフラッシュ・メモリ・アレイの間でインタフェースをとるための方法および装置

Country Status (8)

Country Link
US (1) US8677056B2 (enExample)
EP (1) EP2308054B1 (enExample)
JP (1) JP5562329B2 (enExample)
KR (1) KR101618677B1 (enExample)
CN (1) CN102132349B (enExample)
IL (1) IL210395A0 (enExample)
TW (1) TWI470641B (enExample)
WO (1) WO2010002943A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8429500B2 (en) 2010-03-31 2013-04-23 Lsi Corporation Methods and apparatus for computing a probability value of a received value in communication or storage systems
US8775913B2 (en) 2010-03-31 2014-07-08 Lsi Corporation Methods and apparatus for computing soft data or log likelihood ratios for received values in communication or storage systems
US8504885B2 (en) 2010-03-31 2013-08-06 Lsi Corporation Methods and apparatus for approximating a probability density function or distribution for a received value in communication or storage systems
US9030870B2 (en) * 2011-08-26 2015-05-12 Micron Technology, Inc. Threshold voltage compensation in a multilevel memory
SG11201502753YA (en) 2012-10-09 2015-05-28 Sanbio Inc Methods and compositions for treatment of retinal degeneration
US9652376B2 (en) 2013-01-28 2017-05-16 Radian Memory Systems, Inc. Cooperative flash memory control
US11249652B1 (en) 2013-01-28 2022-02-15 Radian Memory Systems, Inc. Maintenance of nonvolatile memory on host selected namespaces by a common memory controller
US10445229B1 (en) 2013-01-28 2019-10-15 Radian Memory Systems, Inc. Memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies
TWI560549B (en) * 2013-02-07 2016-12-01 Winbond Electronics Corp Access system
US9798613B2 (en) 2013-12-27 2017-10-24 Toshiba Memory Corporation Controller of nonvolatile semiconductor memory
KR102211709B1 (ko) 2014-05-19 2021-02-02 삼성전자주식회사 신호 송수신 특성을 향상한 불휘발성 메모리 시스템, 호스트 장치, 불휘발성 메모리 시스템 및 호스트의 동작방법
KR102251809B1 (ko) 2014-05-28 2021-05-13 삼성전자주식회사 메모리 시스템, 메모리 인터페이스 장치 및 메모리 시스템에서의 인터페이싱 방법
US9542118B1 (en) 2014-09-09 2017-01-10 Radian Memory Systems, Inc. Expositive flash memory control
US10552085B1 (en) 2014-09-09 2020-02-04 Radian Memory Systems, Inc. Techniques for directed data migration
US10552058B1 (en) 2015-07-17 2020-02-04 Radian Memory Systems, Inc. Techniques for delegating data processing to a cooperative memory controller
KR102530789B1 (ko) * 2018-07-11 2023-05-11 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR102733317B1 (ko) * 2019-04-15 2024-11-25 에스케이하이닉스 주식회사 간섭 보상을 위한 메모리 시스템 및 메모리 시스템의 동작 방법
US11175984B1 (en) 2019-12-09 2021-11-16 Radian Memory Systems, Inc. Erasure coding techniques for flash memory
US11586385B1 (en) 2020-05-06 2023-02-21 Radian Memory Systems, Inc. Techniques for managing writes in nonvolatile memory

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03142800A (ja) 1989-10-27 1991-06-18 Nec Corp 電気的消去・書き込み可能なプログラマブル・リード・オンリー・メモリ
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
JPH11149786A (ja) * 1997-11-18 1999-06-02 Matsushita Electric Ind Co Ltd 不揮発性半導体メモリ
US6317842B1 (en) * 1999-02-16 2001-11-13 Qlogic Corporation Method and circuit for receiving dual edge clocked data
US6467044B1 (en) * 1999-10-20 2002-10-15 International Business Machines Corporation On-board clock-control templates for testing integrated circuits
JP2002007200A (ja) * 2000-06-16 2002-01-11 Nec Corp メモリ制御装置及び動作切替方法並びにインターフェース装置、半導体集積チップ、記録媒体
JP2002093175A (ja) * 2000-09-08 2002-03-29 Toshiba Microelectronics Corp 半導体メモリ装置
JP4398962B2 (ja) * 2001-02-20 2010-01-13 株式会社東芝 半導体記憶装置のデータ書き込み方法
JP3875570B2 (ja) * 2001-02-20 2007-01-31 株式会社東芝 半導体記憶装置のデータ書き込み方法及び半導体記憶装置
JP2002251886A (ja) * 2001-02-22 2002-09-06 Seiko Instruments Inc シリアル入出力メモリ
JP2002334588A (ja) * 2001-05-11 2002-11-22 Seiko Epson Corp 不揮発性半導体記憶装置のプログラム方法
US6625081B2 (en) 2001-08-13 2003-09-23 Micron Technology, Inc. Synchronous flash memory with virtual segment architecture
JP4005000B2 (ja) * 2003-07-04 2007-11-07 株式会社東芝 半導体記憶装置及びデータ書き込み方法。
US7752380B2 (en) * 2003-07-31 2010-07-06 Sandisk Il Ltd SDRAM memory device with an embedded NAND flash controller
KR100840441B1 (ko) * 2004-03-31 2008-06-20 마이크론 테크놀로지, 인크. 집적 회로들에서의 신호 타이밍의 재구성
JP4410188B2 (ja) * 2004-11-12 2010-02-03 株式会社東芝 半導体記憶装置のデータ書き込み方法
KR101260632B1 (ko) * 2005-09-30 2013-05-03 모사이드 테크놀로지스 인코퍼레이티드 출력 제어 메모리
WO2007058846A1 (en) * 2005-11-10 2007-05-24 Sandisk Corporation Reverse coupling effect with timing information
JP2007157234A (ja) * 2005-12-05 2007-06-21 Matsushita Electric Ind Co Ltd メモリシステム
KR100673026B1 (ko) * 2006-01-24 2007-01-24 삼성전자주식회사 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법
JP4157562B2 (ja) * 2006-01-31 2008-10-01 株式会社東芝 半導体集積回路装置
JP4157563B2 (ja) * 2006-01-31 2008-10-01 株式会社東芝 半導体集積回路装置
US7400532B2 (en) 2006-02-16 2008-07-15 Micron Technology, Inc. Programming method to reduce gate coupling interference for non-volatile memory
JP2007226853A (ja) * 2006-02-21 2007-09-06 Toshiba Corp マルチチップパッケージ
JP5226669B2 (ja) * 2006-04-24 2013-07-03 サンディスク テクノロジィース インコーポレイテッド 高効率フラッシュメモリデータ転送
US8239735B2 (en) * 2006-05-12 2012-08-07 Apple Inc. Memory Device with adaptive capacity
JP5095131B2 (ja) 2006-05-31 2012-12-12 株式会社東芝 半導体記憶装置
JP4976764B2 (ja) * 2006-07-05 2012-07-18 株式会社東芝 半導体記憶装置
US7894269B2 (en) 2006-07-20 2011-02-22 Sandisk Corporation Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells
JP4940300B2 (ja) * 2006-07-20 2012-05-30 サンディスク コーポレイション プログラミング中における結合の補償
CA2660087C (en) * 2006-08-05 2014-09-23 Benhov Gmbh, Llc Memory configuration and method for calibrating read/write data based on performance characteristics of the memory configuration
JP4784466B2 (ja) * 2006-10-04 2011-10-05 三菱電機株式会社 映像情報再生方法
US8984249B2 (en) * 2006-12-20 2015-03-17 Novachips Canada Inc. ID generation apparatus and method for serially interconnected devices

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