IL210395A0 - Methods and apparatus for interfacing between a flash memory controller and a flash memory array - Google Patents

Methods and apparatus for interfacing between a flash memory controller and a flash memory array

Info

Publication number
IL210395A0
IL210395A0 IL210395A IL21039510A IL210395A0 IL 210395 A0 IL210395 A0 IL 210395A0 IL 210395 A IL210395 A IL 210395A IL 21039510 A IL21039510 A IL 21039510A IL 210395 A0 IL210395 A0 IL 210395A0
Authority
IL
Israel
Prior art keywords
flash memory
interfacing
methods
memory controller
memory array
Prior art date
Application number
IL210395A
Other languages
English (en)
Original Assignee
Lsi Corp
Yohnson Yen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Corp, Yohnson Yen filed Critical Lsi Corp
Publication of IL210395A0 publication Critical patent/IL210395A0/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
IL210395A 2008-07-01 2010-12-30 Methods and apparatus for interfacing between a flash memory controller and a flash memory array IL210395A0 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13367508P 2008-07-01 2008-07-01
US13392108P 2008-07-07 2008-07-07
US13468808P 2008-07-10 2008-07-10
PCT/US2009/049328 WO2010002943A1 (en) 2008-07-01 2009-06-30 Methods and apparatus for interfacing between a flash memory controller and a flash memory array

Publications (1)

Publication Number Publication Date
IL210395A0 true IL210395A0 (en) 2011-03-31

Family

ID=40996674

Family Applications (1)

Application Number Title Priority Date Filing Date
IL210395A IL210395A0 (en) 2008-07-01 2010-12-30 Methods and apparatus for interfacing between a flash memory controller and a flash memory array

Country Status (8)

Country Link
US (1) US8677056B2 (enExample)
EP (1) EP2308054B1 (enExample)
JP (1) JP5562329B2 (enExample)
KR (1) KR101618677B1 (enExample)
CN (1) CN102132349B (enExample)
IL (1) IL210395A0 (enExample)
TW (1) TWI470641B (enExample)
WO (1) WO2010002943A1 (enExample)

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US8504885B2 (en) 2010-03-31 2013-08-06 Lsi Corporation Methods and apparatus for approximating a probability density function or distribution for a received value in communication or storage systems
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US10445229B1 (en) 2013-01-28 2019-10-15 Radian Memory Systems, Inc. Memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies
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US9798613B2 (en) 2013-12-27 2017-10-24 Toshiba Memory Corporation Controller of nonvolatile semiconductor memory
KR102211709B1 (ko) 2014-05-19 2021-02-02 삼성전자주식회사 신호 송수신 특성을 향상한 불휘발성 메모리 시스템, 호스트 장치, 불휘발성 메모리 시스템 및 호스트의 동작방법
KR102251809B1 (ko) 2014-05-28 2021-05-13 삼성전자주식회사 메모리 시스템, 메모리 인터페이스 장치 및 메모리 시스템에서의 인터페이싱 방법
US9542118B1 (en) 2014-09-09 2017-01-10 Radian Memory Systems, Inc. Expositive flash memory control
US10552085B1 (en) 2014-09-09 2020-02-04 Radian Memory Systems, Inc. Techniques for directed data migration
US10552058B1 (en) 2015-07-17 2020-02-04 Radian Memory Systems, Inc. Techniques for delegating data processing to a cooperative memory controller
KR102530789B1 (ko) * 2018-07-11 2023-05-11 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR102733317B1 (ko) * 2019-04-15 2024-11-25 에스케이하이닉스 주식회사 간섭 보상을 위한 메모리 시스템 및 메모리 시스템의 동작 방법
US11175984B1 (en) 2019-12-09 2021-11-16 Radian Memory Systems, Inc. Erasure coding techniques for flash memory
US11586385B1 (en) 2020-05-06 2023-02-21 Radian Memory Systems, Inc. Techniques for managing writes in nonvolatile memory

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Also Published As

Publication number Publication date
CN102132349A (zh) 2011-07-20
EP2308054B1 (en) 2016-04-13
WO2010002943A1 (en) 2010-01-07
JP2011528154A (ja) 2011-11-10
TWI470641B (zh) 2015-01-21
KR20110039310A (ko) 2011-04-15
CN102132349B (zh) 2015-06-17
KR101618677B1 (ko) 2016-05-09
JP5562329B2 (ja) 2014-07-30
US8677056B2 (en) 2014-03-18
TW201007766A (en) 2010-02-16
EP2308054A1 (en) 2011-04-13
US20110138114A1 (en) 2011-06-09

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