JP2011521475A5 - - Google Patents

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Publication number
JP2011521475A5
JP2011521475A5 JP2011510665A JP2011510665A JP2011521475A5 JP 2011521475 A5 JP2011521475 A5 JP 2011521475A5 JP 2011510665 A JP2011510665 A JP 2011510665A JP 2011510665 A JP2011510665 A JP 2011510665A JP 2011521475 A5 JP2011521475 A5 JP 2011521475A5
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JP
Japan
Prior art keywords
focus
parameters
parameter
cell
line width
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Application number
JP2011510665A
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English (en)
Japanese (ja)
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JP2011521475A (ja
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Priority claimed from PCT/US2009/044594 external-priority patent/WO2009143200A2/en
Publication of JP2011521475A publication Critical patent/JP2011521475A/ja
Publication of JP2011521475A5 publication Critical patent/JP2011521475A5/ja
Pending legal-status Critical Current

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JP2011510665A 2008-05-21 2009-05-20 ツール及びプロセスの効果を分離する基板マトリクス Pending JP2011521475A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US5489708P 2008-05-21 2008-05-21
US61/054,897 2008-05-21
PCT/US2009/044594 WO2009143200A2 (en) 2008-05-21 2009-05-20 Substrate matrix to decouple tool and process effects

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2015105955A Division JP2015180953A (ja) 2008-05-21 2015-05-26 ツール及びプロセスの効果を分離する基板マトリクス

Publications (2)

Publication Number Publication Date
JP2011521475A JP2011521475A (ja) 2011-07-21
JP2011521475A5 true JP2011521475A5 (enExample) 2011-12-08

Family

ID=41340835

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2011510665A Pending JP2011521475A (ja) 2008-05-21 2009-05-20 ツール及びプロセスの効果を分離する基板マトリクス
JP2015105955A Pending JP2015180953A (ja) 2008-05-21 2015-05-26 ツール及びプロセスの効果を分離する基板マトリクス
JP2017115541A Pending JP2017201402A (ja) 2008-05-21 2017-06-13 ツール及びプロセスの効果を分離する基板マトリクス

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2015105955A Pending JP2015180953A (ja) 2008-05-21 2015-05-26 ツール及びプロセスの効果を分離する基板マトリクス
JP2017115541A Pending JP2017201402A (ja) 2008-05-21 2017-06-13 ツール及びプロセスの効果を分離する基板マトリクス

Country Status (7)

Country Link
US (1) US8142966B2 (enExample)
EP (1) EP2286447A2 (enExample)
JP (3) JP2011521475A (enExample)
KR (1) KR101504504B1 (enExample)
CN (1) CN102037550B (enExample)
IL (1) IL208576A (enExample)
WO (1) WO2009143200A2 (enExample)

Families Citing this family (12)

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Publication number Priority date Publication date Assignee Title
US9588439B1 (en) * 2010-12-21 2017-03-07 Asml Netherlands B.V. Information matrix creation and calibration test pattern selection based on computational lithography model parameters
NL2009305A (en) * 2011-08-31 2013-03-04 Asml Netherlands Bv A method of determining focus corrections, lithographic processing cell and device manufacturing method.
JP6122290B2 (ja) 2011-12-22 2017-04-26 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 再配線層を有する半導体パッケージ
US9875946B2 (en) * 2013-04-19 2018-01-23 Kla-Tencor Corporation On-device metrology
KR102242414B1 (ko) 2013-10-02 2021-04-21 에이에스엠엘 네델란즈 비.브이. 산업 공정과 관련된 진단 정보를 얻는 방법 및 장치
US9490182B2 (en) 2013-12-23 2016-11-08 Kla-Tencor Corporation Measurement of multiple patterning parameters
KR102145256B1 (ko) 2015-04-10 2020-08-19 에이에스엠엘 네델란즈 비.브이. 검사와 계측을 위한 방법 및 장치
US10504759B2 (en) 2016-04-04 2019-12-10 Kla-Tencor Corporation Semiconductor metrology with information from multiple processing steps
US9940705B2 (en) * 2016-05-04 2018-04-10 Kla-Tencor Corporation System, method and computer program product for detecting defects in a fabricated target component using consistent modulation for the target and reference components
JP6924261B2 (ja) 2016-10-20 2021-08-25 ケーエルエー コーポレイション パターニングされたウェハの特性評価のためのハイブリッド計量
JP6779173B2 (ja) * 2017-05-18 2020-11-04 株式会社荏原製作所 基板処理装置、プログラムを記録した記録媒体
WO2020141092A1 (en) * 2018-12-31 2020-07-09 Asml Netherlands B.V. In-die metrology methods and systems for process control

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JPH03265121A (ja) * 1990-03-15 1991-11-26 Fujitsu Ltd 半導体装置の製造方法
JPH04282820A (ja) * 1991-03-11 1992-10-07 Nippon Telegr & Teleph Corp <Ntt> パタン形成方法
JP3109631B2 (ja) 1992-12-14 2000-11-20 沖電気工業株式会社 ホトリソグラフィーのパターン検証方法
EP1205806A1 (en) * 2000-11-09 2002-05-15 Semiconductor300 GmbH &amp; Co KG Method for exposing a semiconductor wafer
US6625497B2 (en) * 2000-11-20 2003-09-23 Applied Materials Inc. Semiconductor processing module with integrated feedback/feed forward metrology
JP4158384B2 (ja) * 2001-07-19 2008-10-01 株式会社日立製作所 半導体デバイスの製造工程監視方法及びそのシステム
JP4288694B2 (ja) * 2001-12-20 2009-07-01 株式会社ニコン 基板保持装置、露光装置及びデバイス製造方法
JP2004072000A (ja) * 2002-08-09 2004-03-04 Matsushita Electric Ind Co Ltd 加熱装置
US6915177B2 (en) * 2002-09-30 2005-07-05 Advanced Micro Devices, Inc. Comprehensive integrated lithographic process control system based on product design and yield feedback system
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EP1507172A1 (en) * 2003-08-12 2005-02-16 ASML Netherlands B.V. Lithographic apparatus and apparatus adjustment method
JP2005228978A (ja) * 2004-02-13 2005-08-25 Canon Inc 露光装置及び半導体デバイスの製造方法
US20050185174A1 (en) * 2004-02-23 2005-08-25 Asml Netherlands B.V. Method to determine the value of process parameters based on scatterometry data
JP4361830B2 (ja) * 2004-05-13 2009-11-11 信越化学工業株式会社 レジストパターン寸法の面内分布の評価方法、フォトマスクブランクの製造方法、フォトマスクブランク、及びレジストパターン形成工程の管理方法
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US7239368B2 (en) * 2004-11-29 2007-07-03 Asml Netherlands B.V. Using unflatness information of the substrate table or mask table for decreasing overlay
US7381634B2 (en) * 2005-04-13 2008-06-03 Stats Chippac Ltd. Integrated circuit system for bonding
US7747978B2 (en) * 2005-08-08 2010-06-29 Asml Netherlands B.V. System and method for creating a focus-exposure model of a lithography process
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US7596420B2 (en) * 2006-06-19 2009-09-29 Asml Netherlands B.V. Device manufacturing method and computer program product
US7916284B2 (en) * 2006-07-18 2011-03-29 Asml Netherlands B.V. Inspection method and apparatus, lithographic apparatus, lithographic processing cell and device manufacturing method
DE102006034679A1 (de) * 2006-07-24 2008-01-31 Infineon Technologies Ag Halbleitermodul mit Leistungshalbleiterchip und passiven Bauelement sowie Verfahren zur Herstellung desselben

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