JP2011222933A - 薄膜トランジスタ、薄膜トランジスタのアクティブ層の製造方法、および表示装置 - Google Patents
薄膜トランジスタ、薄膜トランジスタのアクティブ層の製造方法、および表示装置 Download PDFInfo
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- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 claims description 5
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Abstract
【解決手段】薄膜トランジスタは、基板上に位置する第1多結晶半導体層と、第1多結晶半導体層上に位置する第2多結晶半導体層と、第1多結晶半導体層と隣接して互いに所定の間隔で離隔している金属触媒とを含む。
【選択図】図3
Description
136:第1多結晶半導体層
137:第2多結晶半導体層
20、25:薄膜トランジスタ
Claims (21)
- 基板上に位置する第1多結晶半導体層;
前記第1多結晶半導体層上に位置する第2多結晶半導体層;および
前記第1多結晶半導体層と隣接して互いに所定の間隔で離隔している金属触媒;
を含む薄膜トランジスタ。 - 前記第1多結晶半導体層および前記第2多結晶半導体層は前記金属触媒を介して結晶化する請求項1に記載の薄膜トランジスタ。
- 前記金属触媒は、ニッケル(Ni)、パラジウム(Pd)、チタニウム(Ti)、銀(Ag)、金(Au)、スズ(Sn)、アンチモン(Sb)、銅(Cu)、コバルト(Co)、モリブデン(Mo)、テルビウム(Tb)、ルテニウム(Ru)、カドミウム(Cd)、および白金(Pt)のうちの1つ以上を含む請求項2に記載の薄膜トランジスタ。
- 前記第2多結晶半導体層は前記第1多結晶半導体層に比べて0.3〜3倍の厚さを有する請求項2に記載の薄膜トランジスタ。
- 前記金属触媒は前記基板と前記第1多結晶半導体層の間に位置する請求項2に記載の薄膜トランジスタ。
- 前記金属触媒は前記第1多結晶半導体層と前記第2多結晶半導体層の間に位置する請求項2に記載の薄膜トランジスタ。
- 前記第2多結晶半導体層上に位置するゲート電極;および
前記第2多結晶半導体層にそれぞれ接続するソース電極およびドレイン電極;
をさらに含む請求項5または6に記載の薄膜トランジスタ。 - 基板上に互いに所定の間隔で離隔するように金属触媒を噴霧する段階;
前記金属触媒を間において前記基板上に第1幅を有する第1シリコン層を形成する段階;
前記第1シリコン層を覆うように前記第1シリコン層上に前記第1幅よりも大きい第2幅を有する第2シリコン層を形成する段階;
前記第1シリコン層および前記第2シリコン層を加熱して前記第1シリコン層を第1多結晶半導体層に形成し、前記第2シリコン層を第2多結晶半導体層に形成する段階;および
前記第1多結晶半導体層および前記第2多結晶半導体層が前記第1幅よりも小さい第3幅を有するように前記第1多結晶半導体層および前記第2多結晶半導体層をパターニングする段階;
を含む薄膜トランジスタのアクティブ層の製造方法。 - 前記第1多結晶半導体層および前記第2多結晶半導体層をパターニングする段階は、前記第1多結晶半導体層の両端部が除去されるように実行される請求項8に記載の薄膜トランジスタのアクティブ層の製造方法。
- 前記第1多結晶半導体層および前記第2多結晶半導体層を形成する段階は、前記金属触媒が前記第1シリコン層および前記第2シリコン層内に拡散することによって実行される請求項8に記載の薄膜トランジスタのアクティブ層の製造方法。
- 前記金属触媒を噴霧する段階は、前記金属触媒が1012/cm2〜1014/cm2の濃度で位置するように実行される請求項8に記載の薄膜トランジスタのアクティブ層の製造方法。
- 基板上に第1シリコン層を形成する段階;
前記第1シリコン層上に互いに所定の間隔で離隔するように金属触媒を噴霧する段階;
前記第1シリコン層が第1幅を有するように前記第1シリコン層をパターニングする段階;
前記金属触媒を間において前記第1シリコン層を覆うように前記第1シリコン層上に前記第1幅よりも大きい第2幅を有する第2シリコン層を形成する段階;
前記第1シリコン層および前記第2シリコン層を加熱して前記第1シリコン層を第1多結晶半導体層に形成し、前記第2シリコン層を第2多結晶半導体層に形成する段階;および
前記第1多結晶半導体層および前記第2多結晶半導体層が前記第1幅よりも小さい第3幅を有するように前記第1多結晶半導体層および前記第2多結晶半導体層をパターニングする段階;
を含む薄膜トランジスタのアクティブ層の製造方法。 - 前記第1多結晶半導体層および前記第2多結晶半導体層をパターニングする段階は、前記第1多結晶半導体層の両端部が除去されるように実行される請求項12に記載の薄膜トランジスタのアクティブ層の製造方法。
- 前記第1多結晶半導体層および前記第2多結晶半導体層を形成する段階は、前記金属触媒が前記第1シリコン層および前記第2シリコン層内に拡散することによって実行される請求項12に記載の薄膜トランジスタのアクティブ層の製造方法。
- 前記金属触媒を噴霧する段階は、前記金属触媒が1012/cm2〜1014/cm2の濃度で位置するように実行される請求項12に記載の薄膜トランジスタのアクティブ層の製造方法。
- 基板;および
前記基板上に位置する第1多結晶半導体層、前記第1多結晶半導体層上に位置する第2多結晶半導体層、および前記第1多結晶半導体層と隣接して互いに所定の間隔で離隔している金属触媒を含む薄膜トランジスタ
を含む表示装置。 - 前記第1多結晶半導体層および前記第2多結晶半導体層は前記金属触媒を介して結晶化する請求項16に記載の表示装置。
- 前記金属触媒は基板と前記第1多結晶半導体層の間に位置する請求項17に記載の表示装置。
- 前記金属触媒は前記第1多結晶半導体層と前記第2多結晶半導体層の間に位置する請求項17に記載の表示装置。
- 前記薄膜トランジスタと連結する第1電極、前記第1電極上に位置する有機発光層、および前記有機発光層上に位置する第2電極を含む有機発光素子をさらに含む請求項18または19に記載の表示装置。
- 前記薄膜トランジスタは前記第2多結晶半導体層上に位置するゲート電極、前記第2多結晶半導体層にそれぞれ接続するソース電極およびドレイン電極をさらに含み、
前記第1電極は前記ドレイン電極と接続する請求項20に記載の表示装置。
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KR20170143082A (ko) * | 2016-06-17 | 2017-12-29 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법 |
KR20180045964A (ko) * | 2016-10-26 | 2018-05-08 | 삼성디스플레이 주식회사 | 표시 장치 및 그의 제조 방법 |
KR20180064600A (ko) * | 2016-12-05 | 2018-06-15 | 삼성디스플레이 주식회사 | 플렉시블 유기 발광 표시 장치 및 그 제조방법 |
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