JP2011222770A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2011222770A JP2011222770A JP2010090771A JP2010090771A JP2011222770A JP 2011222770 A JP2011222770 A JP 2011222770A JP 2010090771 A JP2010090771 A JP 2010090771A JP 2010090771 A JP2010090771 A JP 2010090771A JP 2011222770 A JP2011222770 A JP 2011222770A
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- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000000460 chlorine Substances 0.000 claims abstract description 16
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- 238000000034 method Methods 0.000 claims description 23
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
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- 230000002950 deficient Effects 0.000 abstract description 2
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
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Abstract
【解決手段】半導体装置の製造方法は、半導体基板の第1領域に第1ゲート電極6Aを形成し、前記半導体基板の第2領域に第2ゲート電極6Bを形成し、前記第1ゲート電極の側壁に第1サイドウォール12Aを形成し、前記第2ゲート電極の側壁に第2サイドウォール12Bを形成し、前記半導体基板、前記第1ゲート電極、前記第2ゲート電極、前記第1サイドウォール及び前記第2サイドウォールを覆うように酸化膜20を形成し、前記酸化膜上に、前記第1領域を覆うようにレジストを形成し、前記レジストをマスクとして前記酸化膜20をエッチングすることにより、前記第2領域の前記酸化膜20を除去し、前記レジストを除去し、前記半導体基板及び前記第1領域の前記酸化膜20に対して、塩素を含むガスを用いてプラズマ処理を行う。
【選択図】図5
Description
Siの格子定数よりも大きいため、SiGe層が埋め込まれたソースドレイン領域に挟まれたチャネル領域に圧縮歪みが印加される。この場合、チャネル領域のホール移動度が向上することにより、PMOSFETの電流駆動能力が高まり、PMOSFETの特性向上を実現することができる。
リコン基板の表面にリセス(凹み)を形成する。そして、リセス内にSiGe層を選択エピタキシャル成長させることによって、シリコン基板にeSiGe構造が形成される。
isolation)構造の素子分離膜2を形成する。
むとともに、シリコン基板1上にシリコン酸化膜を堆積する。
リコン酸化膜の平坦化を行い、シリコン基板1に素子分離膜2を形成する。シリコン基板1に素子分離膜2を形成することにより、シリコン基板1にNMOS領域(nチャネル型MOSFETが形成される領域)と、PMOS領域(pチャネル型MOSFETが形成される領域)とがそれぞれ画定される。
NMOS領域のレジストを除去する。
にレジストを形成する。次に、第1ゲート電極6A、第1thinサイドウォール7A、第1サイドウォール12A及びPMOS領域のレジストをマスクとして、シリコン基板1のNMOS領域にソースドレイン注入を行う。このように、第1サイドウォール12Aは、シリコン基板1のNMOS領域にソースドレイン注入を行うためのオフセットスペーサとして機能する。第1thinサイドウォール7Aの形成工程を省略している場合は、第1ゲート電極6A、第1サイドウォール12A及びPMOS領域のレジストをマスクとして、シリコン基板1のNMOS領域にソースドレイン注入を行う。
化膜20を形成する。酸化膜20の膜厚は、例えば、20nmである。図2は、酸化膜20が形成された場合の半導体装置の断面図である。
接触する位置の周辺には酸化膜20の残留物が残っている。
peroxide mixture)溶液又はフッ酸を加えたAPM(ammonia hydrogen peroxide mixture)溶液を用いて、シリコン基板1の表面を洗浄する。シリコン基板1に対する洗浄処理により、リフトオフされた酸化物20の残留物の除去が行われる。図9は、PMOS領域における酸化物20の残留物を除去した場合の半導体装置の断面図である。
・基板温度 500℃以上750℃以下(例えば、550℃)
・混合ガスの全圧 1333.22Pa
・各ガスの分圧 H2(水素):1000Pa以上1500Pa以下(例えば、1300Pa)、SiH4(シラン):4Pa以上10Pa以下(例えば、6Pa)、B2H6(ジボラン):1E−3Pa以上2E−3Pa以下(例えば、1.3E−3Pa)、HCl(塩化水素):1.8Pa以上2.2Pa以下(例えば、2Pa)、GeH4(ゲルマン):4Pa以上10Pa以下(例えば、2Pa)
・Si成長速度 1nm/min
・B濃度 1E19/cm3以上1E21/cm3以下
NMOS領域のシリコン基板1を覆うように酸化膜20が形成されているため、NMOS領域のシリコン基板1の表面、第1ゲート電極6A及び第1サイドウォール12A等には、SiGe層23が形成されていない。このように、NMOS領域の酸化膜20は、SiGe成長防止マスクとして機能する。
シリコン基板1上及びシリコン基板1の上方に、層間絶縁膜30として酸化シリコン(S
iO2)膜を形成する。次に、CMP法により、層間絶縁膜30を研磨して、層間絶縁膜
30の上面を平坦化する。
テン膜に代えて、銅膜をコンタクトホール内に形成してもよい。そして、CMP法により、層間絶縁膜30の表面が露出するまで、タングステン膜及びバリアメタル膜を研磨する。この結果、コンタクトホール内にコンタクトプラグ31が形成される。図14は、層間絶縁膜30及びコンタクトプラグ31を形成した場合の半導体装置の断面図である。
ス幅(Wrecess)の寸法を示す。ゲートピッチ(Wpitch)は、隣接する第2ゲート電極
6Bのピッチである。ゲート幅(Wgate)は、第2ゲート電極6Bの幅である。SW幅(Wsw)は、第2thinサイドウォール7B及び第2サイドウォール12Bの幅である。リセス幅(Wrecess)は、リセス22の幅である。
、下記の式によって算出することが可能である。
酸化膜20としてカバレッジが良い膜を用いた場合、狭ピッチ部のリセス幅(Wrecess)が完全に埋まらないようにするための酸化膜20の膜厚は、Wrecess/2の膜厚となる。カバレッジが良い膜は、平坦部に成長する膜の膜厚と、サイドウォールの横に成長する膜の膜厚との差が小さい膜である。例えば、ゲートピッチ(Wpitch)が140nm、ゲ
ート幅(Wgate)が40nm、SW幅(Wsw)が30nmである場合、Wrecess=140nm−40nm−30nm×2=40nmとなる。したがって、狭ピッチ部のリセス幅(Wrecess)が酸化膜20で完全に埋まらないようにするための酸化膜20の膜厚は、40nm/2=20nmとなる。
2を形成することが可能となり、PMOS領域の半導体基板1の表面に形成されるリセス22の形状不良の発生を抑止することができる。PMOS領域の半導体基板1の表面に所望の形状のリセス22が形成されるため、リセス22内に形成されるSiGe層23の幅のバラツキが抑制される。これにより、チャネル領域に印加される圧縮歪みの大きさが安定化され、PMOSFETの特性の安定化を図ることが可能となる。
2 素子分離膜
3 pウェル
4 nウェル
5 ゲート絶縁膜
6A 第1ゲート電極
6B 第2ゲート電極
7A 第1thinサイドウォール
7B 第2thinサイドウォール
8、10 ポケット領域
9、11 エクステンション領域
12A 第1サイドウォール
12B 第2サイドウォール
13 ソースドレイン領域
20 酸化膜
21 レジスト
22 リセス
23 SiGe(シリコンゲルマニウム)層
24 シリサイド層
30 層間絶縁膜
31 コンタクトプラグ
32 配線層
Claims (4)
- 半導体基板の第1領域に第1ゲート電極を形成し、前記半導体基板の第2領域に第2ゲート電極を形成する工程と、
前記第1ゲート電極の側壁に第1サイドウォールを形成し、前記第2ゲート電極の側壁に第2サイドウォールを形成する工程と、
前記半導体基板、前記第1ゲート電極、前記第2ゲート電極、前記第1サイドウォール及び前記第2サイドウォールを覆うように酸化膜を形成する工程と、
前記酸化膜上に、前記第1領域を覆うようにレジストを形成する工程と、
前記レジストをマスクとして前記酸化膜をエッチングすることにより、前記第2領域の前記酸化膜を除去する工程と、
前記レジストを除去する工程と、
前記半導体基板及び前記第1領域の前記酸化膜に対して、塩素を含むガスを用いてプラズマ処理を行う工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記半導体基板に対して洗浄を行うことにより、前記第2領域に残存する前記酸化膜を除去する工程を更に備える請求項1に記載の半導体装置の製造方法。
- 前記第2領域の前記半導体基板の表面にリセスを形成する工程と、
前記リセス内にシリコンゲルマニウム層を形成する工程と、を更に備えることを特徴とする請求項2に記載の半導体装置の製造方法。 - 前記酸化膜は、TEOS(テトラエトキシシラン)、BTBAS(ビスターシャルブチルアミノシラン)又はTDMAS(テトラジメチルアミノシラン)を含む原料ガスを用いて形成することを特徴とする請求項1から3の何れか一項に記載の半導体装置の製造方法。
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JP2009503851A (ja) * | 2005-07-27 | 2009-01-29 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 応力mosデバイスの製造方法 |
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