JP2011155292A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2011155292A JP2011155292A JP2011081991A JP2011081991A JP2011155292A JP 2011155292 A JP2011155292 A JP 2011155292A JP 2011081991 A JP2011081991 A JP 2011081991A JP 2011081991 A JP2011081991 A JP 2011081991A JP 2011155292 A JP2011155292 A JP 2011155292A
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- electrode pads
- semiconductor chip
- wire
- electrode pad
- electrode
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Abstract
【解決手段】半導体チップ5の複数の第1電極パッドaと配線基板2の複数の第1接続部3b1を、複数の第1ワイヤ10b1を介して電気的に接続する工程と、第2電極パッドbと前記配線基板の複数の第2接続部3b2を、第2ワイヤ10b2を介して電気的に接続する工程と、第3電極パッドcと前記配線基板の複数の第3接続部3b3を、第3ワイヤ10b3を介して電気的に接続する工程とを有し、前記複数の第1ワイヤ10b1のそれぞれを前記複数の第1接続部3b1のそれぞれの前記第1部分に接続し、前記第3ワイヤ10b3を前記第3接続部3b3の前記第2部分に接続し、前記複数の第110b1、第210b2および第3ワイヤ10b3は、平面視において、前記半導体チップ5の前記第2辺の中心部を経由し、かつ前記第2辺と直交する仮想線5sに対して鋭角をなす角度で、前記複数の電極パッドから延在させる。
【選択図】図9
Description
(1)半導体装置は、
主面に形成され、かつ前記主面の一辺に沿って配置された複数の電極パッドを有する半導体チップと、
主面に前記半導体チップが搭載された配線基板と、
前記配線基板の前記主面に形成され、かつ前記半導体チップの前記一辺に沿って配置された複数の第1の接続部と、
前記配線基板の前記主面に形成され、かつ前記半導体チップの前記一辺から前記複数の第1の接続部よりも離れた位置に前記半導体チップの前記一辺に沿って配置された複数の第2の接続部と、
前記配線基板の前記主面に形成され、かつ前記複数の第1の接続部に夫々繋がる複数の第1の配線と、
前記配線基板の前記主面に形成され、かつ前記複数の第2の接続部に夫々繋がる複数の第2の配線と、
前記複数の電極パッドと、前記複数の第1及び第2の接続部とを夫々接続する複数のボンディングワイヤと、
前記半導体チップ、及び前記複数のボンディングワイヤを封止する樹脂封止体とを有し、
前記複数の第1の配線は、前記複数の第1の接続部の夫々から前記半導体チップの前記一辺に向かって延在し、
前記複数の第2の配線は、前記複数の第2の接続部の夫々から前記半導体チップの前記一辺と反対側に向かって延在している。
(2)前記手段(1)において、
前記複数の第1の配線の一端部は、前記複数の第1の接続部に夫々繋がり、
前記複数の第2の配線の一端部は、前記複数の第2の接続部に夫々繋がっている。
(3)前記手段(1)において、
前記第1の接続部の配列ピッチ、及び前記第2の接続部の配列ピッチは、前記電極パッドの配列ピッチの2倍である。
(4)前記手段(1)において、
前記第1及び第2の接続部、並びに前記電極パッドは、平面が方形状で形成され、
前記第1の接続部の一辺は、対応する前記電極パッドの一辺と向かい合っており、
前記第2の接続部の一辺は、対応する前記電極パッドの一辺と向かい合っている。
(5)前記手段(1)において、
前記第2の接続部は、隣り合う2つの前記第1の接続部の間に配置されている。
(6)前記手段(5)において、
前記第2の接続部は、前記2つの第1の接続部における配列ピッチの中間に配置されている。
(7)前記手段(1)において、
前記配線基板は、表層及び内層の配線層を有する多層配線構造になっている。
(8)前記手段(1)において、
前記配線基板は、表層及び内層の配線層を有する多層配線構造のビルドアップ基板である。
(9)前記手段(1)において、
前記配線基板は、表層及び内層の配線層を有する多層配線構造のセミアディティブ基板である。
(10)半導体装置の製造において、
(a)主面に形成され、かつ前記主面の一辺に沿って第1の電極パッド、第2の電極パッド及び第3の電極パッドがこの順番で繰り返し配置された半導体チップを準備する工程と、
(b)前記半導体チップが搭載されるチップ搭載部と、前記チップ搭載部の外側に前記複数の第1の電極パッドに対応して前記半導体チップの一辺に沿って配置された複数の第1の接続部と、前記半導体チップの一辺から前記複数の第1の接続部よりも離れた位置に前記複数の第2の電極パッドに対応して前記半導体チップの一辺に沿って配置された複数の第2の接続部と、前記半導体チップの一辺から前記複数の第2の接続部よりも離れた位置に前記複数の第3の電極パッドに対応して前記半導体チップの一辺に沿って配置された複数の第3の接続部とを有する配線基板を準備する工程と、
(c)前記複数の第1の接続部が前記半導体チップの一辺に沿う状態で前記配線基板のチップ搭載部に前記半導体チップを搭載する工程と、
(d)前記複数の第1の電極パッドと前記複数の第1の接続部とを複数の第1のボンディングワイヤで夫々電気的に接続する工程と、
(e)前記複数の第2の電極パッドと前記複数の第2の接続部とを前記複数の第1のボンディングワイヤよりもループ高さが高い複数の第2のボンディングワイヤで夫々電気的に接続する工程と、
(f)前記複数の第3の電極パッドと前記複数の第3の接続部とを前記第2のボンディングワイヤよりもループ高さが高い複数の第3のボンディングワイヤで夫々電気的に接続する工程と、
(g)前記半導体チップ、及び前記複数の第1乃至第3のボンディングワイヤを樹脂で封止する工程とを有し、
前記複数の第1乃至第3のボンディングワイヤは、前記半導体チップの一辺の中心を横切って前記半導体チップの一辺と直行する仮想線に対して鋭角をなす角度で延在し、
前記第3のボンディングワイヤと前記第3の電極パッドとの接続は、前記第1のボンディングワイヤと前記第1の電極パッドとの接続よりも前記半導体チップの一辺から離れた位置で行われ、
前記(e)工程、(d)工程、及び(f)工程は、この順番で行われる。
(11)前記手段(10)において、
前記第2のボンディングワイヤと前記第2の電極パッドとの接続は、前記第3のボンディングワイヤと前記第3の電極パッドとの接続よりも前記半導体チップの一辺から近い位置で行われる。
(12)前記手段(10)において、
前記第2のボンディングワイヤと前記第2の電極パッドとの接続は、前記第1のボンディングワイヤと前記第1の電極パッドとの接続よりも前記半導体チップの一辺から離れた位置で行われる。
(13)前記手段(10)において、
前記複数の第1乃至第3の電極パッドは、互いに反対側に位置する2つの長辺が前記半導体チップの一辺から遠ざかる方向に沿って延在する長方形状の平面形状になっている。
本発明によれば、半導体装置の製造歩留まり向上を図ることができる。
本実施例1では、BGA型半導体装置として、機能が異なる集積回路が搭載された複数の半導体チップを配線基板に実装して1つのシステムを構築するSIP(System In Package)型半導体装置に本発明を適用した例について説明する。
図1は、半導体装置の内部構造を示す模式的平面図、
図2は、図1におけるボンディングワイヤの一部を省略して示す模式的平面図、
図3は、図1のa’−a’線に沿う模式的断面図、
図4は、図1のb’−b’線に沿う模式的断面図、
図5は、図1の一部(部分A)を簡略化して示す模式的平面図、
図6は、図5におけるボンディングワイヤを削除して示す模式的平面図、
図7は、図5のc’−c’線に沿う模式的断面図、
図8は、図5のd’−d’線に沿う模式的断面図、
図9は、図1の一部(部分B)を簡略化して示す模式的平面図である。
図10は、図9のボンディングワイヤを削除して示す模式的平面図、
図11は、図9のe’−e’線に沿う模式的断面図、
図12は、図9のf’−f’線に沿う模式的断面図、
図13は、図9のg’−g’線に沿う模式的断面図、
図14乃至図16は、半導体装置の製造において、ワイヤボンディング工程を示す模式的平面図である。
1列目の複数の電極パッド3b1とこれに対応する複数の電極パッド6b(a)とを複数のボンディングワイヤ10b1で夫々電気的に接続する工程、2列目の複数の電極パッド3b2とこれに対応する複数の電極パッド6b(b)とを複数のボンディングワイヤ10b2で夫々電気的に接続する工程、及び3列目の複数の電極パッド3b3とこれに対応する複数の電極パッド6b(c)とを複数のボンディングワイヤ10b3で夫々電気的に接続する工程を、この順番で行う。
ボンディングワイヤ10b3と3列目の電極パッド3b3との接続、並びにボンディングワイヤ10b2と2列目の電極パッド3b2との接続は、ボンディグワイヤ10b1と1列目の電極パッド3b1との接続よりも半導体チップ5の第2の辺5bから離れた位置で行う。
図17は、本発明の実施例2である半導体装置の概略構成を示す模式的平面図であり、図18は、図17のボンディングワイヤを省略して示す模式的平面図である。
図19は、本発明の実施例3である半導体装置の概略構成を示す模式的平面図であり、図20は、図19のボンディングワイヤを省略して示す模式的平面図である。
図21は、本発明の実施例4である半導体装置の概略構成を示す模式的平面図である。
2…配線基板、3a1,3a2,3b1,3b2,3b3,3c,3d,3e…電極パッド(接続部)、4a,4b…配線、
5…半導体チップ、5a,5b,5c,5d…第1〜第4の辺、6a,6b,6c,6d…電極パッド(ボンディングパッド)、
7,8…半導体チップ、9…電極パッド(ボンディングパッド)、
10a1,10a2,10b1,10b2,10b3,10c,10d,10e…ボンディングワイヤ、11…樹脂封止体、12…半田バンプ。
Claims (4)
- 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)第1辺を有する上面と、前記上面に形成されたチップ搭載部と、前記第1辺に沿って配置され、かつ平面視において前記第1辺と前記チップ搭載部との間に配置された複数の第1接続部と、前記第1辺に沿って配置され、かつ平面視において前記第1辺と前記複数の第1接続部との間に配置された複数の第2接続部と、前記第1辺に沿って配置され、かつ平面視において前記第1辺と前記複数の第2接続部との間に配置された複数の第3接続部と、前記上面とは反対側の下面と、を備えた配線基板を準備する工程;
(b)第2辺を有する表面と、前記第2辺に沿って前記表面に形成された複数の電極パッドと、前記表面とは反対側の裏面と、を備えた半導体チップを、前記チップ搭載部に搭載する工程;
(c)前記複数の電極パッドのうちの複数の第1電極パッドと前記複数の第1接続部を、複数の第1ワイヤを介してそれぞれ電気的に接続する工程;
(d)前記(c)工程の後、前記複数の電極パッドのうちの第2電極パッドと前記複数の第2接続部のうちの一つを、第2ワイヤを介して電気的に接続する工程;
(e)前記(d)工程の後、前記複数の電極パッドのうちの第3電極パッドと前記複数の第3接続部のうちの一つを、第3ワイヤを介して電気的に接続する工程;
ここで、
前記複数の第1電極パッドは、外側電極パッドと、内側電極パッドとを有しており、
前記第2電極パッドは、平面視において、前記外側電極パッドと前記内側電極パッドの間に配置されており、
前記第3電極パッドは、平面視において、前記第2電極パッドと前記内側電極パッドの間に配置されており、
前記(d)工程では、前記第2ワイヤの一部が前記複数の第1ワイヤのそれぞれの上方に位置するように、第2ワイヤを介して電気的に接続し、
前記(e)工程では、前記第3ワイヤの一部が前記第2ワイヤの上方に位置するように、第3ワイヤを介して電気的に接続し、
前記複数の電極パッドのそれぞれの平面形状は、第1部分と、平面視において前記第1部分よりも前記第2辺から遠くに位置する第2部分とを有する長方形からなり、
前記(c)工程では、前記複数の第1ワイヤのそれぞれを前記複数の第1接続部のそれぞれの前記第1部分に接続し、
前記(e)工程では、前記第3ワイヤを前記第3接続部の前記第2部分に接続し、
前記複数の第1、第2および第3ワイヤは、平面視において、前記半導体チップの前記第2辺の中心部を経由し、かつ前記第2辺と直交する仮想線に対して鋭角をなす角度で、前記複数の電極パッドから延在している。 - 請求項1に記載の半導体装置の製造方法において、
前記(c)乃至(e)工程は、キャピラリを用いて行われることを特徴とする半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記(e)工程の後、前記半導体チップ、前記複数の第1ワイヤ、前記第2ワイヤおよび前記第3ワイヤを、樹脂で封止することを特徴とする半導体装置の製造方法。 - 請求項3に記載の半導体装置の製造方法において、
前記半導体チップ、前記複数の第1ワイヤ、前記第2ワイヤおよび前記第3ワイヤを前記樹脂で封止した後、複数の外部接続用端子を前記配線基板の前記下面に形成することを特徴とする半導体装置の製造方法。
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JPH09270535A (ja) * | 1996-03-29 | 1997-10-14 | Sanyo Electric Co Ltd | 半導体素子及びそれを用いる線状光源 |
JPH1074786A (ja) * | 1996-08-29 | 1998-03-17 | Nec Corp | 半導体装置及びその製造方法 |
JP2003338519A (ja) * | 2002-05-21 | 2003-11-28 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2007053121A (ja) * | 2005-08-12 | 2007-03-01 | Sharp Corp | 半導体装置、積層型半導体装置、及び配線基板 |
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JPH09270535A (ja) * | 1996-03-29 | 1997-10-14 | Sanyo Electric Co Ltd | 半導体素子及びそれを用いる線状光源 |
JPH1074786A (ja) * | 1996-08-29 | 1998-03-17 | Nec Corp | 半導体装置及びその製造方法 |
JP2003338519A (ja) * | 2002-05-21 | 2003-11-28 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2007053121A (ja) * | 2005-08-12 | 2007-03-01 | Sharp Corp | 半導体装置、積層型半導体装置、及び配線基板 |
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