JP2011101065A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2011101065A JP2011101065A JP2011038169A JP2011038169A JP2011101065A JP 2011101065 A JP2011101065 A JP 2011101065A JP 2011038169 A JP2011038169 A JP 2011038169A JP 2011038169 A JP2011038169 A JP 2011038169A JP 2011101065 A JP2011101065 A JP 2011101065A
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- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H01L2224/4805—Shape
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Abstract
【解決手段】 、半導体チップ3と、上記半導体チップ3が上面に搭載される第1導体1と、上記半導体チップ3と電気的に接続される第2導体2と、上記第1導体1、上記第2導体2、および上記半導体チップ3を、上記第1導体1の下面の一部、上記第2導体2の下面の一部を底面に露出させつつ封止する樹脂パッケージ5と、を備え、上記第1導体1および上記第2導体2のうち、少なくとも一方は、下面が上記樹脂パッケージ5の底面50に露出する厚肉部と、下面が上記樹脂パッケージ5の底面50から上方に離間している薄肉部15,21とを有しており、上記薄肉部15,21は、厚みが一様であり、かつ、その端面の少なくとも一部が上記樹脂パッケージ5の底面50と直交する平坦面となっている。
【選択図】 図2
Description
1 第1導体
11 (第1導体の)接続面
14 (第1導体の)端子面
15 薄肉部
2 第2導体
21 薄肉部
22 (第2導体の)接続面
24 (第2導体の)端子面
5 樹脂パッケージ
50 (樹脂パッケージの)底面
6 板状導体
6A (フープ状の)フレーム
6B (短寸の)フレーム
E2 貫通孔
e2 切欠
e3 スタンピング部
Claims (9)
- 半導体チップと、
上記半導体チップが上面に搭載される第1導体と、
上記半導体チップと電気的に接続される第2導体と、
上記第1導体、上記第2導体、および上記半導体チップを、上記第1導体の下面の一部、上記第2導体の下面の一部を底面に露出させつつ封止する樹脂パッケージと、を備えた半導体装置であって、
上記第1導体および上記第2導体のうち、少なくとも一方は、下面が上記樹脂パッケージの底面に露出する厚肉部と、下面が上記樹脂パッケージの底面から上方に離間している薄肉部とを有しており、
上記薄肉部は、厚みが一様であり、かつ、その端面の少なくとも一部は、上記樹脂パッケージの底面と直交する平坦面となっていることを特徴とする、半導体装置。 - 上記第1導体と上記第2導体の双方が上記厚肉部と上記薄肉部とを備える、請求項1に記載の半導体装置。
- 上記厚肉部と上記薄肉部とは、当該厚肉部から当該薄肉部にかけて連続する端面を有しており、当該連続する端面は、上記樹脂パッケージの底面と直交する平坦面となっている、請求項1または2に記載の半導体装置。
- 上記第1導体は、平面視矩形である、請求項1ないし3のいずれかに記載の半導体装置。
- 上記第1導体は、中央が上記厚肉部とされているとともに、当該第1導体の両側に、上記第2導体が配置されている、請求項1に記載の半導体装置。
- 上記第1導体は、その大部分が上記薄肉部とされている、請求項5に記載の半導体装置。
- 上記半導体チップは、上記第1導体の上面と上記第2導体の上面とにまたがって搭載されている、請求項1、2、3、5および6のいずれかに記載の半導体装置。
- 上記半導体チップと上記第2導体とは、ワイヤによって電気的に接続されている、請求項1ないし7のいずれかに記載の半導体装置。
- 上記薄肉部は、スタンピング加工によって形成され、上記薄肉部の端面は、打ち抜き加工によって形成されている、請求項1ないし8のいずれかに記載の半導体装置。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016503240A (ja) * | 2013-01-09 | 2016-02-01 | 日本テキサス・インスツルメンツ株式会社 | 集積回路モジュール |
JP2017111306A (ja) * | 2015-12-16 | 2017-06-22 | オムロン株式会社 | 電子装置及びその製造方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60103653A (ja) * | 1983-11-10 | 1985-06-07 | Nec Corp | 半導体装置の製造方法 |
JPH07147360A (ja) * | 1993-11-25 | 1995-06-06 | Sanyo Electric Co Ltd | 表面実装型半導体装置 |
JPH07147359A (ja) * | 1993-11-25 | 1995-06-06 | Sanyo Electric Co Ltd | 表面実装型半導体装置 |
JP2520482B2 (ja) * | 1989-08-04 | 1996-07-31 | 株式会社三井ハイテック | 半導体装置用リ―ドフレ―ムの製造方法 |
JPH09298256A (ja) * | 1996-03-07 | 1997-11-18 | Matsushita Electron Corp | 電子部品とその製造方法及びそれに用いるリードフレームと金型 |
JPH10335566A (ja) * | 1997-04-02 | 1998-12-18 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置とそれに用いられる回路部材、および樹脂封止型半導体装置の製造方法 |
JP2000311976A (ja) * | 1999-04-27 | 2000-11-07 | Nec Corp | 高周波バイポーラトランジスタ |
JP2001028420A (ja) * | 1999-07-14 | 2001-01-30 | Hitachi Ltd | 半導体装置及びその製造方法 |
-
2011
- 2011-02-24 JP JP2011038169A patent/JP5410465B2/ja not_active Expired - Lifetime
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60103653A (ja) * | 1983-11-10 | 1985-06-07 | Nec Corp | 半導体装置の製造方法 |
JP2520482B2 (ja) * | 1989-08-04 | 1996-07-31 | 株式会社三井ハイテック | 半導体装置用リ―ドフレ―ムの製造方法 |
JPH07147360A (ja) * | 1993-11-25 | 1995-06-06 | Sanyo Electric Co Ltd | 表面実装型半導体装置 |
JPH07147359A (ja) * | 1993-11-25 | 1995-06-06 | Sanyo Electric Co Ltd | 表面実装型半導体装置 |
JPH09298256A (ja) * | 1996-03-07 | 1997-11-18 | Matsushita Electron Corp | 電子部品とその製造方法及びそれに用いるリードフレームと金型 |
JPH10335566A (ja) * | 1997-04-02 | 1998-12-18 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置とそれに用いられる回路部材、および樹脂封止型半導体装置の製造方法 |
JP2000311976A (ja) * | 1999-04-27 | 2000-11-07 | Nec Corp | 高周波バイポーラトランジスタ |
JP2001028420A (ja) * | 1999-07-14 | 2001-01-30 | Hitachi Ltd | 半導体装置及びその製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016503240A (ja) * | 2013-01-09 | 2016-02-01 | 日本テキサス・インスツルメンツ株式会社 | 集積回路モジュール |
JP2017111306A (ja) * | 2015-12-16 | 2017-06-22 | オムロン株式会社 | 電子装置及びその製造方法 |
WO2017104300A1 (ja) * | 2015-12-16 | 2017-06-22 | オムロン株式会社 | 電子装置及びその製造方法 |
US10890813B2 (en) | 2015-12-16 | 2021-01-12 | Omron Corporation | Electronic device having a first electronic component and a second electronic component connected by wiring, and manufacturing method therefor |
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