JP2011097559A5 - - Google Patents

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Publication number
JP2011097559A5
JP2011097559A5 JP2010130632A JP2010130632A JP2011097559A5 JP 2011097559 A5 JP2011097559 A5 JP 2011097559A5 JP 2010130632 A JP2010130632 A JP 2010130632A JP 2010130632 A JP2010130632 A JP 2010130632A JP 2011097559 A5 JP2011097559 A5 JP 2011097559A5
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JP
Japan
Prior art keywords
value
signal
bit
soft
generating
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JP2010130632A
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English (en)
Japanese (ja)
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JP2011097559A (ja
JP5330319B2 (ja
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Priority claimed from US12/609,031 external-priority patent/US7974369B2/en
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Publication of JP2011097559A publication Critical patent/JP2011097559A/ja
Publication of JP2011097559A5 publication Critical patent/JP2011097559A5/ja
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Publication of JP5330319B2 publication Critical patent/JP5330319B2/ja
Expired - Fee Related legal-status Critical Current
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JP2010130632A 2009-10-30 2010-06-08 タイミング回復ループのための位相検出器 Expired - Fee Related JP5330319B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/609,031 2009-10-30
US12/609,031 US7974369B2 (en) 2009-10-30 2009-10-30 Phase detector for timing recovery loop

Publications (3)

Publication Number Publication Date
JP2011097559A JP2011097559A (ja) 2011-05-12
JP2011097559A5 true JP2011097559A5 (enExample) 2013-07-04
JP5330319B2 JP5330319B2 (ja) 2013-10-30

Family

ID=43522378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010130632A Expired - Fee Related JP5330319B2 (ja) 2009-10-30 2010-06-08 タイミング回復ループのための位相検出器

Country Status (6)

Country Link
US (1) US7974369B2 (enExample)
EP (1) EP2317515A3 (enExample)
JP (1) JP5330319B2 (enExample)
KR (1) KR101378007B1 (enExample)
CN (1) CN102055471B (enExample)
TW (1) TWI420878B (enExample)

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US8281224B1 (en) * 2008-10-20 2012-10-02 Link—A—Media Devices Corporation Programmable LBA and dummy bit reliabilities
US8429500B2 (en) * 2010-03-31 2013-04-23 Lsi Corporation Methods and apparatus for computing a probability value of a received value in communication or storage systems
US8149529B2 (en) * 2010-07-28 2012-04-03 Lsi Corporation Dibit extraction for estimation of channel parameters
US9135106B2 (en) * 2012-05-22 2015-09-15 Hgst Technologies Santa Ana, Inc. Read level adjustment using soft information
US8848308B2 (en) * 2013-03-04 2014-09-30 Lsi Corporation Systems and methods for ADC sample based inter-track interference compensation
US9281006B2 (en) 2013-12-13 2016-03-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for ATI characterization
US8917467B1 (en) 2013-12-13 2014-12-23 Lsi Corporation Systems and methods for ATI mitigation
US9240199B2 (en) 2014-03-12 2016-01-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for distortion characterization
US9083366B1 (en) 2014-03-12 2015-07-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Alignment of sampling phases in a multi-channel time-interleaved analog-to-digital converter
US9099157B1 (en) 2014-04-22 2015-08-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for adjacent track interference based re-writing
US9350526B2 (en) * 2014-10-27 2016-05-24 The United States Of America As Represented By The Secretary Of The Air Force Non-integer oversampled timing recovery for higher order quadrature modulation communication systems using in-phase samples
US9319217B1 (en) * 2014-10-28 2016-04-19 The United States Of America As Represented By The Secretary Of The Air Force Non-integer oversampled timing recovery for higher order quadrature modulation communication systems using quadrature-phase samples
US10277256B2 (en) * 2016-01-05 2019-04-30 Mediatek Inc. Decoding across transmission time intervals
US9882710B2 (en) * 2016-06-23 2018-01-30 Macom Connectivity Solutions, Llc Resolving interaction between channel estimation and timing recovery
US9641185B1 (en) * 2016-06-30 2017-05-02 Intel IP Corporation Digital time converter systems and method
US10135606B2 (en) 2016-10-27 2018-11-20 Macom Connectivity Solutions, Llc Mitigating interaction between adaptive equalization and timing recovery
US10050774B1 (en) * 2017-05-02 2018-08-14 MACOM Technology Solutions Holding, Inc. Mitigating interaction between adaptive equalization and timing recovery
US11979163B2 (en) * 2022-10-03 2024-05-07 Western Digital Technologies, Inc. Oversampled phase lock loop in a read channel

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4308000B4 (de) * 1993-03-13 2006-11-30 Robert Bosch Gmbh Verfahren zur entscheidungsrückgekoppelten Taktableitung
JP3428339B2 (ja) * 1996-12-11 2003-07-22 日本ビクター株式会社 位相同期制御回路
AU4515801A (en) * 1999-12-03 2001-06-18 Broadcom Corporation Viterbi slicer for turbo codes
DE60024261T2 (de) * 2000-08-28 2006-08-03 Sony Deutschland Gmbh Soft-Normalisierer für einen Kanaldekoder
JP3749889B2 (ja) * 2002-10-17 2006-03-01 株式会社東芝 Ｐｒｍｌ検出を適用する信号処理デバイス、同デバイスを備えたディスク記憶装置、及び同装置におけるフィードバック制御のための信号処理方法
US7239682B2 (en) * 2002-11-12 2007-07-03 Carnegie Mellon University Timing recovery system and method
ES2300748T3 (es) * 2004-02-19 2008-06-16 Thomson Licensing Metodo y aparato para recuperacion de portadora en un sistema de comunicaciones.
US7653155B1 (en) * 2004-11-04 2010-01-26 Sandia Corporation Using convolutional decoding to improve time delay and phase estimation in digital communications
EP2031791A1 (en) * 2007-08-30 2009-03-04 Deutsche Thomson OHG Apparatus and method for recovering data from a clocked input signal
TWI358204B (en) * 2007-12-12 2012-02-11 Ind Tech Res Inst All digital phase lock loop and method for control

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