TWI420878B - 用於時序回復迴路之相位偵測器 - Google Patents

用於時序回復迴路之相位偵測器 Download PDF

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Publication number
TWI420878B
TWI420878B TW099117070A TW99117070A TWI420878B TW I420878 B TWI420878 B TW I420878B TW 099117070 A TW099117070 A TW 099117070A TW 99117070 A TW99117070 A TW 99117070A TW I420878 B TWI420878 B TW I420878B
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TW
Taiwan
Prior art keywords
value
signal
values
bit
soft
Prior art date
Application number
TW099117070A
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English (en)
Chinese (zh)
Other versions
TW201116022A (en
Inventor
Jingfeng Liu
Hongwei Song
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Lsi Corp
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Publication date
Application filed by Lsi Corp filed Critical Lsi Corp
Publication of TW201116022A publication Critical patent/TW201116022A/zh
Application granted granted Critical
Publication of TWI420878B publication Critical patent/TWI420878B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10268—Improvement or modification of read or write signals bit detection or demodulation methods
    • G11B20/10287—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors
    • G11B20/10296—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors using the Viterbi algorithm
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00—Record carriers by type
    • G11B2220/20—Disc-shaped record carriers
    • G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
    • G11B2220/2508—Magnetic discs
    • G11B2220/2516—Hard disks

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
TW099117070A 2009-10-30 2010-05-27 用於時序回復迴路之相位偵測器 TWI420878B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/609,031 US7974369B2 (en) 2009-10-30 2009-10-30 Phase detector for timing recovery loop

Publications (2)

Publication Number Publication Date
TW201116022A TW201116022A (en) 2011-05-01
TWI420878B true TWI420878B (zh) 2013-12-21

Family

ID=43522378

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099117070A TWI420878B (zh) 2009-10-30 2010-05-27 用於時序回復迴路之相位偵測器

Country Status (6)

Country Link
US (1) US7974369B2 (enExample)
EP (1) EP2317515A3 (enExample)
JP (1) JP5330319B2 (enExample)
KR (1) KR101378007B1 (enExample)
CN (1) CN102055471B (enExample)
TW (1) TWI420878B (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8281224B1 (en) * 2008-10-20 2012-10-02 Link—A—Media Devices Corporation Programmable LBA and dummy bit reliabilities
US8429500B2 (en) * 2010-03-31 2013-04-23 Lsi Corporation Methods and apparatus for computing a probability value of a received value in communication or storage systems
US8149529B2 (en) * 2010-07-28 2012-04-03 Lsi Corporation Dibit extraction for estimation of channel parameters
US9135106B2 (en) * 2012-05-22 2015-09-15 Hgst Technologies Santa Ana, Inc. Read level adjustment using soft information
US8848308B2 (en) * 2013-03-04 2014-09-30 Lsi Corporation Systems and methods for ADC sample based inter-track interference compensation
US9281006B2 (en) 2013-12-13 2016-03-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for ATI characterization
US8917467B1 (en) 2013-12-13 2014-12-23 Lsi Corporation Systems and methods for ATI mitigation
US9240199B2 (en) 2014-03-12 2016-01-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for distortion characterization
US9083366B1 (en) 2014-03-12 2015-07-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Alignment of sampling phases in a multi-channel time-interleaved analog-to-digital converter
US9099157B1 (en) 2014-04-22 2015-08-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for adjacent track interference based re-writing
US9350526B2 (en) * 2014-10-27 2016-05-24 The United States Of America As Represented By The Secretary Of The Air Force Non-integer oversampled timing recovery for higher order quadrature modulation communication systems using in-phase samples
US9319217B1 (en) * 2014-10-28 2016-04-19 The United States Of America As Represented By The Secretary Of The Air Force Non-integer oversampled timing recovery for higher order quadrature modulation communication systems using quadrature-phase samples
US10277256B2 (en) * 2016-01-05 2019-04-30 Mediatek Inc. Decoding across transmission time intervals
US9882710B2 (en) * 2016-06-23 2018-01-30 Macom Connectivity Solutions, Llc Resolving interaction between channel estimation and timing recovery
US9641185B1 (en) * 2016-06-30 2017-05-02 Intel IP Corporation Digital time converter systems and method
US10135606B2 (en) 2016-10-27 2018-11-20 Macom Connectivity Solutions, Llc Mitigating interaction between adaptive equalization and timing recovery
US10050774B1 (en) * 2017-05-02 2018-08-14 MACOM Technology Solutions Holding, Inc. Mitigating interaction between adaptive equalization and timing recovery
US11979163B2 (en) * 2022-10-03 2024-05-07 Western Digital Technologies, Inc. Oversampled phase lock loop in a read channel

Citations (4)

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Publication number Priority date Publication date Assignee Title
DE4308000A1 (de) * 1993-03-13 1994-09-15 Bosch Gmbh Robert Verfahren zur entscheidungsrückgekoppelten Taktableitung
US20040076245A1 (en) * 2002-10-17 2004-04-22 Kabushiki Kaisha Toshiba Signal processing device utilizing partial response maximum likelihood detection
EP2031791A1 (en) * 2007-08-30 2009-03-04 Deutsche Thomson OHG Apparatus and method for recovering data from a clocked input signal
TW200926602A (en) * 2007-12-12 2009-06-16 Ind Tech Res Inst All digital phase lock loop and method for controlling a phase lock loop

Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
JP3428339B2 (ja) * 1996-12-11 2003-07-22 日本ビクター株式会社 位相同期制御回路
AU4515801A (en) * 1999-12-03 2001-06-18 Broadcom Corporation Viterbi slicer for turbo codes
DE60024261T2 (de) * 2000-08-28 2006-08-03 Sony Deutschland Gmbh Soft-Normalisierer für einen Kanaldekoder
US7239682B2 (en) * 2002-11-12 2007-07-03 Carnegie Mellon University Timing recovery system and method
ES2300748T3 (es) * 2004-02-19 2008-06-16 Thomson Licensing Metodo y aparato para recuperacion de portadora en un sistema de comunicaciones.
US7653155B1 (en) * 2004-11-04 2010-01-26 Sandia Corporation Using convolutional decoding to improve time delay and phase estimation in digital communications

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4308000A1 (de) * 1993-03-13 1994-09-15 Bosch Gmbh Robert Verfahren zur entscheidungsrückgekoppelten Taktableitung
US20040076245A1 (en) * 2002-10-17 2004-04-22 Kabushiki Kaisha Toshiba Signal processing device utilizing partial response maximum likelihood detection
EP2031791A1 (en) * 2007-08-30 2009-03-04 Deutsche Thomson OHG Apparatus and method for recovering data from a clocked input signal
TW200926602A (en) * 2007-12-12 2009-06-16 Ind Tech Res Inst All digital phase lock loop and method for controlling a phase lock loop

Also Published As

Publication number Publication date
EP2317515A2 (en) 2011-05-04
JP2011097559A (ja) 2011-05-12
CN102055471A (zh) 2011-05-11
KR101378007B1 (ko) 2014-03-27
US7974369B2 (en) 2011-07-05
US20110103527A1 (en) 2011-05-05
KR20110047961A (ko) 2011-05-09
EP2317515A3 (en) 2011-05-25
JP5330319B2 (ja) 2013-10-30
TW201116022A (en) 2011-05-01
CN102055471B (zh) 2015-05-20

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