JP2011097082A - 自己整合損傷層を有するデバイス構造体の形成方法 - Google Patents
自己整合損傷層を有するデバイス構造体の形成方法 Download PDFInfo
- Publication number
- JP2011097082A JP2011097082A JP2011001856A JP2011001856A JP2011097082A JP 2011097082 A JP2011097082 A JP 2011097082A JP 2011001856 A JP2011001856 A JP 2011001856A JP 2011001856 A JP2011001856 A JP 2011001856A JP 2011097082 A JP2011097082 A JP 2011097082A
- Authority
- JP
- Japan
- Prior art keywords
- doped region
- substrate
- crystal damage
- semiconductor material
- ions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 239000000463 material Substances 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 239000013078 crystal Substances 0.000 claims description 115
- 150000002500 ions Chemical class 0.000 claims description 45
- 238000002513 implantation Methods 0.000 claims description 27
- 239000011261 inert gas Substances 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 230000007547 defect Effects 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 2
- 239000012466 permeate Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 168
- 108091006146 Channels Proteins 0.000 description 30
- 230000008569 process Effects 0.000 description 25
- 239000011800 void material Substances 0.000 description 22
- 230000005669 field effect Effects 0.000 description 14
- 239000004020 conductor Substances 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 10
- 125000006850 spacer group Chemical group 0.000 description 9
- 125000004429 atom Chemical group 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 5
- 239000007943 implant Substances 0.000 description 5
- 230000005865 ionizing radiation Effects 0.000 description 5
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000001629 suppression Effects 0.000 description 4
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012777 electrically insulating material Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000001016 Ostwald ripening Methods 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
【解決手段】デバイス構造体は、基板の半導体材料内部に画定された第1導電型の第1及び第2ドープ領域を有する。逆の導電型の第3ドープ領域が、横方向に第1ドープ領域を第2ドープ領域から分離する。ゲート構造部が基板の上表面に配置され、第3ドープ領域と垂直方向で重なる関係を有する。第1結晶損傷層は基板の半導体材料の内部に画定される。第1結晶損傷層は、基板の半導体材料によって取り囲まれた第1の複数のボイドを有する。第1ドープ領域は、第1結晶損傷層と基板の上表面との垂直方向の間に配置される。第1結晶損傷層は横方向に第3ドープ領域内には延びない。
【選択図】 図7
Description
14:基板
15:井戸(ウェル)
16:ゲート誘電体層
18:ゲート導電体層
20:ハードマスク層
22:基板14の上表面
24:レジスト層
25、27:ゲート電極26の側壁
26:ゲート電極
28:ゲート誘電体
30:ゲート構造部
32、34:側壁スペーサ
35、39:接合部(界面)
36:ソース領域
37:チャネル領域
38:ドレイン領域
40:注入マスク
42、48:イオン(一方向矢印)
44:ゲート電極26の上表面
46a、46b、52a、52b、54a、54b:結晶損傷層
47、49:結晶損傷層の端部
50、53、55:ボイド
56、58:導電層
60:誘電体層
62、64、66:コンタクト
65:デバイス構造体
Claims (13)
- 半導体材料で構成される基板の内部にデバイス構造体を製造する方法であって、
前記基板の前記半導体材料内に第1導電型の第1ドープ領域を形成するステップと、
前記半導体材料内の前記第1導電型の第2ドープ領域であって、前記第1導電型とは逆の第2導電型を有する第3ドープ領域によって前記第1ドープ領域から横方向に分離される、前記第2ドープ領域を形成するステップと、
前記基板の上表面の上にある、前記第3ドープ領域と垂直方向に重なる関係を有するゲート構造部を形成するステップと、
前記基板の前記半導体材料によって取り囲まれた第1の複数のボイドを形成して第1結晶損傷層を画定するステップと
を含み、
前記第1結晶損傷層は、前記第1ドープ領域の少なくとも一部分により前記上表面から分離され、前記第3ドープ領域内に横方向に有意な距離は延びない、
方法。 - 前記第1の複数のボイドを形成するステップは、
不活性気体の第1の複数のイオンを、第1運動エネルギーにおいて第1ドーズ量で前記基板内に注入するステップと、
前記基板をアニールして前記第1の複数のイオンにより前記半導体材料内に生成された点欠陥を前記第1の複数のボイド内に凝集させるステップと
をさらに含む、請求項1に記載の方法。 - 前記注入された第1の複数のイオンからの前記不活性気体の原子は、前記点欠陥と共に前記第1の複数のボイド内に凝集され、その結果前記第1の複数のボイドの少なくとも一部は前記不活性気体の1つ又は複数の原子を含む、請求項2に記載の方法。
- 前記ゲート構造部は前記基板の前記上表面の上に形成され、
前記ゲート構造部及び前記上表面の上にレジスト層を塗布するステップと、
前記レジスト層をパターン付けして前記第1ドープ領域の上にある前記上表面の第1領域を露出させるステップと、
前記不活性気体の前記第1の複数のイオンの注入の間、前記ゲート構造部および前記レジスト層を、前記第3ドープ領域を覆う注入マスクとして用いて、前記第1結晶損傷層の終端部を前記ゲート構造部の第1側壁と垂直方向において概ね位置合せするステップと
をさらに含む、
請求項2に記載の方法。 - 前記注入マスクを用いて、前記不活性気体の第2の複数のイオンを、第1運動エネルギーとは異なる第2運動エネルギーにおいて第2ドーズ量で前記基板内に注入して第2の複数のボイドを形成し第2結晶損傷層を画定するステップをさらに含み、
前記第2結晶損傷層は、前記ゲート構造部の前記第1側壁と垂直方向において概ね位置合せされた端部を有し、前記第1ドープ領域の少なくとも一部分によって前記基板の前記上表面から分離される、
請求項4に記載の方法。 - 前記レジスト層は、前記第2ドープ領域の上にある前記上表面の第2領域を露出させるようにパターン付けされ、
前記不活性気体の前記第1の複数のイオンの一部が前記上表面の前記第2領域を通して前記第2ドープ領域に浸透することを可能にして、第2の複数のボイドを形成し第2結晶損傷層を画定するステップをさらに含み、
前記第2結晶損傷層は、前記ゲート構造部の第2側壁に概ね位置合せされた終端部を有し、前記第3ドープ領域によって前記第1結晶損傷層から横方向に分離される、
請求項4に記載の方法。 - 前記第1導電型の前記第1ドープ領域を形成するステップは、
前記注入マスクを用いて、不純物種の複数のイオンを前記基板の前記半導体材料の内部に注入し、前記基板の前記半導体材料をドープして前記第1ドープ領域にするステップをさらに含む、
請求項4に記載の方法。 - 前記第1ドープ領域と前記第3ドープ領域は界面に沿って交わり、前記第1結晶損傷層は前記界面に概ね位置合せされた終端部を有する、請求項1に記載の方法。
- 半導体材料で構成される基板の内部に第1導電型の第1ドープ領域および第2ドープ領域と前記第1導電型とは逆の第2導電型の第3ドープ領域とを備えるデバイス構造体を製造する方法であって、
前記基板の上表面の上にある、前記第3ドープ領域と垂直方向に重なる関係を有するゲート構造部を形成するステップと、
前記ゲート構造部及び前記上表面の上にレジスト層を塗布し、該レジスト層をパターン付けして前記第1ドープ領域の上にある前記上表面の第1領域と前記第2ドープ領域の上にある前記上表面の第2領域を露出させ、前記第3ドープ領域を覆う注入マスクを形成するステップと、
前記注入マスクを用いて、不純物種の複数のイオンを前記基板の前記半導体材料の内部に注入し、前記基板の前記半導体材料をドープして、前記第1ドープ領域と、前記第3ドープ領域によって前記第1ドープ領域から横方向に分離される、前記第2ドープ領域とを形成するステップであって、前記第1ドープ領域および前記第2ドープ領域は、前記第3ドープ領域において実質的に垂直な界面と水平縁部とを備える湾曲した境界を形成するステップと、
前記注入マスクを用いて、不活性気体の第1の複数のイオンを、第1運動エネルギーにおいて第1ドーズ量で前記基板内に注入して前記基板の前記半導体材料によって取り囲まれた第1の複数のボイドを形成し、前記第1ドープ領域および前記第2ドープ領域の内部で前記上表面と前記界面の水平縁部との間の深さに第1結晶損傷層を画定するステップと、
前記不活性気体の第2の複数のイオンを、第1運動エネルギーとは異なる第2運動エネルギーにおいて第2ドーズ量で前記基板内に注入して前記基板の前記半導体材料によって取り囲まれた第2の複数のボイドを形成し、前記界面の水平縁部よりも深い位置に第2結晶損傷層を画定するステップと、
を含み、
前記第1結晶損傷層は、前記第1ドープ領域の少なくとも一部分により前記上表面から分離され、前記第1および第2結晶損傷層は、前記第3ドープ領域内に横方向に有意な距離は延びず、
前記第2導電型はp型の導電性であり、従って前記第3ドープ領域内の前記半導体材料はp型導電性を有し、前記第1結晶損傷層は圧縮性応力を前記第3ドープ領域に効果的に伝達する、
方法。 - 前記複数のボイドの形成は、
前記基板をアニールして前記不活性気体の複数のイオンにより前記半導体材料内に生成された点欠陥を前記複数のボイド内に凝集させる、請求項9に記載の方法。 - 注入された前記不活性気体の原子は、前記点欠陥と共に前記複数のボイド内に凝集され、その結果前記複数のボイドの少なくとも一部は前記不活性気体の1つ又は複数の原子を含む、請求項10に記載の方法。
- 前記不活性気体の前記複数のイオンの注入の間、前記ゲート構造部および前記レジスト層を、前記第3ドープ領域を覆う注入マスクとして用いることによって、前記第1結晶損傷層の終端部を前記ゲート構造部の第1側壁と垂直方向において概ね位置合せし、前記第2結晶損傷層の終端部を前記ゲート構造部の第2側壁と垂直方向において概ね位置合せする、
請求項10に記載の方法。 - 前記第1および第2結晶損傷層は前記界面に概ね位置合せされた終端部を有する、請求項9に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/178766 | 2008-07-24 | ||
US12/178,766 US7795679B2 (en) | 2008-07-24 | 2008-07-24 | Device structures with a self-aligned damage layer and methods for forming such device structures |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008287315A Division JP4782821B2 (ja) | 2008-07-24 | 2008-11-10 | 自己整合損傷層を有するデバイス構造体 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011097082A true JP2011097082A (ja) | 2011-05-12 |
JP5385926B2 JP5385926B2 (ja) | 2014-01-08 |
Family
ID=40578806
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008287315A Expired - Fee Related JP4782821B2 (ja) | 2008-07-24 | 2008-11-10 | 自己整合損傷層を有するデバイス構造体 |
JP2011001856A Expired - Fee Related JP5385926B2 (ja) | 2008-07-24 | 2011-01-07 | 自己整合損傷層を有するデバイス構造体の形成方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008287315A Expired - Fee Related JP4782821B2 (ja) | 2008-07-24 | 2008-11-10 | 自己整合損傷層を有するデバイス構造体 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7795679B2 (ja) |
EP (1) | EP2148372B1 (ja) |
JP (2) | JP4782821B2 (ja) |
CN (1) | CN101635312B (ja) |
AT (1) | ATE514189T1 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102005414B (zh) * | 2009-08-28 | 2012-12-12 | 中芯国际集成电路制造(上海)有限公司 | Cmos图像传感器像素、制造方法及图像捕获设备 |
US10128115B2 (en) * | 2010-02-26 | 2018-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming ultra-shallow junctions in semiconductor devices |
CN102468164B (zh) * | 2010-10-29 | 2014-10-08 | 中国科学院微电子研究所 | 晶体管及其制造方法 |
JP2014056881A (ja) * | 2012-09-11 | 2014-03-27 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
US9721853B2 (en) * | 2013-03-13 | 2017-08-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for forming a semiconductor device |
CN105448913A (zh) * | 2014-06-23 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Cmos器件及其形成方法 |
US10833175B2 (en) * | 2015-06-04 | 2020-11-10 | International Business Machines Corporation | Formation of dislocation-free SiGe finFET using porous silicon |
CN106486376A (zh) * | 2015-08-31 | 2017-03-08 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应管及其制作方法 |
JP6611532B2 (ja) | 2015-09-17 | 2019-11-27 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
CN107492487B (zh) * | 2016-06-13 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
JP7328221B2 (ja) * | 2017-12-01 | 2023-08-16 | シリコン ジェネシス コーポレーション | 三次元集積回路 |
US11133227B2 (en) * | 2018-12-20 | 2021-09-28 | Xia Tai Xin Semiconductor (Qing Dao) Ltd. | Semiconductor device having active region and method for fabricating the same |
US11164867B2 (en) * | 2019-08-07 | 2021-11-02 | Globalfoundries U.S. Inc. | Fin-type field-effect transistors over one or more buried polycrystalline layers |
US11315825B2 (en) | 2019-08-28 | 2022-04-26 | Globalfoundries U.S. Inc. | Semiconductor structures including stacked depleted and high resistivity regions |
US10971633B2 (en) * | 2019-09-04 | 2021-04-06 | Stmicroelectronics (Rousset) Sas | Structure and method of forming a semiconductor device |
US11860417B2 (en) * | 2019-09-09 | 2024-01-02 | Cisco Technology, Inc. | Precision spacing control for optical waveguides |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0845869A (ja) * | 1994-07-25 | 1996-02-16 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | 特に集積化された電子装置における電荷キャリアの寿命の局所化される短縮のための処理、および電荷キャリアの寿命の局所化される短縮を伴う集積化された電子装置 |
JPH1167682A (ja) * | 1997-08-08 | 1999-03-09 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2000012547A (ja) * | 1998-06-26 | 2000-01-14 | Nec Corp | 半導体装置およびその製造方法 |
US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
US20040014304A1 (en) * | 2002-07-18 | 2004-01-22 | Micron Technology, Inc. | Stable PD-SOI devices and methods |
US20040166624A1 (en) * | 2003-02-21 | 2004-08-26 | International Business Machines Corporation | Cmos performance enhancement using localized voids and extended defects |
US7282414B2 (en) * | 2004-05-18 | 2007-10-16 | Industrial Technology Research Institute | Fabrication methods for compressive strained-silicon and transistors using the same |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4766482A (en) * | 1986-12-09 | 1988-08-23 | General Electric Company | Semiconductor device and method of making the same |
US6228694B1 (en) * | 1999-06-28 | 2001-05-08 | Intel Corporation | Method of increasing the mobility of MOS transistors by use of localized stress regions |
KR20040007025A (ko) * | 2002-07-16 | 2004-01-24 | 주식회사 하이닉스반도체 | 반도체 웨이퍼 제조 방법 |
US7022544B2 (en) * | 2002-12-18 | 2006-04-04 | International Business Machines Corporation | High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same |
KR20070069160A (ko) | 2004-10-29 | 2007-07-02 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | 서로 다른 스트레인드 채널 영역들을 갖는 반도체 영역들을포함하는 반도체 디바이스 및 이를 제조하는 방법 |
US7432553B2 (en) * | 2005-01-19 | 2008-10-07 | International Business Machines Corporation | Structure and method to optimize strain in CMOSFETs |
US20070158779A1 (en) * | 2006-01-12 | 2007-07-12 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a buried damage layer |
-
2008
- 2008-07-24 US US12/178,766 patent/US7795679B2/en not_active Expired - Fee Related
- 2008-10-21 EP EP08167167A patent/EP2148372B1/en not_active Not-in-force
- 2008-10-21 AT AT08167167T patent/ATE514189T1/de not_active IP Right Cessation
- 2008-11-10 JP JP2008287315A patent/JP4782821B2/ja not_active Expired - Fee Related
-
2009
- 2009-07-24 CN CN2009101601442A patent/CN101635312B/zh not_active Expired - Fee Related
-
2011
- 2011-01-07 JP JP2011001856A patent/JP5385926B2/ja not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0845869A (ja) * | 1994-07-25 | 1996-02-16 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | 特に集積化された電子装置における電荷キャリアの寿命の局所化される短縮のための処理、および電荷キャリアの寿命の局所化される短縮を伴う集積化された電子装置 |
JPH1167682A (ja) * | 1997-08-08 | 1999-03-09 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2000012547A (ja) * | 1998-06-26 | 2000-01-14 | Nec Corp | 半導体装置およびその製造方法 |
US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
US20040014304A1 (en) * | 2002-07-18 | 2004-01-22 | Micron Technology, Inc. | Stable PD-SOI devices and methods |
US20040166624A1 (en) * | 2003-02-21 | 2004-08-26 | International Business Machines Corporation | Cmos performance enhancement using localized voids and extended defects |
US7282414B2 (en) * | 2004-05-18 | 2007-10-16 | Industrial Technology Research Institute | Fabrication methods for compressive strained-silicon and transistors using the same |
Also Published As
Publication number | Publication date |
---|---|
EP2148372B1 (en) | 2011-06-22 |
CN101635312B (zh) | 2012-05-16 |
JP4782821B2 (ja) | 2011-09-28 |
JP5385926B2 (ja) | 2014-01-08 |
JP2010034488A (ja) | 2010-02-12 |
US7795679B2 (en) | 2010-09-14 |
EP2148372A1 (en) | 2010-01-27 |
CN101635312A (zh) | 2010-01-27 |
US20100019330A1 (en) | 2010-01-28 |
ATE514189T1 (de) | 2011-07-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5385926B2 (ja) | 自己整合損傷層を有するデバイス構造体の形成方法 | |
CN101714526B (zh) | 半导体元件的制造方法 | |
US8513106B2 (en) | Pseudo butted junction structure for back plane connection | |
CN103247535A (zh) | 用于finfet器件的位错smt | |
US9379104B1 (en) | Method to make gate-to-body contact to release plasma induced charging | |
US20140110767A1 (en) | Bulk finfet well contacts with fin pattern uniformity | |
US8466030B2 (en) | Semiconductor device and fabricating method thereof | |
KR100596444B1 (ko) | 반도체 소자 및 그의 제조방법 | |
US9871035B2 (en) | Semiconductor device with metal silicide blocking region and method of manufacturing the same | |
JP2012028562A (ja) | 半導体装置の製造方法 | |
US7402478B2 (en) | Method of fabricating dual gate electrode of CMOS semiconductor device | |
US20140021552A1 (en) | Strain Adjustment in the Formation of MOS Devices | |
CN107180764B (zh) | 一种半导体器件及其制造方法、电子装置 | |
JP5205779B2 (ja) | 半導体装置の製造方法および半導体装置 | |
JP2005026661A (ja) | リフレッシュタイムを改善させた半導体素子の製造方法 | |
US20050153498A1 (en) | Method of manufacturing p-channel MOS transistor and CMOS transistor | |
US20050208726A1 (en) | Spacer approach for CMOS devices | |
WO2016168994A1 (zh) | 隧穿晶体管及隧穿晶体管的制备方法 | |
CN107919368A (zh) | 一种半导体器件及其制造方法、电子装置 | |
KR100247816B1 (ko) | 반도체장치의 제조방법 | |
JP2012038749A (ja) | 半導体装置およびその製造方法 | |
KR100546124B1 (ko) | 반도체소자의 트랜지스터 형성방법 | |
KR20060019367A (ko) | 보이드가 없는 게이트 전극을 구비한 mos 트랜지스터의제조방법 | |
WO2010029681A1 (ja) | 半導体装置及びその製造方法 | |
JP3956879B2 (ja) | 半導体集積回路装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121218 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130318 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130423 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130717 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130910 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20130910 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131004 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |